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mb/google/brya/var/crota: Add reset and enable delay time for rtd3-cold

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This CL adds the delay time into the RTD3 sequence, which will turn
off the eMMC controller (a true D3cold state) during the RTD3 sequence.
We checked power on sequence requires enable pin prior to reset pin
delay of 50ms and add delay of 20ms to meet the sequence on various
eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in
chapter 7.2.

BUG=b:231291431
TEST=USE="project_crota" emerge-brya coreboot chromeos-bootimage

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Id9bed46e801602f3f327753053ec6a1ceb0656e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Terry Chen
2022-05-16 20:55:05 +08:00
committed by Felix Held
parent 2afcbc1b21
commit 9686ac2261
1 changed files with 2 additions and 0 deletions
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2
src/mainboard/google/brya/variants/crota/overridetree.cb
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@@ -88,6 +88,8 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
register "srcclk_pin" = "1" register "srcclk_pin" = "1"
register "reset_delay_ms" = "50"
register "enable_delay_ms" = "20"
device generic 0 alias emmc_rtd3 on end device generic 0 alias emmc_rtd3 on end
end end
# Enable PCIe-to-eMMC bridge PCIE 3 using clk 1 # Enable PCIe-to-eMMC bridge PCIE 3 using clk 1