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soc/intel/xeon_sp: Update FSP-T UPD for FSP2.4

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FSP2.4 and previous FSP versions have different FSP-T UPD
parameter settings.

Change-Id: I48384944ac69636cca2acd8169d3dd15f90362ec
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81313
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Li, Jincheng 2023-03-01 18:25:49 +08:00 committed by Lean Sheng Tan
parent 3199802045
commit 969f04fb34
1 changed files with 27 additions and 0 deletions
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27
src/soc/intel/xeon_sp/bootblock.c
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@ -14,6 +14,32 @@
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#if (CONFIG(PLATFORM_USES_FSP2_4))
const FSPT_UPD temp_ram_init_params = {
.FspUpdHeader = {
.Signature = FSPT_UPD_SIGNATURE,
.Revision = 2,
.Reserved = {0},
},
.FsptArchUpd = {
.Revision = 2,
.Length = 32,
.FspDebugHandler = 0,
.Reserved1 = {0},
},
.FsptCoreUpd = {
.MicrocodeRegionBase = 0,
.MicrocodeRegionLength = 0,
.CodeRegionBase = (UINT64)CACHE_ROM_BASE,
.CodeRegionLength = (UINT64)CACHE_ROM_SIZE,
},
.FsptConfig = {
.FsptPort80RouteDisable = 0,
.ReservedTempRamInitUpd = {0},
},
.UpdTerminator = 0x55AA,
};
#else
const FSPT_UPD temp_ram_init_params = {
.FspUpdHeader = {
.Signature = FSPT_UPD_SIGNATURE,
@ -34,6 +60,7 @@ const FSPT_UPD temp_ram_init_params = {
.UnusedUpdSpace0 = {0},
.UpdTerminator = 0x55AA,
};
#endif //(!CONFIG(PLATFORM_USES_FSP2_4))
static uint64_t assembly_timestamp;
static uint64_t bootblock_timestamp;