From 97014a5ab9413ffcb769b392004885c133adbced Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Wed, 8 Sep 2021 15:04:48 -0600 Subject: [PATCH] soc/intel/tigerlake: Remove write to IOP TCSS_IN_D3 Change-Id: Ibbf6b5e0bf627536d10c8dee2f632e66da427151 Signed-off-by: Jeremy Soller Signed-off-by: Tim Crawford --- src/soc/intel/tigerlake/acpi/tcss.asl | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 2a71b31cae..f686d1af48 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -354,12 +354,6 @@ Scope (\_SB.PCI0) Offset(0x10), RBAR, 64 /* RegBar, offset 0x7110 in MCHBAR */ } - Field (MBAR, DWordAcc, NoLock, Preserve) - { - Offset(0x304), /* PRIMDN_MASK1_0_0_0_MCHBAR_IMPH, offset 0x7404 */ - , 31, - TCD3, 1 /* [31:31] TCSS IN D3 bit */ - } /* * Operation region defined to access the pCode mailbox interface. Get the MCHBAR @@ -689,11 +683,6 @@ Scope (\_SB.PCI0) } Else { - /* - * Program IOP MCTP Drop (TCSS_IN_D3) after D3 cold exit and - * acknowledgement by IOM. - */ - TCD3 = 0 /* * If the TCSS Deven is cleared by BIOS Mailbox request, then * restore to previously saved value of TCSS DEVNE. @@ -741,11 +730,6 @@ Scope (\_SB.PCI0) } } - /* - * Program IOM MCTP Drop (TCSS_IN_D3) in D3Cold entry before entering D3 cold. - */ - TCD3 = 1 - /* Request IOM for D3 cold entry sequence. */ TD3C = 1 }