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arch/x86: consolidate HPET base address definitions

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Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and
the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO
region which is 0xfed00000 on all chipsets and SoCs in the coreboot
tree. Since these two different constants are used in different places
that however might end up used in the same coreboot build, drop the
Kconfig option and use the definition from arch/x86 instead. Since it's
no longer needed to check for a mismatch of those two constants, the
corresponding checks are dropped too.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held
2022-02-23 16:32:20 +01:00
parent 887d4ed912
commit 972d9f2cce
30 changed files with 81 additions and 71 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/southbridge/intel/bd82x6x/acpi/lpc.asl
View File

@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hpet.h>
// Intel LPC Bus Device - 0:1f.0
Device (LPCB)
@@ -78,7 +80,7 @@ Device (LPCB)
Name(BUF0, ResourceTemplate()
{
Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
})
Method (_STA, 0) // Device Status
@@ -91,15 +93,15 @@ Device (LPCB)
If (HPTE) {
CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
If (Lequal(HPAS, 1)) {
HPT0 = CONFIG_HPET_ADDRESS + 0x1000
HPT0 = HPET_BASE_ADDRESS + 0x1000
}
If (Lequal(HPAS, 2)) {
HPT0 = CONFIG_HPET_ADDRESS + 0x2000
HPT0 = HPET_BASE_ADDRESS + 0x2000
}
If (Lequal(HPAS, 3)) {
HPT0 = CONFIG_HPET_ADDRESS + 0x3000
HPT0 = HPET_BASE_ADDRESS + 0x3000
}
}

7
src/southbridge/intel/i82801dx/lpc.c
View File

@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hpet.h>
#include <arch/io.h>
#include <arch/ioapic.h>
#include <console/console.h>
@@ -213,7 +214,7 @@ static void enable_hpet(struct device *dev)
u32 reg32, hpet, val;
/* Set HPET base address and enable it */
printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", CONFIG_HPET_ADDRESS);
printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", HPET_BASE_ADDRESS);
reg32 = pci_read_config32(dev, GEN_CNTL);
/*
* Bit 17 is HPET enable bit.
@@ -221,7 +222,7 @@ static void enable_hpet(struct device *dev)
*/
reg32 &= ~(3 << 15); /* Clear it */
hpet = CONFIG_HPET_ADDRESS >> 12;
hpet = HPET_BASE_ADDRESS >> 12;
hpet &= 0x3;
reg32 |= (hpet << 15);
@@ -234,7 +235,7 @@ static void enable_hpet(struct device *dev)
val &= 0x7;
if ((val & 0x4) && (hpet == (val & 0x3))) {
printk(BIOS_INFO, "HPET enabled at 0x%x\n", CONFIG_HPET_ADDRESS);
printk(BIOS_INFO, "HPET enabled at 0x%x\n", HPET_BASE_ADDRESS);
} else {
printk(BIOS_WARNING, "HPET was not enabled correctly\n");
reg32 &= ~(1 << 17); /* Clear Enable */

10
src/southbridge/intel/i82801gx/acpi/lpc.asl
View File

@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hpet.h>
// Intel LPC Bus Device - 0:1f.0
Device (LPCB)
@@ -60,7 +62,7 @@ Device (LPCB)
Name(BUF0, ResourceTemplate()
{
Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
})
Method (_STA, 0) // Device Status
@@ -73,15 +75,15 @@ Device (LPCB)
If (HPTE) {
CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
If (HPAS == 1) {
HPT0 = CONFIG_HPET_ADDRESS + 0x1000
HPT0 = HPET_BASE_ADDRESS + 0x1000
}
If (HPAS == 2) {
HPT0 = CONFIG_HPET_ADDRESS + 0x2000
HPT0 = HPET_BASE_ADDRESS + 0x2000
}
If (HPAS == 3) {
HPT0 = CONFIG_HPET_ADDRESS + 0x3000
HPT0 = HPET_BASE_ADDRESS + 0x3000
}
}

10
src/southbridge/intel/i82801ix/acpi/lpc.asl
View File

@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hpet.h>
// Intel LPC Bus Device - 0:1f.0
Device (LPCB)
@@ -60,7 +62,7 @@ Device (LPCB)
Name(BUF0, ResourceTemplate()
{
Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
})
Method (_STA, 0) // Device Status
@@ -73,15 +75,15 @@ Device (LPCB)
If (HPTE) {
CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
If (Lequal(HPAS, 1)) {
HPT0 = CONFIG_HPET_ADDRESS + 0x1000
HPT0 = HPET_BASE_ADDRESS + 0x1000
}
If (Lequal(HPAS, 2)) {
HPT0 = CONFIG_HPET_ADDRESS + 0x2000
HPT0 = HPET_BASE_ADDRESS + 0x2000
}
If (Lequal(HPAS, 3)) {
HPT0 = CONFIG_HPET_ADDRESS + 0x3000
HPT0 = HPET_BASE_ADDRESS + 0x3000
}
}

10
src/southbridge/intel/i82801jx/acpi/lpc.asl
View File

@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hpet.h>
// Intel LPC Bus Device - 0:1f.0
Device (LPCB)
@@ -60,7 +62,7 @@ Device (LPCB)
Name(BUF0, ResourceTemplate()
{
Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
})
Method (_STA, 0) // Device Status
@@ -73,15 +75,15 @@ Device (LPCB)
If (HPTE) {
CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
If (Lequal(HPAS, 1)) {
HPT0 = CONFIG_HPET_ADDRESS + 0x1000
HPT0 = HPET_BASE_ADDRESS + 0x1000
}
If (Lequal(HPAS, 2)) {
HPT0 = CONFIG_HPET_ADDRESS + 0x2000
HPT0 = HPET_BASE_ADDRESS + 0x2000
}
If (Lequal(HPAS, 3)) {
HPT0 = CONFIG_HPET_ADDRESS + 0x3000
HPT0 = HPET_BASE_ADDRESS + 0x3000
}
}

10
src/southbridge/intel/lynxpoint/acpi/lpc.asl
View File

@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hpet.h>
// Intel LPC Bus Device - 0:1f.0
#include <southbridge/intel/lynxpoint/pch.h>
@@ -66,7 +68,7 @@ Device (LPCB)
Name (BUF0, ResourceTemplate ()
{
Memory32Fixed (ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
Memory32Fixed (ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
})
Method (_STA, 0) // Device Status
@@ -79,15 +81,15 @@ Device (LPCB)
If (HPTE) {
CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
If (HPAS == 1) {
HPT0 = CONFIG_HPET_ADDRESS + 0x1000
HPT0 = HPET_BASE_ADDRESS + 0x1000
}
If (HPAS == 2) {
HPT0 = CONFIG_HPET_ADDRESS + 0x2000
HPT0 = HPET_BASE_ADDRESS + 0x2000
}
If (HPAS == 3) {
HPT0 = CONFIG_HPET_ADDRESS + 0x3000
HPT0 = HPET_BASE_ADDRESS + 0x3000
}
}