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nb/intel/nehalem/raminit.c: Remove variable set but not used

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Change-Id: I216d4d00375fcff9e740583b9e17013e0495360c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32944
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS
2019-05-22 20:53:25 +02:00
committed by Patrick Georgi
parent 3c3f836d7e
commit 97642c28f6
1 changed files with 12 additions and 17 deletions
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29
src/northbridge/intel/nehalem/raminit.c
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@@ -3722,11 +3722,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
u16 deven; u16 deven;
int cbmem_wasnot_inited; int cbmem_wasnot_inited;
/* only used for dummy reads */
volatile u8 tmp8;
volatile u16 tmp16;
volatile u32 tmp32;
x2ca8 = MCHBAR8(0x2ca8); x2ca8 = MCHBAR8(0x2ca8);
deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN);
@@ -4040,10 +4035,10 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c); pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e); pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e);
tmp8 = MCHBAR8(0x1150); MCHBAR8(0x1150);
tmp8 = MCHBAR8(0x1151); MCHBAR8(0x1151);
tmp8 = MCHBAR8(0x1022); MCHBAR8(0x1022);
tmp8 = MCHBAR8(0x16d0); MCHBAR8(0x16d0);
MCHBAR32(0x1300) = 0x60606060; MCHBAR32(0x1300) = 0x60606060;
MCHBAR32(0x1304) = 0x60606060; MCHBAR32(0x1304) = 0x60606060;
MCHBAR32(0x1308) = 0x78797a7b; MCHBAR32(0x1308) = 0x78797a7b;
@@ -4231,10 +4226,10 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
} }
MCHBAR32_AND_OR(0x2c80, 0, 0x1053688); // !!!! MCHBAR32_AND_OR(0x2c80, 0, 0x1053688); // !!!!
tmp32 = MCHBAR32(0x1c04); // !!!! MCHBAR32(0x1c04); // !!!!
MCHBAR32(0x1804) = 0x406080; MCHBAR32(0x1804) = 0x406080;
tmp8 = MCHBAR8(0x2ca8); MCHBAR8(0x2ca8);
if (x2ca8 == 0) { if (x2ca8 == 0) {
MCHBAR8_AND(0x2ca8, ~3); MCHBAR8_AND(0x2ca8, ~3);
@@ -4246,9 +4241,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8);
MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!! MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!!
pci_write_config32(PCI_DEV (0xff, 0, 0), 0x60, 0x20220); pci_write_config32(PCI_DEV (0xff, 0, 0), 0x60, 0x20220);
tmp16 = MCHBAR16(0x2c20); // !!!! MCHBAR16(0x2c20); // !!!!
tmp16 = MCHBAR16(0x2c10); // !!!! MCHBAR16(0x2c10); // !!!!
tmp16 = MCHBAR16(0x2c00); // !!!! MCHBAR16(0x2c00); // !!!!
MCHBAR16(0x2c00) = 0x8c0; MCHBAR16(0x2c00) = 0x8c0;
udelay(1000); udelay(1000);
write_1d0(0, 0x33d, 0, 0); write_1d0(0, 0x33d, 0, 0);
@@ -4354,7 +4349,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
MCHBAR32_AND_OR(0x1f4, 0, 0x20000); // !!!! MCHBAR32_AND_OR(0x1f4, 0, 0x20000); // !!!!
MCHBAR32(0x1f0) = 0x1d000200; MCHBAR32(0x1f0) = 0x1d000200;
MCHBAR8_AND_OR(0x1f0, 0, 0x1); // !!!! MCHBAR8_AND_OR(0x1f0, 0, 0x1); // !!!!
tmp8 = MCHBAR8(0x1f0); // !!!! MCHBAR8(0x1f0); // !!!!
program_board_delay(&info); program_board_delay(&info);
@@ -4413,7 +4408,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
info.populated_ranks[channel][0][0] ? 9 : 1); info.populated_ranks[channel][0][0] ? 9 : 1);
rmw_1d0(0x116, 0xe, 1, 4, 1); // = 0x4040432 // !!!! rmw_1d0(0x116, 0xe, 1, 4, 1); // = 0x4040432 // !!!!
tmp32 = MCHBAR32(0x144); // !!!! MCHBAR32(0x144); // !!!!
write_1d0(2, 0xae, 6, 1); write_1d0(2, 0xae, 6, 1);
write_1d0(2, 0x300, 6, 1); write_1d0(2, 0x300, 6, 1);
write_1d0(2, 0x121, 3, 1); write_1d0(2, 0x121, 3, 1);
@@ -4663,7 +4658,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
reg1c = read32p(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK reg1c = read32p(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK
pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
write32p(DEFAULT_EPBAR | 0x01c, reg1c); // OK write32p(DEFAULT_EPBAR | 0x01c, reg1c); // OK
tmp8 = MCHBAR8(0xe08); // = 0x0 MCHBAR8(0xe08); // = 0x0
pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126 pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126
MCHBAR8_OR(0x1210, 2); MCHBAR8_OR(0x1210, 2);
MCHBAR32(0x1200) = 0x8800440; MCHBAR32(0x1200) = 0x8800440;