From 36cc664bc749a650012e41321e9a1cac3abdbd54 Mon Sep 17 00:00:00 2001 From: "Pandya, Varshit B" Date: Mon, 1 Jul 2019 16:27:01 +0530 Subject: [PATCH 001/231] util/cbfstool/ifittool: use strtol function instead of atoi Fix error "Invalid option -A" by adding "A" to options list. Also, atoi does not parse hex string, for instance 0x200 is interpreted as 0, and this causes a failure when updating second FIT table using -j option. Use strtol instead of atoi BUG=none BRANCH=none TEST=Build and boot hatch after enabling dual bootblock feature. Change-Id: Ib227437f88ffcccda1ce2f20a9ab098e5aa091c7 Signed-off-by: Pandya, Varshit B Reviewed-on: https://review.coreboot.org/c/coreboot/+/33937 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi Reviewed-by: Subrata Banik --- util/cbfstool/ifittool.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/cbfstool/ifittool.c b/util/cbfstool/ifittool.c index a83fd96715..3b16c3fcf0 100644 --- a/util/cbfstool/ifittool.c +++ b/util/cbfstool/ifittool.c @@ -28,7 +28,7 @@ /* Global variables */ partitioned_file_t *image_file; -static const char *optstring = "H:j:f:r:d:t:n:s:caDvh?"; +static const char *optstring = "H:j:f:r:d:t:n:s:cAaDvh?"; static struct option long_options[] = { {"file", required_argument, 0, 'f' }, {"region", required_argument, 0, 'r' }, @@ -230,7 +230,7 @@ int main(int argc, char *argv[]) } break; case 'j': - topswap_size = atoi(optarg); + topswap_size = strtol(optarg, NULL, 0); if (!is_valid_topswap(topswap_size)) return 1; break; From 595d926bc23e706acc06e69fa3313bea5d461186 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Thu, 27 Jun 2019 17:33:10 -0600 Subject: [PATCH 002/231] util/ifdtool: Make internal functions static These functions are only used in ifdtool, so they can be made static. Change-Id: Ia48bfecb89a7445dbd0f140acb5ac0592da2ebe7 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33860 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- util/ifdtool/ifdtool.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index a1a327f6ed..83caa693ab 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1067,7 +1067,7 @@ static void unlock_descriptor(const char *filename, char *image, int size) } /* Set the AltMeDisable (or HAP for >= IFD_VERSION_2) */ -void fpsba_set_altmedisable(fpsba_t *fpsba, fmsba_t *fmsba, bool altmedisable) +static void fpsba_set_altmedisable(fpsba_t *fpsba, fmsba_t *fmsba, bool altmedisable) { if (ifd_version >= IFD_VERSION_2) { printf("%sting the HAP bit to %s Intel ME...\n", @@ -1107,7 +1107,7 @@ void fpsba_set_altmedisable(fpsba_t *fpsba, fmsba_t *fmsba, bool altmedisable) } } -void inject_region(const char *filename, char *image, int size, +static void inject_region(const char *filename, char *image, int size, unsigned int region_type, const char *region_fname) { frba_t *frba = find_frba(image, size); @@ -1173,7 +1173,7 @@ void inject_region(const char *filename, char *image, int size, write_image(filename, image, size); } -unsigned int next_pow2(unsigned int x) +static unsigned int next_pow2(unsigned int x) { unsigned int y = 1; if (x == 0) @@ -1200,7 +1200,7 @@ static int regions_collide(const region_t *r1, const region_t *r2) return !(r1->limit < r2->base || r1->base > r2->limit); } -void new_layout(const char *filename, char *image, int size, +static void new_layout(const char *filename, char *image, int size, const char *layout_fname) { FILE *romlayout; From 02b1e20f005007685a71945e86b701bb2e5b79f0 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Thu, 27 Jun 2019 17:34:13 -0600 Subject: [PATCH 003/231] util/ifdtool: Enable -Wmissing-prototypes Change-Id: Idc31144024f785a42cbad78bf2c965d08dcc5178 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33861 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- util/ifdtool/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile index e1188b209c..4cddfc5542 100644 --- a/util/ifdtool/Makefile +++ b/util/ifdtool/Makefile @@ -18,7 +18,7 @@ PROGRAM = ifdtool CC = gcc INSTALL = /usr/bin/env install PREFIX = /usr/local -CFLAGS = -O2 -g -Wall -W -Werror -I../../src/commonlib/include +CFLAGS = -O2 -g -Wall -W -Wmissing-prototypes -Werror -I../../src/commonlib/include LDFLAGS = OBJS = ifdtool.o From 1430b3995f796de0daeaaf95c31dc086f5f2d5ac Mon Sep 17 00:00:00 2001 From: You-Cheng Syu Date: Mon, 1 Jul 2019 16:40:25 +0800 Subject: [PATCH 004/231] util/cbmem: Update banner string regular expression Banner string format has been changed (CB:30935). We should update our regular expression correspondingly. Also add "verstage" into the stage search list since some boards (e.g., Kukui) might start console initialization at verstage. Change-Id: I16eba3ac5e203e80b0bfd42a4294401dbccd4463 Signed-off-by: You-Cheng Syu Reviewed-on: https://review.coreboot.org/c/coreboot/+/33779 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Paul Menzel --- util/cbmem/cbmem.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 52fdc9b81f..9d2a64349c 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -797,9 +797,11 @@ static void dump_console(int one_boot_only) a banner, store the last match for that stage in cursor and stop. */ cursor = 0; if (one_boot_only) { -#define BANNER_REGEX(stage) "\n\ncoreboot-[^\n]* " stage " starting\\.\\.\\.\n" +#define BANNER_REGEX(stage) \ + "\n\ncoreboot-[^\n]* " stage " starting.*\\.\\.\\.\n" #define OVERFLOW_REGEX(stage) "\n\\*\\*\\* Pre-CBMEM " stage " console overflow" const char *regex[] = { BANNER_REGEX("bootblock"), + BANNER_REGEX("verstage"), OVERFLOW_REGEX("romstage"), BANNER_REGEX("romstage"), OVERFLOW_REGEX("ramstage"), From 24e52659a3ab5a4bd4954696700666174bb016a9 Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Tue, 11 Jun 2019 11:17:57 -0700 Subject: [PATCH 005/231] QC common: fix compiler complaint, missing Change-Id: I5b5b7bc61dd82fb1b866857d60926b057fae3715 Signed-off-by: T Michael Turney Reviewed-on: https://review.coreboot.org/c/coreboot/+/33445 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/soc/qualcomm/common/qclib.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index 25512a938f..ac80a76c82 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include From c796a8f238f70a09828d5c40c23c05650803cb3c Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 1 Jul 2019 10:21:11 +0530 Subject: [PATCH 006/231] soc/intel/icelake: Disable HDA based on devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I28c2beca4bc26ddb896e68886571ebdc82276b48 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/33933 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Paul Menzel --- src/soc/intel/icelake/romstage/fsp_params.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 3c49feeccc..fa6f9392a4 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -25,7 +25,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_icelake_config *config) { unsigned int i; - const struct device *dev = pcidev_on_root(0, 0); + const struct device *dev; uint32_t mask = 0; /* Set IGD stolen size to 60MB. */ @@ -36,7 +36,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->RMT; m_cfg->SkipMbpHob = 1; + /* If Audio Codec is enabled, enable FSP UPD */ + dev = pcidev_on_root(0x1f, 3); if (!dev) m_cfg->PchHdaEnable = 0; else From c1b7e8a60be9853b5b00fc70615cea2fa8bfafc5 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 21 Feb 2019 10:27:04 +0100 Subject: [PATCH 007/231] cpu/x86/pae/pgtbl: Add memset with PAE To clear all DRAM on x86_32, add a new method that uses PAE to access more than 32bit of address space. Add Documentation as well. Required for clearing all system memory as part of security API. Tested on wedge100s: Takes less than 2 seconds to clear 8GiB of DRAM. Tested on P8H61M-Pro: Takes less than 1 second to clear 4GiB of DRAM. Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/31549 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- Documentation/arch/x86/index.md | 2 + Documentation/arch/x86/pae.md | 15 +++ Documentation/security/memory_clearing.md | 4 + src/cpu/x86/pae/pgtbl.c | 127 ++++++++++++++++++++++ src/include/cpu/x86/pae.h | 25 +++++ 5 files changed, 173 insertions(+) create mode 100644 Documentation/arch/x86/pae.md diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 3ecb9803a4..73c982385a 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -2,6 +2,8 @@ This section contains documentation about coreboot on x86 architecture. +* [x86 PAE support](pae.md) + ## State of x86_64 support At the moment there's no single board that supports x86_64 or to be exact `ARCH_RAMSTAGE_X86_64` and `ARCH_ROMSTAGE_X86_64`. diff --git a/Documentation/arch/x86/pae.md b/Documentation/arch/x86/pae.md new file mode 100644 index 0000000000..54cd82f2e4 --- /dev/null +++ b/Documentation/arch/x86/pae.md @@ -0,0 +1,15 @@ +# x86_32 PAE documentation + +Due to missing x86_64 support it's required to use PAE enabled x86_32 code. +The corresponding functions can be found in ``src/cpu/x86/pae/``. + +## Memory clearing helper functions + +To clear all DRAM on request of the +[Security API](../../security/memory_clearing.md), a helper function can be used +called `memset_pae`. +The function has additional requirements in contrast to `memset`, and has more +overhead as it uses virtual memory to access memory above 4GiB. +Memory is cleared in 2MiB chunks, which might take a while. + +Make sure to enable caches through MTRRs, otherwise `memset_pae` will be slow! diff --git a/Documentation/security/memory_clearing.md b/Documentation/security/memory_clearing.md index 3d985925d9..e5c19256b9 100644 --- a/Documentation/security/memory_clearing.md +++ b/Documentation/security/memory_clearing.md @@ -42,3 +42,7 @@ Without MTRRs (and caches enabled) clearing memory takes multiple seconds. As some platforms place code and stack in DRAM (FSP1.0), the regions can be skipped. + +## Architecture specific implementations + +* [x86 PAE](../arch/x86/pae.md) diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 9c921342f1..f54a1c35db 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2005 Yinghai Lu + * Copyright (C) 2019 9elements Agency GmbH + * Copyright (C) 2019 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +24,7 @@ #include #include #include +#include #define PDPTE_PRES (1ULL << 0) #define PDPTE_ADDR_MASK (~((1ULL << 12) - 1)) @@ -59,9 +62,20 @@ #define PTE_IDX_SHIFT 12 #define PTE_IDX_MASK 0x1ff +#define OVERLAP(a, b, s, e) ((b) > (s) && (a) < (e)) + static const size_t s2MiB = 2 * MiB; static const size_t s4KiB = 4 * KiB; +struct pde { + uint32_t addr_lo; + uint32_t addr_hi; +} __packed; +struct pg_table { + struct pde pd[2048]; + struct pde pdp[512]; +} __packed; + void paging_enable_pae_cr3(uintptr_t cr3) { /* Load the page table address */ @@ -101,6 +115,119 @@ void paging_disable_pae(void) write_cr4(cr4); } +/* + * Use PAE to map a page and then memset it with the pattern specified. + * In order to use PAE pagetables for virtual addressing are set up and reloaded + * on a 2MiB boundary. After the function is done, virtual addressing mode is + * disabled again. The PAT are set to all cachable, but MTRRs still apply. + * + * Requires a scratch memory for pagetables and a virtual address for + * non identity mapped memory. + * + * The scratch memory area containing pagetables must not overlap with the + * memory range to be cleared. + * The scratch memory area containing pagetables must not overlap with the + * virtual address for non identity mapped memory. + * + * @param vmem_addr Where the virtual non identity mapped page resides, must + * be 2 aligned MiB and at least 2 MiB in size. + * Content at physical address is preserved. + * @param pgtbl Where pagetables reside, must be 4 KiB aligned and 20 KiB in + * size. + * Must not overlap memory range pointed to by dest. + * Must not overlap memory range pointed to by vmem_addr. + * Content at physical address isn't preserved. + * @param length The length of the memory segment to memset + * @param dest Physical memory address to memset + * @param pat The pattern to write to the pyhsical memory + * @return 0 on success, 1 on error + */ +int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl, + void *vmem_addr) +{ + struct pg_table *pgtbl_buf = (struct pg_table *)pgtbl; + ssize_t offset; + + printk(BIOS_DEBUG, "%s: Using virtual address %p as scratchpad\n", + __func__, vmem_addr); + printk(BIOS_DEBUG, "%s: Using address %p for page tables\n", + __func__, pgtbl_buf); + + /* Cover some basic error conditions */ + if (!IS_ALIGNED((uintptr_t)pgtbl_buf, s4KiB) || + !IS_ALIGNED((uintptr_t)vmem_addr, s2MiB)) { + printk(BIOS_ERR, "%s: Invalid alignment\n", __func__); + return 1; + } + const uintptr_t pgtbl_s = (uintptr_t)pgtbl_buf; + const uintptr_t pgtbl_e = pgtbl_s + sizeof(struct pg_table); + + if (OVERLAP(dest, dest + length, pgtbl_s, pgtbl_e)) { + printk(BIOS_ERR, "%s: destination overlaps page tables\n", + __func__); + return 1; + } + + if (OVERLAP((uintptr_t)vmem_addr, (uintptr_t)vmem_addr + s2MiB, + pgtbl_s, pgtbl_e)) { + printk(BIOS_ERR, "%s: vmem address overlaps page tables\n", + __func__); + return 1; + } + + paging_disable_pae(); + + struct pde *pd = pgtbl_buf->pd, *pdp = pgtbl_buf->pdp; + /* Point the page directory pointers at the page directories. */ + memset(pgtbl_buf->pdp, 0, sizeof(pgtbl_buf->pdp)); + + pdp[0].addr_lo = ((uintptr_t)&pd[512*0]) | PDPTE_PRES; + pdp[1].addr_lo = ((uintptr_t)&pd[512*1]) | PDPTE_PRES; + pdp[2].addr_lo = ((uintptr_t)&pd[512*2]) | PDPTE_PRES; + pdp[3].addr_lo = ((uintptr_t)&pd[512*3]) | PDPTE_PRES; + + offset = dest - ALIGN_DOWN(dest, s2MiB); + dest = ALIGN_DOWN(dest, s2MiB); + + /* Identity map the whole 32-bit address space */ + for (size_t i = 0; i < 2048; i++) { + pd[i].addr_lo = (i << PDE_IDX_SHIFT) | PDE_PS | PDE_PRES | PDE_RW; + pd[i].addr_hi = 0; + } + + /* Get pointer to PD that's not identity mapped */ + pd = &pgtbl_buf->pd[((uintptr_t)vmem_addr) >> PDE_IDX_SHIFT]; + + paging_enable_pae_cr3((uintptr_t)pdp); + + do { + const size_t len = MIN(length, s2MiB - offset); + + /* + * Map a page using PAE at virtual address vmem_addr. + * dest is already 2 MiB aligned. + */ + pd->addr_lo = dest | PDE_PS | PDE_PRES | PDE_RW; + pd->addr_hi = dest >> 32; + + /* Update page tables */ + asm volatile ("invlpg (%0)" :: "b"(vmem_addr) : "memory"); + + printk(BIOS_SPEW, "%s: Clearing %llx[%lx] - %zx\n", __func__, + dest + offset, (uintptr_t)vmem_addr + offset, len); + + memset(vmem_addr + offset, pat, len); + + dest += s2MiB; + length -= len; + offset = 0; + } while (length > 0); + + paging_disable_pae(); + + return 0; +} + #if ENV_RAMSTAGE void *map_2M_page(unsigned long page) { diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h index 7627187a52..72bae53d68 100644 --- a/src/include/cpu/x86/pae.h +++ b/src/include/cpu/x86/pae.h @@ -1,3 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH + * Copyright (C) 2019 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #ifndef CPU_X86_PAE_H #define CPU_X86_PAE_H @@ -41,4 +57,13 @@ int paging_identity_map_addr(uintptr_t base, size_t size, int pat); #define MAPPING_ERROR ((void *)0xffffffffUL) void *map_2M_page(unsigned long page); +/* To be used with memset_pae */ +#define MEMSET_PAE_VMEM_ALIGN (2 * MiB) +#define MEMSET_PAE_VMEM_SIZE (2 * MiB) +#define MEMSET_PAE_PGTL_ALIGN (4 * KiB) +#define MEMSET_PAE_PGTL_SIZE (20 * KiB) + +int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl, + void *vmem_addr); + #endif /* CPU_X86_PAE_H */ From a19b07fec13e713004e722f439e1ed7bc2e6ebd0 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 21 Feb 2019 12:11:14 +0100 Subject: [PATCH 008/231] security/memory: Clear memory in ramstage * Add architecture independend way of clearing all DRAM * Implemented in ramstage as MTRRs need to be set to speed up clearing. Takes up to 15 seconds per GiB otherwise. * Use memset_pae on x86 * Add quirks for FSP1.0 Tested on P8H61M-Pro: * Clears 4GiB in less than 1 second Tested on wedge100s: * Clears 8GiB in 2 seconds Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/31550 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/arch/x86/include/arch/memory_clear.h | 24 ++++ src/security/memory/Kconfig | 2 + src/security/memory/Makefile.inc | 2 + src/security/memory/memory_clear.c | 160 +++++++++++++++++++++++ 4 files changed, 188 insertions(+) create mode 100644 src/arch/x86/include/arch/memory_clear.h create mode 100644 src/security/memory/memory_clear.c diff --git a/src/arch/x86/include/arch/memory_clear.h b/src/arch/x86/include/arch/memory_clear.h new file mode 100644 index 0000000000..87ad7ada85 --- /dev/null +++ b/src/arch/x86/include/arch/memory_clear.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH + * Copyright (C) 2019 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MEMORY_CLEAR_H +#define MEMORY_CLEAR_H + +#include + +int arch_clear_memranges(const struct memranges *mem_reserved); + +#endif /* MEMORY_CLEAR_H */ diff --git a/src/security/memory/Kconfig b/src/security/memory/Kconfig index 5436119ba5..d84b80d382 100644 --- a/src/security/memory/Kconfig +++ b/src/security/memory/Kconfig @@ -17,7 +17,9 @@ menu "Memory initialization" config PLATFORM_HAS_DRAM_CLEAR bool + default y if ARCH_X86 default n + depends on RELOCATABLE_RAMSTAGE help Selected by platforms that support clearing all DRAM after DRAM initialization. diff --git a/src/security/memory/Makefile.inc b/src/security/memory/Makefile.inc index 525c4dbb4d..0882ca3660 100644 --- a/src/security/memory/Makefile.inc +++ b/src/security/memory/Makefile.inc @@ -1,3 +1,5 @@ romstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c postcar-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c ramstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c + +ramstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory_clear.c diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c new file mode 100644 index 0000000000..638c41a929 --- /dev/null +++ b/src/security/memory/memory_clear.c @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH + * Copyright (C) 2019 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if CONFIG(ARCH_X86) +#include +#else +#define memset_pae(a, b, c, d, e) 0 +#define MEMSET_PAE_PGTL_ALIGN 0 +#define MEMSET_PAE_PGTL_SIZE 0 +#define MEMSET_PAE_PGTL_SIZE 0 +#define MEMSET_PAE_VMEM_ALIGN 0 +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Helper to find free space for memset_pae. */ +static uintptr_t get_free_memory_range(struct memranges *mem, + const resource_t align, + const resource_t size) +{ + const struct range_entry *r; + + /* Find a spot for virtual memory address */ + memranges_each_entry(r, mem) { + if (range_entry_tag(r) != BM_MEM_RAM) + continue; + + if (ALIGN_UP(range_entry_base(r) + size, align) + size > + range_entry_end(r)) + continue; + + return ALIGN_UP(range_entry_base(r) + size, align); + } + printk(BIOS_ERR, "%s: Couldn't find free memory range\n", __func__); + + return 0; +} + +/* + * Clears all memory regions marked as BM_MEM_RAM. + * Uses memset_pae if the memory region can't be accessed by memset and + * architecture is x86. + * + * @return 0 on success, 1 on error + */ +static void clear_memory(void *unused) +{ + const struct range_entry *r; + struct memranges mem; + uintptr_t pgtbl, vmem_addr; + + if (acpi_is_wakeup_s3()) + return; + + if (!security_clear_dram_request()) + return; + + /* FSP1.0 is marked as MMIO and won't appear here */ + + memranges_init(&mem, IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED | + IORESOURCE_CACHEABLE, + IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED | + IORESOURCE_CACHEABLE, + BM_MEM_RAM); + + /* Add reserved entries */ + void *baseptr = NULL; + size_t size = 0; + + /* Only skip CBMEM, as RELOCATABLE_RAMSTAGE is a requirement, no need + * to separately protect stack or heap */ + + cbmem_get_region(&baseptr, &size); + memranges_insert(&mem, (uintptr_t)baseptr, size, BM_MEM_TABLE); + + if (CONFIG(PLATFORM_USES_FSP1_0)) { + /* Protect CBMEM pointer */ + memranges_insert(&mem, CBMEM_FSP_HOB_PTR, sizeof(void *), + BM_MEM_TABLE); + } + + if (CONFIG(ARCH_X86)) { + /* Find space for PAE enabled memset */ + pgtbl = get_free_memory_range(&mem, MEMSET_PAE_PGTL_ALIGN, + MEMSET_PAE_PGTL_SIZE); + + /* Don't touch page tables while clearing */ + memranges_insert(&mem, pgtbl, MEMSET_PAE_PGTL_SIZE, + BM_MEM_TABLE); + + vmem_addr = get_free_memory_range(&mem, MEMSET_PAE_VMEM_ALIGN, + MEMSET_PAE_PGTL_SIZE); + + printk(BIOS_SPEW, "%s: pgtbl at %p, virt memory at %p\n", + __func__, (void *)pgtbl, (void *)vmem_addr); + } + + /* Now clear all useable DRAM */ + memranges_each_entry(r, &mem) { + if (range_entry_tag(r) != BM_MEM_RAM) + continue; + printk(BIOS_DEBUG, "%s: Clearing DRAM %016llx-%016llx\n", + __func__, range_entry_base(r), range_entry_end(r)); + + /* Does regular memset work? */ + if (!(range_entry_end(r) >> sizeof(void *) * 8)) { + /* fastpath */ + memset((void *)(uintptr_t)range_entry_base(r), 0, + range_entry_size(r)); + } + /* Use PAE if available */ + else if (CONFIG(ARCH_X86)) { + if (memset_pae(range_entry_base(r), 0, + range_entry_size(r), (void *)pgtbl, + (void *)vmem_addr)) + printk(BIOS_ERR, "%s: Failed to memset " + "memory\n", __func__); + } else { + printk(BIOS_ERR, "%s: Failed to memset memory\n", + __func__); + } + } + + if (CONFIG(ARCH_X86)) { + /* Clear previously skipped memory reserved for pagetables */ + printk(BIOS_DEBUG, "%s: Clearing DRAM %016lx-%016lx\n", + __func__, pgtbl, pgtbl + MEMSET_PAE_PGTL_SIZE); + + memset((void *)pgtbl, 0, MEMSET_PAE_PGTL_SIZE); + } + + memranges_teardown(&mem); +} + +/* After DEV_INIT as MTRRs needs to be configured on x86 */ +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, clear_memory, NULL); From 8c9be4327154ef46ffc96da13f816ffddb77253d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 29 Jun 2019 22:34:07 +0300 Subject: [PATCH 009/231] device/pci_rom: Fix on-board optionrom address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The function pci_rom_probe() may be called multiple times for a device. For cases where CBFS does not contain optionrom file, only the first time probing for the on-board ROM chip worked. PCI_ROM_ADDRESS_ENABLE is set on the first run. Mask out all the reserved bits of PCI_ROM_ADDRESS register to get correct physical address for rom_header. Change-Id: I14374954af09201494bf2f13e5a6e4dc640c05ee Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/33908 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Mike Banon --- src/device/pci_rom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 3160c2041b..7322e57f45 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -77,6 +77,8 @@ struct rom_header *pci_rom_probe(struct device *dev) rom_address|PCI_ROM_ADDRESS_ENABLE); } + rom_address &= PCI_ROM_ADDRESS_MASK; + printk(BIOS_DEBUG, "Option ROM address for %s = %lx\n", dev_path(dev), (unsigned long)rom_address); rom_header = (struct rom_header *)rom_address; From fb49379ed22341d5e5e859af6823e9361db021f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 30 Jun 2019 06:29:52 +0300 Subject: [PATCH 010/231] device/pci_rom: Fix redundant pci_rom_probe() calls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For the PCI_VENDOR_ID_ATI case, we can rely on pci_rom_acpi_fill_vfct() to make the call if necessary. For hardware other than ATI, pci_rom_probe() was already called from pci_rom_ssdt() and pci_dev_init(), so PCI_ROM_ADDRESS BAR is already enabled, if requested so. Change-Id: I0ea893a9ac7ba480840ebf5570d8fe0d9e20938f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/33909 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Mike Banon --- src/arch/x86/acpi.c | 5 ++++- src/device/pci_rom.c | 22 +++++++++------------- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 80923e3edd..8ab993ec48 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -763,11 +763,14 @@ void acpi_create_vfct(struct device *device, memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = asl_revision; - header->length = sizeof(struct acpi_vfct); header->revision = get_acpi_table_revision(VFCT); current = acpi_fill_vfct(device, vfct, current); + /* If no BIOS image, return with header->length == 0. */ + if (!vfct->VBIOSImageOffset) + return; + /* (Re)calculate length and checksum. */ header->length = current - (unsigned long)vfct; header->checksum = acpi_checksum((void *)vfct, header->length); diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 7322e57f45..31fe115c89 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -209,8 +209,6 @@ pci_rom_acpi_fill_vfct(struct device *device, struct acpi_vfct *vfct_struct, struct acpi_vfct_image_hdr *header = &vfct_struct->image_hdr; struct rom_header *rom; - vfct_struct->VBIOSImageOffset = (size_t)header - (size_t)vfct_struct; - rom = check_initialized(device); if (!rom) rom = pci_rom_probe(device); @@ -233,6 +231,8 @@ pci_rom_acpi_fill_vfct(struct device *device, struct acpi_vfct *vfct_struct, header->ImageLength = rom->size * 512; memcpy((void *)&header->VbiosContent, rom, header->ImageLength); + vfct_struct->VBIOSImageOffset = (size_t)header - (size_t)vfct_struct; + current += header->ImageLength; return current; } @@ -241,9 +241,6 @@ unsigned long pci_rom_write_acpi_tables(struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { - struct acpi_vfct *vfct; - struct rom_header *rom; - /* Only handle VGA devices */ if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) return current; @@ -252,19 +249,18 @@ pci_rom_write_acpi_tables(struct device *device, unsigned long current, if (!device->enabled) return current; - /* Probe for option rom */ - rom = pci_rom_probe(device); - if (!rom) - return current; - /* AMD/ATI uses VFCT */ if (device->vendor == PCI_VENDOR_ID_ATI) { + struct acpi_vfct *vfct; + current = ALIGN_UP(current, 8); - printk(BIOS_DEBUG, "ACPI: * VFCT at %lx\n", current); vfct = (struct acpi_vfct *)current; acpi_create_vfct(device, vfct, pci_rom_acpi_fill_vfct); - current += vfct->header.length; - acpi_add_table(rsdp, vfct); + if (vfct->header.length) { + printk(BIOS_DEBUG, "ACPI: * VFCT at %lx\n", current); + current += vfct->header.length; + acpi_add_table(rsdp, vfct); + } } return current; From 76378b3c01b52f4d4184284d3d07bf63fef2ca17 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Wed, 26 Jun 2019 13:56:28 +0800 Subject: [PATCH 011/231] mb/google/reef/variants/: fix Samsung K4F6E3S4HM-MGCJ density Samsung K4F6E3S4HM-MGCJ density is 16Gb BUG=b:121228792 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage MemTotal: 8041964kB in /proc/meminfo Change-Id: Ie8ecd82b92d4e82d3955cf773febca30f6280a5e Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/33795 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/mainboard/google/reef/variants/baseboard/memory.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c index f298cae95e..76731070db 100644 --- a/src/mainboard/google/reef/variants/baseboard/memory.c +++ b/src/mainboard/google/reef/variants/baseboard/memory.c @@ -140,8 +140,8 @@ static const struct lpddr4_sku skus[] = { /* K4F6E3S4HM-MGCJ - both logical channels */ [7] = { .speed = LP4_SPEED_2400, - .ch0_rank_density = LP4_8Gb_DENSITY, - .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_rank_density = LP4_16Gb_DENSITY, + .ch1_rank_density = LP4_16Gb_DENSITY, .part_num = "K4F6E3S4HM-MGCJ", }, }; From 5c354b9979c7e7ad9af668bad0e1b6a5c3003d26 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 22 Apr 2019 14:55:16 -0600 Subject: [PATCH 012/231] soc/amd/picasso: Create picasso as a copy of stoneyridge So that everyone can see what's being updated from stoney, we're starting with a direct copy of the stoney directory. There are arguments both for and against doing it this way, but I believe This the most transparent way. We've moved much of the duplicated stoney code into the soc/amd/common directory and will continue that work as it becomes obvious that we have unchanged code between the SOCs. Makefile.inc has been renamed as makefile.inc so that it won't build in jenkins until the directory is updated. Other than that change, this is an exact copy of the stoneyridge SOC directory which will be updated in the follow-on commits in the patch train. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407 Reviewed-by: Richard Spiegel Reviewed-by: Angel Pons Reviewed-by: Edward O'Callaghan Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/BiosCallOuts.c | 166 +++++ src/soc/amd/picasso/Kconfig | 389 ++++++++++ src/soc/amd/picasso/acpi.c | 406 +++++++++++ src/soc/amd/picasso/acpi/acpi_wake_source.asl | 32 + src/soc/amd/picasso/acpi/cpu.asl | 49 ++ src/soc/amd/picasso/acpi/globalnvs.asl | 77 ++ src/soc/amd/picasso/acpi/northbridge.asl | 134 ++++ src/soc/amd/picasso/acpi/pci_int.asl | 469 ++++++++++++ src/soc/amd/picasso/acpi/pcie.asl | 99 +++ src/soc/amd/picasso/acpi/sb_fch.asl | 153 ++++ src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 619 ++++++++++++++++ src/soc/amd/picasso/acpi/sleepstates.asl | 39 + src/soc/amd/picasso/acpi/soc.asl | 31 + src/soc/amd/picasso/acpi/usb.asl | 392 ++++++++++ src/soc/amd/picasso/bootblock/bootblock.c | 122 ++++ src/soc/amd/picasso/chip.c | 175 +++++ src/soc/amd/picasso/chip.h | 81 +++ src/soc/amd/picasso/cpu.c | 155 ++++ src/soc/amd/picasso/enable_usbdebug.c | 42 ++ src/soc/amd/picasso/finalize.c | 60 ++ src/soc/amd/picasso/gpio.c | 67 ++ src/soc/amd/picasso/i2c.c | 241 +++++++ src/soc/amd/picasso/include/soc/acpi.h | 40 ++ .../picasso/include/soc/amd_pci_int_defs.h | 61 ++ src/soc/amd/picasso/include/soc/cpu.h | 35 + src/soc/amd/picasso/include/soc/gpio.h | 308 ++++++++ src/soc/amd/picasso/include/soc/i2c.h | 49 ++ src/soc/amd/picasso/include/soc/iomap.h | 88 +++ src/soc/amd/picasso/include/soc/northbridge.h | 133 ++++ src/soc/amd/picasso/include/soc/nvs.h | 67 ++ src/soc/amd/picasso/include/soc/pci_devs.h | 198 +++++ src/soc/amd/picasso/include/soc/romstage.h | 21 + src/soc/amd/picasso/include/soc/smbus.h | 35 + src/soc/amd/picasso/include/soc/smi.h | 242 +++++++ src/soc/amd/picasso/include/soc/southbridge.h | 415 +++++++++++ src/soc/amd/picasso/makefile.inc | 316 ++++++++ src/soc/amd/picasso/mca.c | 214 ++++++ src/soc/amd/picasso/monotonic_timer.c | 38 + src/soc/amd/picasso/nb_util.c | 40 ++ src/soc/amd/picasso/northbridge.c | 492 +++++++++++++ src/soc/amd/picasso/pmutil.c | 27 + src/soc/amd/picasso/ramtop.c | 151 ++++ src/soc/amd/picasso/reset.c | 73 ++ src/soc/amd/picasso/romstage.c | 247 +++++++ src/soc/amd/picasso/sata.c | 48 ++ src/soc/amd/picasso/sm.c | 104 +++ src/soc/amd/picasso/smbus.c | 191 +++++ src/soc/amd/picasso/smbus_spd.c | 76 ++ src/soc/amd/picasso/smi.c | 38 + src/soc/amd/picasso/smi_util.c | 138 ++++ src/soc/amd/picasso/smihandler.c | 287 ++++++++ src/soc/amd/picasso/southbridge.c | 675 ++++++++++++++++++ src/soc/amd/picasso/spi.c | 189 +++++ src/soc/amd/picasso/tsc_freq.c | 49 ++ src/soc/amd/picasso/uart.c | 30 + src/soc/amd/picasso/usb.c | 85 +++ 56 files changed, 9198 insertions(+) create mode 100644 src/soc/amd/picasso/BiosCallOuts.c create mode 100644 src/soc/amd/picasso/Kconfig create mode 100644 src/soc/amd/picasso/acpi.c create mode 100644 src/soc/amd/picasso/acpi/acpi_wake_source.asl create mode 100644 src/soc/amd/picasso/acpi/cpu.asl create mode 100644 src/soc/amd/picasso/acpi/globalnvs.asl create mode 100644 src/soc/amd/picasso/acpi/northbridge.asl create mode 100644 src/soc/amd/picasso/acpi/pci_int.asl create mode 100644 src/soc/amd/picasso/acpi/pcie.asl create mode 100644 src/soc/amd/picasso/acpi/sb_fch.asl create mode 100644 src/soc/amd/picasso/acpi/sb_pci0_fch.asl create mode 100644 src/soc/amd/picasso/acpi/sleepstates.asl create mode 100644 src/soc/amd/picasso/acpi/soc.asl create mode 100644 src/soc/amd/picasso/acpi/usb.asl create mode 100644 src/soc/amd/picasso/bootblock/bootblock.c create mode 100644 src/soc/amd/picasso/chip.c create mode 100644 src/soc/amd/picasso/chip.h create mode 100644 src/soc/amd/picasso/cpu.c create mode 100644 src/soc/amd/picasso/enable_usbdebug.c create mode 100644 src/soc/amd/picasso/finalize.c create mode 100644 src/soc/amd/picasso/gpio.c create mode 100644 src/soc/amd/picasso/i2c.c create mode 100644 src/soc/amd/picasso/include/soc/acpi.h create mode 100644 src/soc/amd/picasso/include/soc/amd_pci_int_defs.h create mode 100644 src/soc/amd/picasso/include/soc/cpu.h create mode 100644 src/soc/amd/picasso/include/soc/gpio.h create mode 100644 src/soc/amd/picasso/include/soc/i2c.h create mode 100644 src/soc/amd/picasso/include/soc/iomap.h create mode 100644 src/soc/amd/picasso/include/soc/northbridge.h create mode 100644 src/soc/amd/picasso/include/soc/nvs.h create mode 100644 src/soc/amd/picasso/include/soc/pci_devs.h create mode 100644 src/soc/amd/picasso/include/soc/romstage.h create mode 100644 src/soc/amd/picasso/include/soc/smbus.h create mode 100644 src/soc/amd/picasso/include/soc/smi.h create mode 100644 src/soc/amd/picasso/include/soc/southbridge.h create mode 100644 src/soc/amd/picasso/makefile.inc create mode 100644 src/soc/amd/picasso/mca.c create mode 100644 src/soc/amd/picasso/monotonic_timer.c create mode 100644 src/soc/amd/picasso/nb_util.c create mode 100644 src/soc/amd/picasso/northbridge.c create mode 100644 src/soc/amd/picasso/pmutil.c create mode 100644 src/soc/amd/picasso/ramtop.c create mode 100644 src/soc/amd/picasso/reset.c create mode 100644 src/soc/amd/picasso/romstage.c create mode 100644 src/soc/amd/picasso/sata.c create mode 100644 src/soc/amd/picasso/sm.c create mode 100644 src/soc/amd/picasso/smbus.c create mode 100644 src/soc/amd/picasso/smbus_spd.c create mode 100644 src/soc/amd/picasso/smi.c create mode 100644 src/soc/amd/picasso/smi_util.c create mode 100644 src/soc/amd/picasso/smihandler.c create mode 100644 src/soc/amd/picasso/southbridge.c create mode 100644 src/soc/amd/picasso/spi.c create mode 100644 src/soc/amd/picasso/tsc_freq.c create mode 100644 src/soc/amd/picasso/uart.c create mode 100644 src/soc/amd/picasso/usb.c diff --git a/src/soc/amd/picasso/BiosCallOuts.c b/src/soc/amd/picasso/BiosCallOuts.c new file mode 100644 index 0000000000..c55e73499a --- /dev/null +++ b/src/soc/amd/picasso/BiosCallOuts.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011, 2017 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +void __weak platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset) {} + +AGESA_STATUS agesa_fch_initreset(uint32_t Func, uintptr_t FchData, + void *ConfigPtr) +{ + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; + + if (StdHeader->Func == AMD_INIT_RESET) { + FCH_RESET_DATA_BLOCK *FchParams_reset; + FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + + /* Get platform specific configuration changes */ + platform_FchParams_reset(FchParams_reset); + + printk(BIOS_DEBUG, "Done\n"); + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesa_fch_initenv(uint32_t Func, uintptr_t FchData, + void *ConfigPtr) +{ + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; + const struct device *dev = pcidev_path_on_root(SATA_DEVFN); + + if (StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + + /* XHCI configuration */ + if (CONFIG(STONEYRIDGE_XHCI_ENABLE)) + FchParams_env->Usb.Xhci0Enable = TRUE; + else + FchParams_env->Usb.Xhci0Enable = FALSE; + FchParams_env->Usb.Xhci1Enable = FALSE; + + /* SATA configuration */ + FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE; + if (dev && dev->enabled) { + switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { + case SataRaid: + case SataAhci: + case SataAhci7804: + case SataLegacyIde: + FchParams_env->Sata.SataIdeMode = FALSE; + break; + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams_env->Sata.SataIdeMode = TRUE; + break; + } + } else + FchParams_env->Sata.SataIdeMode = FALSE; + + /* Platform updates */ + platform_FchParams_env(FchParams_env); + + printk(BIOS_DEBUG, "Done\n"); + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesa_ReadSpd(uint32_t Func, uintptr_t Data, void *ConfigPtr) +{ + uint8_t spd_address; + int err; + DEVTREE_CONST struct device *dev; + DEVTREE_CONST struct soc_amd_stoneyridge_config *conf; + AGESA_READ_SPD_PARAMS *info = ConfigPtr; + + if (!ENV_ROMSTAGE) + return AGESA_UNSUPPORTED; + + dev = pcidev_path_on_root(DCT_DEVFN); + if (dev == NULL) + return AGESA_ERROR; + + conf = dev->chip_info; + if (conf == NULL) + return AGESA_ERROR; + + if (info->SocketId >= ARRAY_SIZE(conf->spd_addr_lookup)) + return AGESA_ERROR; + if (info->MemChannelId >= ARRAY_SIZE(conf->spd_addr_lookup[0])) + return AGESA_ERROR; + if (info->DimmId >= ARRAY_SIZE(conf->spd_addr_lookup[0][0])) + return AGESA_ERROR; + + spd_address = conf->spd_addr_lookup + [info->SocketId][info->MemChannelId][info->DimmId]; + if (spd_address == 0) + return AGESA_ERROR; + + err = mainboard_read_spd(spd_address, (void *)info->Buffer, + CONFIG_DIMM_SPD_SIZE); + + /* Read the SPD if the mainboard didn't fill the buffer */ + if (err || (*info->Buffer == 0)) + err = sb_read_spd(spd_address, (void *)info->Buffer, + CONFIG_DIMM_SPD_SIZE); + + if (err) + return AGESA_ERROR; + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesa_HaltThisAp(uint32_t Func, uintptr_t Data, void *ConfigPtr) +{ + AGESA_HALT_THIS_AP_PARAMS *info = ConfigPtr; + uint32_t flags = 0; + + if (info->PrimaryCore == TRUE) + return AGESA_UNSUPPORTED; /* force normal path */ + if (info->ExecWbinvd == TRUE) + flags |= 1; + if (info->CacheEn == TRUE) + flags |= 2; + + ap_teardown_car(flags); /* does not return */ + + /* Should never reach here */ + return AGESA_UNSUPPORTED; +} + +/* Allow mainboards to fill the SPD buffer */ +__weak int mainboard_read_spd(uint8_t spdAddress, char *buf, + size_t len) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return -1; /* SPD not read */ +} diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig new file mode 100644 index 0000000000..ba82565bf4 --- /dev/null +++ b/src/soc/amd/picasso/Kconfig @@ -0,0 +1,389 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SOC_AMD_STONEYRIDGE_FP4 + bool + help + AMD Stoney Ridge FP4 support + +config SOC_AMD_STONEYRIDGE_FT4 + bool + help + AMD Stoney Ridge FT4 support + +if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select X86_AMD_FIXED_MTRRS + select ACPI_AMD_HARDWARE_SLEEP_VALUES + select COLLECT_TIMESTAMPS_NO_TSC + select DRIVERS_I2C_DESIGNWARE + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select IOAPIC + select HAVE_USBDEBUG_OPTIONS + select HAVE_MONOTONIC_TIMER + select SPI_FLASH if HAVE_ACPI_RESUME + select TSC_SYNC_LFENCE + select COLLECT_TIMESTAMPS + select SOC_AMD_PI + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_IOMMU + select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + select SOC_AMD_COMMON_BLOCK_ACPI + select SOC_AMD_COMMON_BLOCK_LPC + select SOC_AMD_COMMON_BLOCK_PCI + select SOC_AMD_COMMON_BLOCK_HDA + select SOC_AMD_COMMON_BLOCK_SATA + select SOC_AMD_COMMON_BLOCK_PI + select SOC_AMD_COMMON_BLOCK_PSP + select SOC_AMD_COMMON_BLOCK_CAR + select SOC_AMD_COMMON_BLOCK_S3 + select C_ENVIRONMENT_BOOTBLOCK + select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select PARALLEL_MP + select PARALLEL_MP_AP_WORK + select HAVE_SMI_HANDLER + select SMM_TSEG + select POSTCAR_STAGE + select POSTCAR_CONSOLE + select SSE2 + select RTC + select SOC_AMD_PSP_SELECTABLE_SMU_FW + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + +config UDELAY_LAPIC_FIXED_FSB + int + default 200 + +# TODO: Sync these with definitions in PI vendorcode. +# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. +# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. + +config DCACHE_RAM_BASE + hex + default 0x30000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + +config DCACHE_BSP_STACK_SIZE + depends on C_ENVIRONMENT_BOOTBLOCK + hex + default 0x4000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x1600 + help + Increase this value if preram cbmem console is getting truncated + +config CPU_ADDR_BITS + int + default 48 + +config BOTTOMIO_POSITION + hex "Bottom of 32-bit IO space" + default 0xD0000000 + help + If PCI peripherals with big BARs are connected to the system + the bottom of the IO must be decreased to allocate such + devices. + + Declare the beginning of the 128MB-aligned MMIO region. This + option is useful when PCI peripherals requesting large address + ranges are present. + +config MMCONF_BASE_ADDRESS + hex + default 0xF8000000 + +config MMCONF_BUS_NUMBER + int + default 64 + +config VGA_BIOS_ID + string + default "1002,98e4" + help + The default VGA BIOS PCI vendor/device ID should be set to the + result of the map_oprom_vendev() function in northbridge.c. + +config VGA_BIOS_FILE + string + default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin" + +config S3_VGA_ROM_RUN + bool + default n + +config HEAP_SIZE + hex + default 0xc0000 + +config EHCI_BAR + hex + default 0xfef00000 + +config STONEYRIDGE_XHCI_ENABLE + bool "Enable Stoney Ridge XHCI Controller" + default y + help + The XHCI controller must be enabled and the XHCI firmware + must be added in order to have USB 3.0 support configured + by coreboot. The OS will be responsible for enabling the XHCI + controller if the XHCI firmware is available but the + XHCI controller is not enabled by coreboot. + +config STONEYRIDGE_XHCI_FWM + bool "Add xhci firmware" + default y + help + Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0 + +config STONEYRIDGE_GEC_FWM + bool + default n + help + Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC. + Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. + +config STONEYRIDGE_XHCI_FWM_FILE + string "XHCI firmware path and filename" + default "3rdparty/blobs/soc/amd/stoneyridge/xhci.bin" + depends on STONEYRIDGE_XHCI_FWM + +config STONEYRIDGE_GEC_FWM_FILE + string "GEC firmware path and filename" + depends on STONEYRIDGE_GEC_FWM + +config AMD_PUBKEY_FILE + string "AMD public Key" + default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin" + +config STONEYRIDGE_SATA_MODE + int "SATA Mode" + default 0 + range 0 6 + help + Select the mode in which SATA should be driven. + The default is NATIVE. + 0: NATIVE mode does not require a ROM. + 2: AHCI may work with or without AHCI ROM. It depends on the payload support. + For example, seabios does not require the AHCI ROM. + 3: LEGACY IDE + 4: IDE to AHCI + 5: AHCI7804: ROM Required, and AMD driver required in the OS. + 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. + +comment "NATIVE" + depends on STONEYRIDGE_SATA_MODE = 0 + +comment "AHCI" + depends on STONEYRIDGE_SATA_MODE = 2 + +comment "LEGACY IDE" + depends on STONEYRIDGE_SATA_MODE = 3 + +comment "IDE to AHCI" + depends on STONEYRIDGE_SATA_MODE = 4 + +comment "AHCI7804" + depends on STONEYRIDGE_SATA_MODE = 5 + +comment "IDE to AHCI7804" + depends on STONEYRIDGE_SATA_MODE = 6 + +if STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5 + +config AHCI_ROM_ID + string "AHCI device PCI IDs" + default "1022,7801" if STONEYRIDGE_SATA_MODE = 2 + default "1022,7804" if STONEYRIDGE_SATA_MODE = 5 + +endif # STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5 + +config STONEYRIDGE_LEGACY_FREE + bool "System is legacy free" + help + Select y if there is no keyboard controller in the system. + This sets variables in AGESA and ACPI. + +config SERIRQ_CONTINUOUS_MODE + bool + default n + help + Set this option to y for serial IRQ in continuous mode. + Otherwise it is in quiet mode. + +config STONEYRIDGE_ACPI_IO_BASE + hex + default 0x400 + help + Base address for the ACPI registers. + This value must match the hardcoded value of AGESA. + +config STONEYRIDGE_UART + bool "UART controller on Stoney Ridge" + default n + select DRIVERS_UART_8250MEM + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO + select UART_OVERRIDE_REFCLK + help + There are two UART controllers in Stoney Ridge. + The UART registers are memory-mapped. UART + controller 0 registers range from FEDC_6000h + to FEDC_6FFFh. UART controller 1 registers + range from FEDC_8000h to FEDC_8FFFh. + +config CONSOLE_UART_BASE_ADDRESS + depends on CONSOLE_SERIAL + hex + default 0xfedc6000 + +config SMM_TSEG_SIZE + hex + default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER + default 0x0 + +config SMM_RESERVED_SIZE + hex + default 0x150000 + +config SMM_MODULE_STACK_SIZE + hex + default 0x800 + +config ACPI_CPU_STRING + string + default "\\_PR.P%03d" + +config ACPI_BERT + bool "Build ACPI BERT Table" + default y + depends on HAVE_ACPI_TABLES + help + Report Machine Check errors identified in POST to the OS in an + ACPI Boot Error Record Table. This option reserves an 8MB region + for building the error structures. + +config USE_PSPSECUREOS + bool "Include PSP SecureOS blobs in AMD firmware" + default y + help + Include the PspSecureOs, PspTrustlet and TrustletKey binaries + in the amdfw section. + + If unsure, answer 'y' + +config SOC_AMD_SMU_FANLESS + bool + depends on SOC_AMD_PSP_SELECTABLE_SMU_FW + default n if SOC_AMD_SMU_NOTFANLESS + default y + +config SOC_AMD_SMU_FANNED + bool + depends on SOC_AMD_PSP_SELECTABLE_SMU_FW + default n + select SOC_AMD_SMU_NOTFANLESS + +config SOC_AMD_SMU_NOTFANLESS # helper symbol - do not use + bool + depends on SOC_AMD_PSP_SELECTABLE_SMU_FW + +config AMDFW_OUTSIDE_CBFS + bool "The AMD firmware is outside CBFS" + default n + help + The AMDFW (PSP) is typically locatable in cbfs. Select this + option to manually attach the generated amdfw.rom outside of + cbfs. The location is selected by the FWM position. + +config AMD_FWM_POSITION_INDEX + int "Firmware Directory Table location (0 to 5)" + range 0 5 + default 0 if BOARD_ROMSIZE_KB_512 + default 1 if BOARD_ROMSIZE_KB_1024 + default 2 if BOARD_ROMSIZE_KB_2048 + default 3 if BOARD_ROMSIZE_KB_4096 + default 4 if BOARD_ROMSIZE_KB_8192 + default 5 if BOARD_ROMSIZE_KB_16384 + help + Typically this is calculated by the ROM size, but there may + be situations where you want to put the firmware directory + table in a different location. + 0: 512 KB - 0xFFFA0000 + 1: 1 MB - 0xFFF20000 + 2: 2 MB - 0xFFE20000 + 3: 4 MB - 0xFFC20000 + 4: 8 MB - 0xFF820000 + 5: 16 MB - 0xFF020000 + +comment "AMD Firmware Directory Table set to location for 512KB ROM" + depends on AMD_FWM_POSITION_INDEX = 0 +comment "AMD Firmware Directory Table set to location for 1MB ROM" + depends on AMD_FWM_POSITION_INDEX = 1 +comment "AMD Firmware Directory Table set to location for 2MB ROM" + depends on AMD_FWM_POSITION_INDEX = 2 +comment "AMD Firmware Directory Table set to location for 4MB ROM" + depends on AMD_FWM_POSITION_INDEX = 3 +comment "AMD Firmware Directory Table set to location for 8MB ROM" + depends on AMD_FWM_POSITION_INDEX = 4 +comment "AMD Firmware Directory Table set to location for 16MB ROM" + depends on AMD_FWM_POSITION_INDEX = 5 + +config DIMM_SPD_SIZE + int + default 512 # DDR4 + +config RO_REGION_ONLY + string + depends on CHROMEOS + default "apu/amdfw" + +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 + +config MAINBOARD_POWER_RESTORE + def_bool n + help + This option determines what state to go to once power is restored + after having been lost in S0. Select this option to automatically + return to S0. Otherwise the system will remain in S5 once power + is restored. + +endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c new file mode 100644 index 0000000000..d1ea24ffd5 --- /dev/null +++ b/src/soc/amd/picasso/acpi.c @@ -0,0 +1,406 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write Kern IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + CONFIG_MAX_CPUS+1, IO_APIC2_ADDR, 24); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xf); + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, + 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} + +/* + * Reference section 5.2.9 Fixed ACPI Description Table (FADT) + * in the ACPI 3.0b specification. + */ +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", STONEYRIDGE_ACPI_IO_BASE); + + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = get_acpi_table_revision(FADT); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = asl_revision; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->preferred_pm_profile = FADT_PM_PROFILE; + fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0; /* Not supported */ + fadt->pstate_cnt = 0; /* Not supported */ + fadt->cst_cnt = 0; /* Not supported */ + acpi_disable_sci(); + } else { + fadt->smi_cmd = 0; /* disable system management mode */ + fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ + fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ + fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ + fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ + fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ + acpi_enable_sci(); + } + + fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = 0x0000; + fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; + fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->gpe1_blk = 0x0000; /* No gpe1 block */ + + fadt->pm1_evt_len = 4; /* 32 bits */ + fadt->pm1_cnt_len = 2; /* 16 bits */ + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; /* 32 bits */ + fadt->gpe0_blk_len = 8; /* 64 bits */ + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ + fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alarm work */ + fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ + fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_PLATFORM_CLOCK | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON; + + /* Format is from 5.2.3.1: Generic Address Structure */ + /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */ + /* 8 bit write of value 0x06 to 0xCF9 in IO space */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = SYS_RESET; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + + fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ + fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ + + fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + /* + * Note: Under this current AMD C state implementation, this is no + * longer used and should not be reported to OS. + */ + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = 0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); +} + +void generate_cpu_entries(struct device *device) +{ + int cores, cpu; + + /* Stoney Ridge is single node, just report # of cores */ + cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK; + cores++; /* number of cores is CmpCap+1 */ + + printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores); + + /* Generate BSP \_PR.P000 */ + acpigen_write_processor(0, ACPI_GPE0_BLK, 6); + acpigen_pop_len(); + + /* Generate AP \_PR.Pxxx */ + for (cpu = 1; cpu < cores; cpu++) { + acpigen_write_processor(cpu, 0, 0); + acpigen_pop_len(); + } +} + +unsigned long southbridge_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + return acpi_write_hpet(device, current, rsdp); +} + +static void acpi_create_gnvs(struct global_nvs_t *gnvs) +{ + /* Clear out GNVS. */ + memset(gnvs, 0, sizeof(*gnvs)); + + if (CONFIG(CONSOLE_CBMEM)) + gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); + + if (CONFIG(CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&gnvs->chromeos); + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } + + /* Set unknown wake source */ + gnvs->pm1i = ~0ULL; + gnvs->gpei = ~0ULL; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); +} + +void southbridge_inject_dsdt(struct device *device) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs) { + acpi_create_gnvs(gnvs); + + /* Add it to DSDT */ + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); + acpigen_pop_len(); + } +} + +static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) +{ + /* + * Store (\_SB.GPR2 (addr), Local5) + * \_SB.GPR2 is used to read control byte 2 from control register. + * / It is defined in gpio_lib.asl. + */ + acpigen_write_store(); + acpigen_emit_namestring("\\_SB.GPR2"); + acpigen_write_integer(addr); + acpigen_emit_byte(LOCAL5_OP); +} + +static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) +{ + if (gpio_num >= SOC_GPIO_TOTAL_PINS) { + printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" + " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); + return -1; + } + uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num); + + acpigen_soc_get_gpio_in_local5(addr); + + /* If (And (Local5, mask)) */ + acpigen_write_if_and(LOCAL5_OP, mask); + + /* Store (One, Local0) */ + acpigen_write_store_ops(ONE_OP, LOCAL0_OP); + + acpigen_pop_len(); /* If */ + + /* Else */ + acpigen_write_else(); + + /* Store (Zero, Local0) */ + acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); + + acpigen_pop_len(); /* Else */ + + return 0; +} + +static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) +{ + if (gpio_num >= SOC_GPIO_TOTAL_PINS) { + printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" + " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); + return -1; + } + uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num); + + /* Store (0x40, Local0) */ + acpigen_write_store(); + acpigen_write_integer(GPIO_PIN_OUT); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_soc_get_gpio_in_local5(addr); + + if (val) { + /* Or (Local5, GPIO_PIN_OUT, Local5) */ + acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP); + } else { + /* Not (GPIO_PIN_OUT, Local6) */ + acpigen_write_not(LOCAL0_OP, LOCAL6_OP); + + /* And (Local5, Local6, Local5) */ + acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); + } + + /* + * SB.GPW2 (addr, Local5) + * \_SB.GPW2 is used to write control byte in control register + * / byte 2. It is defined in gpio_lib.asl. + */ + acpigen_emit_namestring("\\_SB.GPW2"); + acpigen_write_integer(addr); + acpigen_emit_byte(LOCAL5_OP); + + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN); +} + +int acpigen_soc_get_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT); +} + +int acpigen_soc_set_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_set_gpio_val(gpio_num, 1); +} + +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_set_gpio_val(gpio_num, 0); +} diff --git a/src/soc/amd/picasso/acpi/acpi_wake_source.asl b/src/soc/amd/picasso/acpi/acpi_wake_source.asl new file mode 100644 index 0000000000..fa01802618 --- /dev/null +++ b/src/soc/amd/picasso/acpi/acpi_wake_source.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Method (_SWS) + { + /* Index into PM1 for device that caused wake */ + Return (\PM1I) + } +} + +Scope (\_GPE) +{ + Method (_SWS) + { + /* Index into GPE for device that caused wake */ + Return (\GPEI) + } +} diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl new file mode 100644 index 0000000000..414326ecf1 --- /dev/null +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Required function by EC, Notify OS to re-read CPU tables */ +Method (PNOT) +{ +} + +/* + * Processor Object + */ +/* These devices are created at runtime */ +External (\_PR.P000, DeviceObj) +External (\_PR.P001, DeviceObj) +External (\_PR.P002, DeviceObj) +External (\_PR.P003, DeviceObj) +External (\_PR.P004, DeviceObj) +External (\_PR.P005, DeviceObj) +External (\_PR.P006, DeviceObj) +External (\_PR.P007, DeviceObj) + +/* Return a package containing enabled processor entries */ +Method (PPKG) +{ + If (LGreaterEqual (\PCNT, 2)) { + Return (Package () + { + \_PR.P000, + \_PR.P001 + }) + } Else { + Return (Package () + { + \_PR.P000 + }) + } +} diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl new file mode 100644 index 0000000000..03d205f8d3 --- /dev/null +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Alexandru Gagniuc for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * NOTE: The layout of the GNVS structure below must match the layout in + * soc/amd/stoneyridge/include/soc/nvs.h !!! + * + */ + +External (NVSA) + +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + Offset (0x00), + PCNT, 8, // 0x00 - Processor Count + PPCM, 8, // 0x01 - Max PPC State + LIDS, 8, // 0x02 - LID State + PWRS, 8, // 0x03 - AC Power State + DPTE, 8, // 0x04 - Enable DPTF + CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console + PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index + GPEI, 64, // 0x11 - 0x18 - GPE Wake Source + NHLA, 64, // 0x19 - 0x20 - NHLT Address + NHLL, 32, // 0x21 - 0x24 - NHLT Length + PRT0, 32, // 0x25 - 0x28 - PERST_0 Address + SCDP, 8, // 0x29 - SD_CD GPIO portid + SCDO, 8, // 0x2A - GPIO pad offset relative to the community + TMPS, 8, // 0x2B - Temperature Sensor ID + TLVL, 8, // 0x2C - Throttle Level Limit + FLVL, 8, // 0x2D - Current FAN Level + TCRT, 8, // 0x2E - Critical Threshold + TPSV, 8, // 0x2F - Passive Threshold + TMAX, 8, // 0x30 - CPU Tj_max + Offset (0x34), // 0x34 - AOAC Device Enables + , 5, + IC0E, 1, // I2C0, 5 + IC1E, 1, // I2C1, 6 + IC2E, 1, // I2C2, 7 + IC3E, 1, // I2C3, 8 + , 2, + UT0E, 1, // UART0, 11 + UT1E, 1, // UART1, 12 + , 2, + ST_E, 1, // SATA, 15 + , 2, + EHCE, 1, // EHCI, 18 + , 4, + XHCE, 1, // XCHI, 23 + SD_E, 1, // SD, 24 + , 2, + ESPI, 1, // ESPI, 27 + , 4, + FW00, 16, // 0x38 - xHCI FW ROM addr, boot RAM + FW02, 16, // 0x3A - xHCI FW ROM addr, Instruction RAM + FW01, 32, // 0x3C - xHCI FW RAM addr, boot RAM + FW03, 32, // 0x40 - xHCI FW RAM addr, Instruction RAM + EH10, 32, // 0x44 - EHCI BAR + /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ + Offset (0x100), + #include +} diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl new file mode 100644 index 0000000000..fe78534403 --- /dev/null +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Note: Only need HID on Primary Bus */ +External (TOM1) +External (TOM2) +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ +Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ +Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + +/* Describe the Northbridge devices */ + +Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ +{ + Return(Zero) +} + +Method(_STA, 0, NotSerialized) +{ + Return(0x0B) /* Status is visible */ +} + +Method(_PRT,0, NotSerialized) +{ + If(PMOD) + { + Return(APR0) /* APIC mode */ + } + Return (PR0) /* PIC Mode */ +} + +Device(AMRT) { + Name(_ADR, 0x00000000) +} /* end AMRT */ + +/* Internal Graphics */ +Device(IGFX) { + Name(_ADR, 0x00010000) +} + +/* Gpp 0 */ +Device(PBR4) { + Name(_ADR, 0x00020001) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR4 */ + +/* Gpp 1 */ +Device(PBR5) { + Name(_ADR, 0x00020002) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR5 */ + +/* Gpp 2 */ +Device(PBR6) { + Name(_ADR, 0x00020003) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR6 */ + +/* Gpp 3 */ +Device(PBR7) { + Name(_ADR, 0x00020004) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR7 */ + +/* Gpp 4 */ +Device(PBR8) { + Name(_ADR, 0x00020005) + Method(_PRT,0) { + If(PMOD){ Return(APS8) } /* APIC mode */ + Return (PS8) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ + +Device(AZHD) { /* 0:9.2 - HD Audio */ + Name(_ADR, 0x00090002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6c), + MMDT, 16, + } + + Method (_INI, 0, NotSerialized) + { + If (LEqual (OSVR, 0x03)) + { + Store (Zero, NSEN) + Store (One, NSDO) + Store (One, NSDI) + } + } +} /* end AZHD */ diff --git a/src/soc/amd/picasso/acpi/pci_int.asl b/src/soc/amd/picasso/acpi/pci_int.asl new file mode 100644 index 0000000000..617b9eb86c --- /dev/null +++ b/src/soc/amd/picasso/acpi/pci_int.asl @@ -0,0 +1,469 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ + OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000a0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000a0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000a0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000a0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12c), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1a0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1a8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1ac), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1b0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22c), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2a0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2a8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2aC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2b0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + + Method(CIRQ, 0x00, NotSerialized){ + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PIRA) { + Return(0x0b) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_SRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PIRB) { + Return(0x0b) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PIRC) { + Return(0x0b) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIRD) { + Return(0x0b) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRD) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PIRE) { + Return(0x0b) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PIRF) { + Return(0x0b) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PIRG) { + Return(0x0b) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRG) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PIRH) { + Return(0x0b) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl new file mode 100644 index 0000000000..925187209c --- /dev/null +++ b/src/soc/amd/picasso/acpi/pcie.asl @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* PCI IRQ mapping registers, C00h-C01h. */ + OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000c14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000c50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000c52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000c6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000Cd0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ + OperationRegion(PIOR, SystemIO, 0x00000Cd6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x60), /* AcpiPm1EvgBlk */ + P1EB, 16, + Offset(0xee), + UPWS, 3, + } + OperationRegion (P1E0, SystemIO, P1EB, 0x04) + Field (P1E0, ByteAcc, Nolock, Preserve) { + Offset(0x02), + , 14, + PEWD, 1, + } diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl new file mode 100644 index 0000000000..e7975f8d94 --- /dev/null +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -0,0 +1,153 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +Device (AAHB) +{ + Name (_HID, "AAHB0000") + Name (_UID, 0x0) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (GPIO) +{ + Name (_HID, GPIO_DEVICE_NAME) + Name (_CID, GPIO_DEVICE_NAME) + Name (_UID, 0) + Name (_DDN, GPIO_DEVICE_DESC) + + Name (_CRS, ResourceTemplate() + { + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { 7 } + Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (FUR0) +{ + Name (_HID, "AMD0020") + Name (_UID, 0x0) + Name (_CRS, ResourceTemplate() + { + IRQ (Edge, ActiveHigh, Exclusive) { 10 } + Memory32Fixed (ReadWrite, 0xFEDC6000, 0x2000) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (FUR1) { + Name (_HID, "AMD0020") + Name (_UID, 0x1) + Name (_CRS, ResourceTemplate() + { + IRQ (Edge, ActiveHigh, Exclusive) { 11 } + Memory32Fixed (ReadWrite, 0xFEDC8000, 0x2000) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (I2CA) { + Name (_HID, "AMD0010") + Name (_UID, 0x0) + Name (_CRS, ResourceTemplate() + { + IRQ (Edge, ActiveHigh, Exclusive) { 3 } + Memory32Fixed (ReadWrite, 0xFEDC2000, 0x1000) + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (I2CB) +{ + Name (_HID, "AMD0010") + Name (_UID, 0x1) + Name (_CRS, ResourceTemplate() + { + IRQ (Edge, ActiveHigh, Exclusive) { 15 } + Memory32Fixed (ReadWrite, 0xFEDC3000, 0x1000) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (I2CC) { + Name (_HID, "AMD0010") + Name (_UID, 0x2) + Name (_CRS, ResourceTemplate() + { + IRQ (Edge, ActiveHigh, Exclusive) { 6 } + Memory32Fixed (ReadWrite, 0xFEDC4000, 0x1000) + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (I2CD) +{ + Name (_HID, "AMD0010") + Name (_UID, 0x3) + Name (_CRS, ResourceTemplate() { + IRQ (Edge, ActiveHigh, Exclusive) { 14 } + Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (MISC) +{ + Name (_HID, "AMD0040") + Name (_UID, 0x3) + Name (_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl new file mode 100644 index 0000000000..3623814080 --- /dev/null +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -0,0 +1,619 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +External(\_SB.ALIB, MethodObj) + +/* System Bus */ +/* _SB.PCI0 */ + +/* Operating System Capabilities Method */ +Method(_OSC,4) +{ + /* Check for proper PCI/PCIe UUID */ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } Else { + CreateDWordField(Arg3,0,CDW1) + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } +} + +/* Describe the Southbridge devices */ + +/* 0:11.0 - SATA */ +Device(STCR) { + Name(_ADR, 0x00110000) +} /* end STCR */ + +/* 0:14.0 - SMBUS */ +Device(SBUS) { + Name(_ADR, 0x00140000) +} /* end SBUS */ + +#include "usb.asl" + +/* 0:14.2 - I2S Audio */ + +/* 0:14.3 - LPC */ +#include + +/* 0:14.7 - SD Controller */ +Device(SDCN) { + Name(_ADR, 0x00140007) + + Method(_PS0) { + FDDC(24, 0) + } + Method(_PS3) { + FDDC(24, 3) + } + Method(_PSC) { + Return(SDTD) + } +} /* end SDCN */ + +Name(CRES, ResourceTemplate() { + /* Set the Bus number and Secondary Bus number for the PCI0 device + * The Secondary bus range for PCI0 lets the system + * know what bus values are allowed on the downstream + * side of this PCI bus if there is a PCI-PCI bridge. + * PCI busses can have 256 secondary busses which + * range from [0-0xFF] but they do not need to be + * sequential. + */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x00ff, /* range maximum */ + 0x0000, /* translation */ + 0x0100, /* length */ + ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ + + IO(Decode16, 0x0cf8, 0x0cf8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0cf7, /* range maximum */ + 0x0000, /* translation */ + 0x0cf8 /* length */ + ) + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x03b0, /* range minimum */ + 0x03df, /* range maximum */ + 0x0000, /* translation */ + 0x0030 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0d00, /* range minimum */ + 0xffff, /* range maximum */ + 0x0000, /* translation */ + 0xf300 /* length */ + ) + + Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) +}) /* End Name(_SB.PCI0.CRES) */ + +Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(CRES) /* note to change the Name buffer */ +} /* end of Method(_SB.PCI0._CRS) */ + +/* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ +Method(_INI, 0, Serialized) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + OSFL() + + /* Send ALIB Function 1 the AC/DC state */ + Name(F1BF, Buffer(0x03){}) + CreateWordField(F1BF, 0, F1SZ) + CreateByteField(F1BF, 2, F1DA) + + Store(3, F1SZ) + Store(\PWRS, F1DA) + + \_SB.ALIB(1, F1BF) + +} /* End Method(_SB._INI) */ + +Method(OSFL, 0){ + + if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + + if (CondRefOf(\_OSI)) + { + Store(1, OSVR) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSVR) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSVR) /* Linux */ + } Else { + Store(4, OSVR) /* Gotta be WinCE */ + } + } + Return(OSVR) +} + +OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000) +Field( SMIC, ByteAcc, NoLock, Preserve) { + /* MISC registers */ + offset (0x03ee), + U3PS, 2, /* Usb3PowerSel */ + + offset (0x0e28), + ,29 , + SARP, 1, /* Sata Ref Clock Powerdown */ + U2RP, 1, /* Usb2 Ref Clock Powerdown */ + U3RP, 1, /* Usb3 Ref Clock Powerdown */ + + /* XHCI_PM registers */ + offset (0x1c00), + , 1, + ,6, + U3PY, 1, + , 7, + UD3P, 1, /* bit 15 */ + U3PR, 1, /* bit 16 */ + , 11, + FWLM, 1, /* FirmWare Load Mode */ + FPLS, 1, /* Fw PreLoad Start */ + FPLC, 1, /* Fw PreLoad Complete */ + + offset (0x1c04), + UA04, 16, + , 15, + ROAM, 1, /* 1= ROM 0=RAM */ + + offset (0x1c08), + UA08, 32, + + /* AOAC Registers */ + offset (0x1e4a), /* I2C0 D3 Control */ + I0TD, 2, + , 1, + I0PD, 1, + offset (0x1e4b), /* I2C0 D3 State */ + I0DS, 3, + + offset (0x1e4c), /* I2C1 D3 Control */ + I1TD, 2, + , 1, + I1PD, 1, + offset (0x1e4d), /* I2C1 D3 State */ + I1DS, 3, + + offset (0x1e4e), /* I2C2 D3 Control */ + I2TD, 2, + , 1, + I2PD, 1, + offset (0x1e4f), /* I2C2 D3 State */ + I2DS, 3, + + offset (0x1e50), /* I2C3 D3 Control */ + I3TD, 2, + , 1, + I3PD, 1, + offset (0x1e51), /* I2C3 D3 State */ + I3DS, 3, + + offset (0x1e56), /* UART0 D3 Control */ + U0TD, 2, + , 1, + U0PD, 1, + offset (0x1e57), /* UART0 D3 State */ + U0DS, 3, + + offset (0x1e58), /* UART1 D3 Control */ + U1TD, 2, + , 1, + U1PD, 1, + offset (0x1e59), /* UART1 D3 State */ + U1DS, 3, + + offset (0x1e5e), /* SATA D3 Control */ + SATD, 2, + , 1, + SAPD, 1, + offset (0x1e5f), /* SATA D3 State */ + SADS, 3, + + offset (0x1e64), /* USB2 D3 Control */ + U2TD, 2, + , 1, + U2PD, 1, + offset (0x1e65), /* USB2 D3 State */ + U2DS, 3, + + offset (0x1e6e), /* USB3 D3 Control */ + U3TD, 2, + , 1, + U3PD, 1, + offset (0x1e6f), /* USB3 D3 State */ + U3DS, 3, + + offset (0x1e70), /* SD D3 Control */ + SDTD, 2, + , 1, + SDPD, 1, + , 1, + , 1, + SDRT, 1, + SDSC, 1, + + offset (0x1e71), /* SD D3 State */ + SDDS, 3, + + offset (0x1e80), /* Shadow Register Request */ + , 15, + RQ15, 1, + , 2, + RQ18, 1, + , 4, + RQ23, 1, + RQ24, 1, + , 5, + RQTY, 1, + offset (0x1e84), /* Shadow Register Status */ + , 15, + SASR, 1, /* SATA 15 Shadow Reg Request Status Register */ + , 2, + U2SR, 1, /* USB2 18 Shadow Reg Request Status Register */ + , 4, + U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */ + SDSR, 1, /* SD 24 Shadow Reg Request Status Register */ + + offset (0x1ea0), /* PwrGood Control */ + PG1A, 1, + PG2_, 1, + ,1, + U3PG, 1, /* Usb3 Power Good BIT3 */ + + offset (0x1ea3), /* PwrGood Control b[31:24] */ + PGA3, 8 , +} + +OperationRegion(FCFG, SystemMemory, PCBA, 0x01000000) +Field(FCFG, DwordAcc, NoLock, Preserve) +{ + /* XHCI */ + Offset(0x00080010), /* Base address */ + XHBA, 32, + Offset(0x0008002c), /* Subsystem ID / Vendor ID */ + XH2C, 32, + + Offset(0x00080048), /* Indirect PCI Index Register */ + IDEX, 32, + DATA, 32, + Offset(0x00080054), /* PME Control / Status */ + U_PS, 2, + + /* EHCI */ + Offset(0x00090004), /* Control */ + , 1, + EHME, 1, + Offset(0x00090010), /* Base address */ + EHBA, 32, + Offset(0x0009002c), /* Subsystem ID / Vendor ID */ + EH2C, 32, + Offset(0x00090054), /* EHCI Spare 1 */ + EH54, 8, + Offset(0x00090064), /* Misc Control 2 */ + EH64, 8, + + Offset(0x000900c4), /* PME Control / Status */ + E_PS, 2, + + /* LPC Bridge */ + Offset(0x000a30cb), /* ClientRomProtect[31:24] */ + , 7, + AUSS, 1, /* AutoSizeStart */ +} + +/* + * Arg0:device: + * 5=I2C0, 6=I2C1, 7=I2C2, 8=I2C3, 11=UART0, 12=UART1, + * 15=SATA, 18=EHCI, 23=xHCI, 24=SD + * Arg1:D-state + */ +Mutex (FDAS, 0) /* FCH Device AOAC Semophore */ +Method(FDDC, 2, Serialized) +{ + Acquire(FDAS, 0xffff) + + if(LEqual(Arg1, 0)) { + Switch(ToInteger(Arg0)) { + Case(Package() {5, 15, 24}) { + Store(One, PG1A) + } + Case(Package() {6, 7, 8, 11, 12, 18}) { + Store(One, PG2_) + } + } + /* put device into D0 */ + Switch(ToInteger(Arg0)) + { + Case(5) { + Store(0x00, I0TD) + Store(One, I0PD) + Store(I0DS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(I0DS, Local0) + } + } + Case(6) { + Store(0x00, I1TD) + Store(One, I1PD) + Store(I1DS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(I1DS, Local0) + } + } + Case(7) { + Store(0x00, I2TD) + Store(One, I2PD) + Store(I2DS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(I2DS, Local0) + } + } + Case(8) {Store(0x00, I3TD) + Store(One, I3PD) + Store(I3DS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(I3DS, Local0) + } + } + Case(11) { + Store(0x00, U0TD) + Store(One, U0PD) + Store(U0DS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(U0DS, Local0) + } + } + Case(12) { + Store(0x00, U1TD) + Store(One, U1PD) + Store(U1DS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(U1DS, Local0) + } + } +/* todo Case(15) { STD0()} */ /* SATA */ + Case(18) { U2D0()} /* EHCI */ + Case(23) { U3D0()} /* XHCI */ + Case(24) { /* SD */ + Store(0x00, SDTD) + Store(One, SDPD) + Store(SDDS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(SDDS, Local0) + } + } + } + } else { + /* put device into D3cold */ + Switch(ToInteger(Arg0)) + { + Case(5) { + Store(Zero, I0PD) + Store(I0DS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(I0DS, Local0) + } + Store(0x03, I0TD) + } + Case(6) { + Store(Zero, I1PD) + Store(I1DS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(I1DS, Local0) + } + Store(0x03, I1TD) + } + Case(7) { + Store(Zero, I2PD) + Store(I2DS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(I2DS, Local0) + } + Store(0x03, I2TD)} + Case(8) { + Store(Zero, I3PD) + Store(I3DS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(I3DS, Local0) + } + Store(0x03, I3TD) + } + Case(11) { + Store(Zero, U0PD) + Store(U0DS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(U0DS, Local0) + } + Store(0x03, U0TD) + } + Case(12) { + Store(Zero, U1PD) + Store(U1DS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(U1DS, Local0) + } + Store(0x03, U1TD) + } +/* todo Case(15) { STD3()} */ /* SATA */ + Case(18) { U2D3()} /* EHCI */ + Case(23) { U3D3()} /* XHCI */ + Case(24) { /* SD */ + Store(Zero, SDPD) + Store(SDDS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(SDDS, Local0) + } + Store(0x03, SDTD) + } + } + /* Turn off Power */ + if(LEqual(I0TD, 3)) { + if(LEqual(SATD, 3)) { + if(LEqual(SDTD, 3)) { Store(Zero, PG1A) } + } + } + if(LEqual(I1TD, 3)) { + if(LEqual(I2TD, 3)) { + if(LEqual(I3TD, 3)) { + if(LEqual(U0TD, 3)) { + if(LEqual(U1TD, 3)) { + if(LEqual(U2TD, 3)) { + Store(Zero, PG2_) + } + } + } + } + } + } + } + Release(FDAS) +} + +Method(FPTS,0, Serialized) /* FCH _PTS */ +{ + if(LEqual(\XHCE, one)) { + if(LNotEqual(U3TD, 0x03)) { + FDDC(23, 3) + } + } + if(LNotEqual(U2TD, 0x03)) { + FDDC(18, 3) + } +} + +Method(FWAK,0, Serialized) /* FCH _WAK */ +{ + if(LEqual(\XHCE, one)) { + if(LEqual(U3TD, 0x03)) { + FDDC(23, 0) + } + } + if(LEqual(U2TD, 0x03)) { + FDDC(18, 0) + } + if(LEqual(\UT0E, zero)) { + if(LNotEqual(U0TD, 0x03)) { + FDDC(11, 3) + } + } + if(LEqual(\UT1E, zero)) { + if(LNotEqual(U1TD, 0x03)) { + FDDC(12, 3) + } + } + if(LEqual(\IC0E, zero)) { + if(LNotEqual(I0TD, 0x03)) { + FDDC(5, 3) + } + } + if(LEqual(\IC1E, zero)) { + if(LNotEqual(I1TD, 0x03)) { + FDDC(6, 3) + } + } + if(LEqual(\IC2E, zero)) { + if(LNotEqual(I2TD, 0x03)) { + FDDC(7, 3) + } + } + if(LEqual(\IC3E, zero)) { + if(LNotEqual(I3TD, 0x03)) { + FDDC(8, 3) + } + } +} + +/* + * Helper for setting a bit in AOACxA0 PwrGood Control + * Arg0: bit to set or clear + * Arg1: 0 = clear bit[Arg0], non-zero = set bit[Arg0] + */ +Method(PWGC,2, Serialized) +{ + And (PGA3, 0xdf, Local0) /* do SwUsb3SlpShutdown below */ + if(Arg1) { + Or(Arg0, Local0, Local0) + } else { + Not(Arg0, Local1) + And(Local1, Local0, Local0) + } + Store(Local0, PGA3) + if(LEqual(Arg0, 0x20)) { /* if SwUsb3SlpShutdown */ + Store(PGA3, Local0) + And(Arg0, Local0, Local0) + while(LNot(Local0)) { /* wait SwUsb3SlpShutdown to complete */ + Store(PGA3, Local0) + And(Arg0, Local0, Local0) + } + } +} diff --git a/src/soc/amd/picasso/acpi/sleepstates.asl b/src/soc/amd/picasso/acpi/sleepstates.asl new file mode 100644 index 0000000000..d4aabdb7af --- /dev/null +++ b/src/soc/amd/picasso/acpi/sleepstates.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ +Name(SSFG, 0x09) +If (CONFIG(HAVE_ACPI_RESUME)) { + Store(0x0D, SSFG) +} + +/* Supported sleep states: */ +Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + +If (And(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ +} +If (And(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ +} +If (And(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ +} +If (And(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ +} + +Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl new file mode 100644 index 0000000000..52c7ee6c00 --- /dev/null +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(PCI0) { + /* Describe the AMD Northbridge */ + #include "northbridge.asl" + + /* Describe the AMD Fusion Controller Hub */ + #include "sb_pci0_fch.asl" +} + +/* Describe PCI INT[A-H] for the Southbridge */ +#include "pci_int.asl" + +/* Describe the devices in the Southbridge */ +#include "sb_fch.asl" + +/* Add GPIO library */ +#include diff --git a/src/soc/amd/picasso/acpi/usb.asl b/src/soc/amd/picasso/acpi/usb.asl new file mode 100644 index 0000000000..f2ee8f6427 --- /dev/null +++ b/src/soc/amd/picasso/acpi/usb.asl @@ -0,0 +1,392 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* 0:12.0 - EHCI */ +Device(EHC0) { + Name(_ADR, 0x00120000) + Name(_PRW, Package() { 0xb, 3 }) + Device (RHUB) { + Name (_ADR, Zero) + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + } + + Name(_PR0, Package() { P0U2 }) /* Indicate support for D0 */ + Name(_PR3, Package() { P3U2 }) /* Indicate support for D3cold */ + + Method(_S0W,0) { + Return(0) + } + + Method(_S3W,0) { + Return(4) + } + + Method(_S4W,0) { + Return(4) + } +} /* end EHC0 */ + + +/* 0:10.0 - XHCI 0*/ +Device(XHC0) { + Name(_ADR, 0x00100000) + Name(_PRW, Package() { 0xb, 3 }) + Device (SS01) { Name (_ADR, 1) } + Device (SS02) { Name (_ADR, 2) } + Device (SS03) { Name (_ADR, 3) } + + Name(_PR0, Package() { P0U3 }) /* Indicate support for D0 */ + Name(_PR3, Package() { P3U3 }) /* Indicate support for D3cold */ + + Method(_S0W,0) { + Return(0) + } + + Method(_S3W,0) { + Return(4) + } + + Method(_S4W,0) { + Return(4) + } + +} /* end XHC0 */ + +Scope(\_SB) +{ + Name(XHD0, 0) + Name(XHD3, 0) + PowerResource(P0U3, 0, 0) { + Method(_STA) { + Return(XHD0) + } + Method(_ON) { + Store(0x01, XHD0) + } + Method(_OFF) { + Store(0x00, XHD0) + } + } + PowerResource(P3U3, 0, 0) { + Method(_STA) { + Return(XHD3) + } + Method(_ON) { + Store(0x01, XHD3) + } + Method(_OFF) { + Store(0x00, XHD3) + } + } + + Name(EHD0, 0) + Name(EHD3, 0) + PowerResource(P0U2, 0, 0) { + Method(_STA) { + Return(EHD0) + } + Method(_ON) { + Store(0x01, EHD0) + } + Method(_OFF) { + Store(0x00, EHD0) + } + } + PowerResource(P3U2, 0, 0) { + Method(_STA) { + Return(EHD3) + } + Method(_ON) { + Store(0x01, EHD3) + } + Method(_OFF) { + Store(0x00, EHD3) + } + } +} + +OperationRegion(EHMC, SystemMemory, EH10, 0x100) +Field(EHMC, DwordAcc, NoLock, Preserve) +{ + Offset(0xb0), + , 5, + ESIM, 1, +} + +Method(U2D3,0, Serialized) +{ + if (LNotEqual(EH10, Zero)) { + Store (EH10, EHBA) + Store (One, EHME) + Store (ESIM, SSIM) + } + + if (LEqual(E_PS, 3)) { + Store (Zero, RQTY) + Store (One, RQ18) + + Store (U2SR, Local0) + while (Local0) { + Store (U2SR, Local0) + } + + Store (Zero, U2PD) + + Store (U2DS, Local0) + while (LNotEqual(Local0, Zero)) { + Store (U2DS, Local0) + } + + Store (0x03,U2TD) + + if (LEqual(U3TD, 0x03)) { /* Shutdown USB2 PLL */ + PWGC (0x40, 0) + Store (One, U2RP) + } + } +} + +Method(U2D0,0, Serialized) +{ + PWGC (0x40, 1) + Store (Zero, U2RP) + Store (0x00,U2TD) + + Store (Zero, U2TD) + Store (One, U2PD) + + Store (U2DS, Local0) + while (LNotEqual(Local0,0x7)) { + Store (U2DS, Local0) + } + + Store (One, RQTY) + Store (One, RQ18) + Store (U2SR, Local0) + while (LNot(Local0)) { + Store (U2SR, Local0) + } + Store (EHID, EH2C) + + + if (LNotEqual(EH10, Zero)) { + Store (EH10, EHBA) + Store (One, EHME) + Store (SSIM, ESIM) + } + + Store (ES54, EH54) + Store (ES64, EH64) +} + +Method(LXFW,3, Serialized) //Load Xhci FirmWare +{ + Store (One, FWLM) /* Firmware Load Mode */ + Store (Arg0, ROAM) /* ROM/RAM */ + Store (Arg1, UA04) + Store (Arg2, UA08) + Store (One, FPLS) /* Firmware Preload Start */ + Store (FPLC, Local0) /* Firmware Preload Complete */ + while (LNot(Local0)) { + Store (FPLC, Local0) + } + Store (Zero, FPLS) +} + +Method(U3D3,0, Serialized) +{ + if (LEqual(U_PS, 3)) { + X0_S () + + Or (PGA3, 0x20, PGA3) /* SwUsb3SlpShutdown */ + And (PGA3, 0x20, Local0) + while (LNot(Local0)) { /* wait for it to complete */ + And (PGA3, 0x20, Local0) + } + Store (One, UD3P) /* U3P_D3Cold_PWRDN */ + + Store (Zero, U3PD) /* PwrOnDev */ + Store (U3DS, Local0) + while (Local0) { /* RstBState, RefClkOkState, PwrRstBState */ + Store (U3DS, Local0) + } + + Store (0x3, U3TD) /* TargetedDeviceState */ + + Store (One, U3RP) /* USB3_RefClk_Pwdn */ + + if (Lequal(U2TD, 0x3)) { /* If EHCI targeted in D3cold */ + And (PGA3, 0x9f, PGA3) /* SwUsb2S5RstB */ + Store (One, U2RP) /* USB2_RefClk_Pwdn */ + } + Store (Zero, U3PG) /* XhcPwrGood */ + Store (One, U3PS) /* Usb3PowerSel */ + } +} + +Method(U3D0,0, Serialized) +{ + Store (Zero, U3PS) /* Usb3PowerSel */ + Store (One, U3PG) /* XhcPwrGood */ + + Store (Zero, U2RP) + Store (Zero, U3RP) + + And (PGA3, 0xdf, Local0) + Or (Local0, 0x40, Local0) + Store (Local0, PGA3) /* SwUsb2S5RstB */ + + Store (Zero, U3TD) /* TargetedDeviceState */ + Store (One, U3PD) /* PwrOnDev */ + + Store (U3DS, Local0) /* wait for RstBState, RefClkOkState, PwrRstBState */ + while (LNot(Lequal(Local0, 0x7))) { + Store (U3DS, Local0) + } + + Store (U3PY, Local0) /* USB3 PHY Lock */ + while (LNot(Local0)) { + Store (U3PY, Local0) + } + + Store (Zero, U3PR) /* U3P_RESTORE_RESET */ + + Store (AUSS, Local0) /* AutoSizeStart */ + if (LNotEqual(Local0,1)) { + Store(One, AUSS) + } + Store (AUSS, Local0) + while (LNotEqual(Local0,1)) { + Store (AUSS, Local0) + } + + LXFW (1, FW00, FW01) + LXFW (0, FW02, FW03) + + X0_R () + + Store (One, U3PR) /* U3P_RESTORE_RESET */ + Store (Zero, UD3P) /* U3P_D3Cold_PWRDN */ + Store (One, U3TD) /* TargetedDeviceState */ +} + +Name (SVBF, Buffer (0x1000) {0}) /* length from FchCarrizo.asl, new fields */ +CreateDWordField(SVBF, 0x000, S000) /* will be easier to add from there */ +CreateDWordField(SVBF, 0x004, S004) +CreateDWordField(SVBF, 0x008, S008) +CreateDWordField(SVBF, 0x00C, S00C) +CreateDWordField(SVBF, 0x018, S018) +CreateDWordField(SVBF, 0x01C, S01C) +CreateDWordField(SVBF, 0x020, S020) +CreateDWordField(SVBF, 0x030, S030) +CreateDWordField(SVBF, 0x118, S118) +CreateDWordField(SVBF, 0x158, S158) +CreateDWordField(SVBF, 0x198, S198) +CreateDWordField(SVBF, 0x1D8, S1D8) +CreateDWordField(SVBF, 0x300, S300) +CreateDWordField(SVBF, 0x304, S304) +CreateDWordField(SVBF, 0x308, S308) +CreateDWordField(SVBF, 0x30C, S30C) +CreateDWordField(SVBF, 0x310, S310) +CreateDWordField(SVBF, 0x428, S428) +CreateDWordField(SVBF, 0x438, S438) +CreateDWordField(SVBF, 0x43C, S43C) +CreateDWordField(SVBF, 0x458, S458) +CreateDWordField(SVBF, 0x468, S468) +CreateDWordField(SVBF, 0x46C, S46C) +CreateDWordField(SVBF, 0x470, S470) +CreateDWordField(SVBF, 0x480, S480) +CreateDWordField(SVBF, 0x484, S484) +CreateDWordField(SVBF, 0x488, S488) +CreateDWordField(SVBF, 0x48C, S48C) +CreateDWordField(SVBF, 0x730, EHID) /* EHCI SSID */ +CreateDWordField(SVBF, 0x734, XHID) /* XHCI SSID */ +CreateByteField(SVBF, 0x740, ES54) /* EHCI PCIx54 */ +CreateByteField(SVBF, 0x741, ES64) /* EHCI PCIx64 */ +CreateDWordField(SVBF, 0x7B0, SSIM) /* EHCI SIM BIT */ + +Method(X0_S,0) +{ + Store (XH2C, XHID) + Store (0x00000000, IDEX) Store (DATA, S000) + Store (0x00000004, IDEX) Store (DATA, S004) + Store (0x00000008, IDEX) Store (DATA, S008) + Store (0x0000000c, IDEX) Store (DATA, S00C) + Store (0x00000018, IDEX) Store (DATA, S018) + Store (0x0000001c, IDEX) Store (DATA, S01C) + Store (0x00000020, IDEX) Store (DATA, S020) + Store (0x00000030, IDEX) Store (DATA, S030) + Store (0x00000118, IDEX) Store (DATA, S118) + Store (0x00000158, IDEX) Store (DATA, S158) + Store (0x00000198, IDEX) Store (DATA, S198) + Store (0x000001d8, IDEX) Store (DATA, S1D8) + Store (0x00000300, IDEX) Store (DATA, S300) + Store (0x00000304, IDEX) Store (DATA, S304) + Store (0x00000308, IDEX) Store (DATA, S308) + Store (0x0000030c, IDEX) Store (DATA, S30C) + Store (0x00000310, IDEX) Store (DATA, S310) + Store (0x40000028, IDEX) Store (DATA, S428) + Store (0x40000038, IDEX) Store (DATA, S438) + Store (0x4000003c, IDEX) Store (DATA, S43C) + Store (0x40000058, IDEX) Store (DATA, S458) + Store (0x40000068, IDEX) Store (DATA, S468) + Store (0x4000006c, IDEX) Store (DATA, S46C) + Store (0x40000070, IDEX) Store (DATA, S470) + Store (0x40000080, IDEX) Store (DATA, S480) + Store (0x40000084, IDEX) Store (DATA, S484) + Store (0x40000088, IDEX) Store (DATA, S488) + Store (0x4000008c, IDEX) Store (DATA, S48C) +} + +Method(X0_R,0) +{ + Store (XHID, XH2C) + Store (0x00000000, IDEX) Store (S000, DATA) + Store (0x00000004, IDEX) Store (S004, DATA) + Store (0x00000008, IDEX) Store (S008, DATA) + Store (0x0000000c, IDEX) Store (S00C, DATA) + Store (0x00000018, IDEX) Store (S018, DATA) + Store (0x0000001c, IDEX) Store (S01C, DATA) + Store (0x00000020, IDEX) Store (S020, DATA) + Store (0x00000030, IDEX) Store (S030, DATA) + Store (0x00000118, IDEX) Store (S118, DATA) + Store (0x00000158, IDEX) Store (S158, DATA) + Store (0x00000198, IDEX) Store (S198, DATA) + Store (0x000001d8, IDEX) Store (S1D8, DATA) + Store (0x00000300, IDEX) Store (S300, DATA) + Store (0x00000304, IDEX) Store (S304, DATA) + Store (0x00000308, IDEX) Store (S308, DATA) + Store (0x0000030c, IDEX) Store (S30C, DATA) + Store (0x00000310, IDEX) Store (S310, DATA) + Store (0x40000028, IDEX) Store (S428, DATA) + Store (0x40000038, IDEX) Store (S438, DATA) + Store (0x4000003c, IDEX) Store (S43C, DATA) + Store (0x40000058, IDEX) Store (S458, DATA) + Store (0x40000068, IDEX) Store (S468, DATA) + Store (0x4000006c, IDEX) Store (S46C, DATA) + Store (0x40000070, IDEX) Store (S470, DATA) + Store (0x40000080, IDEX) Store (S480, DATA) + Store (0x40000084, IDEX) Store (S484, DATA) + Store (0x40000088, IDEX) Store (S488, DATA) + Store (0x4000008c, IDEX) Store (S48C, DATA) +} diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c new file mode 100644 index 0000000000..9239030d6c --- /dev/null +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation.. + * Copyright (C) 2017 Advanced Micro Devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000 +#error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB" +#endif +#if CONFIG_PI_AGESA_CAR_HEAP_BASE < 0x100000 +#error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB" +#endif + +/* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ +static void amd_initmmio(void) +{ + msr_t mmconf; + msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); + int mtrr; + + mmconf.hi = 0; + mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN + | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; + wrmsr(MMIO_CONF_BASE, mmconf); + + /* + * todo: AGESA currently writes variable MTRRs. Once that is + * corrected, un-hardcode this MTRR. + * + * Be careful not to use get_free_var_mtrr/set_var_mtrr pairs + * where all cores execute the path. Both cores within a compute + * unit share MTRRs. Programming core0 has the appearance of + * modifying core1 too. Using the pair again will create + * duplicate copies. + */ + mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH; + set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_CAR_HEAP; + set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE, + CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK); + + mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_TEMPRAM; + set_var_mtrr(mtrr, CONFIG_PI_AGESA_TEMP_RAM_BASE, + CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE); +} + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + amd_initmmio(); + /* + * Call lib/bootblock.c main with BSP, shortcut for APs + */ + if (!boot_cpu()) { + void (*ap_romstage_entry)(void) = + (void (*)(void))get_ap_entry_ptr(); + + ap_romstage_entry(); /* execution does not return */ + halt(); + } + + /* TSC cannot be relied upon. Override the TSC value passed in. */ + bootblock_main_with_timestamp(timestamp_get(), NULL, 0); +} + +void bootblock_soc_early_init(void) +{ + /* + * This call (sb_reset_i2c_slaves) was originally early at + * bootblock_c_entry, but had to be moved here. There was an + * unexplained delay in the middle of the i2c transaction when + * we had it in bootblock_c_entry. Moving it to this point + * (or adding delays) fixes the issue. It seems like the processor + * just pauses but we don't know why. + */ + sb_reset_i2c_slaves(); + bootblock_fch_early_init(); + post_code(0x90); +} + +void bootblock_soc_init(void) +{ + if (CONFIG(STONEYRIDGE_UART)) + assert(CONFIG_UART_FOR_CONSOLE >= 0 + && CONFIG_UART_FOR_CONSOLE <= 1); + + u32 val = cpuid_eax(1); + printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + + bootblock_fch_init(); + + /* Initialize any early i2c buses. */ + i2c_soc_early_init(); +} diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c new file mode 100644 index 0000000000..7221f955f6 --- /dev/null +++ b/src/soc/amd/picasso/chip.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +/* Supplied by i2c.c */ +extern struct device_operations stoneyridge_i2c_mmio_ops; +extern const char *i2c_acpi_name(const struct device *dev); + +struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = stoney_init_cpus, + .acpi_fill_ssdt_generator = generate_cpu_entries, +}; + +const char *soc_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type == DEVICE_PATH_USB) { + switch (dev->path.usb.port_type) { + case 0: + /* Root Hub */ + return "RHUB"; + case 2: + /* USB2 ports */ + switch (dev->path.usb.port_id) { + case 0: return "HS01"; + case 1: return "HS02"; + case 2: return "HS03"; + case 3: return "HS04"; + case 4: return "HS05"; + case 5: return "HS06"; + case 6: return "HS07"; + case 7: return "HS08"; + } + break; + case 3: + /* USB3 ports */ + switch (dev->path.usb.port_id) { + case 0: return "SS01"; + case 1: return "SS02"; + case 2: return "SS03"; + } + break; + } + return NULL; + } + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case GFX_DEVFN: + return "IGFX"; + case PCIE0_DEVFN: + return "PBR4"; + case PCIE1_DEVFN: + return "PBR5"; + case PCIE2_DEVFN: + return "PBR6"; + case PCIE3_DEVFN: + return "PBR7"; + case PCIE4_DEVFN: + return "PBR8"; + case HDA1_DEVFN: + return "AZHD"; + case EHCI1_DEVFN: + return "EHC0"; + case LPC_DEVFN: + return "LPCB"; + case SATA_DEVFN: + return "STCR"; + case SD_DEVFN: + return "SDCN"; + case SMBUS_DEVFN: + return "SBUS"; + case XHCI_DEVFN: + return "XHC0"; + default: + return NULL; + } +}; + +struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = domain_set_resources, + .enable_resources = domain_enable_resources, + .scan_bus = pci_domain_scan_bus, + .acpi_name = soc_acpi_name, +}; + +static void enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) + dev->ops = &pci_domain_ops; + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + dev->ops = &cpu_bus_ops; + else if (dev->path.type == DEVICE_PATH_PCI) + sb_enable(dev); + else if (dev->path.type == DEVICE_PATH_MMIO) + if (i2c_acpi_name(dev) != NULL) + dev->ops = &stoneyridge_i2c_mmio_ops; +} + +static void soc_init(void *chip_info) +{ + southbridge_init(chip_info); + setup_bsp_ramtop(); +} + +static void soc_final(void *chip_info) +{ + southbridge_final(chip_info); + fam15_finalize(chip_info); +} + +struct chip_operations soc_amd_stoneyridge_ops = { + CHIP_NAME("AMD StoneyRidge SOC") + .enable_dev = enable_dev, + .init = soc_init, + .final = soc_final +}; + +static void earliest_ramstage(void *unused) +{ + int s3_resume = acpi_s3_resume_allowed() && + romstage_handoff_is_resume(); + if (!s3_resume) { + post_code(0x46); + if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) + psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2"); + + post_code(0x47); + do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); + } else { + /* Complete the initial system restoration */ + post_code(0x46); + do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); + } +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, earliest_ramstage, NULL); diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h new file mode 100644 index 0000000000..d1a7d30199 --- /dev/null +++ b/src/soc/amd/picasso/chip.h @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __STONEYRIDGE_CHIP_H__ +#define __STONEYRIDGE_CHIP_H__ + +#include +#include +#include +#include +#include +#include + +#define MAX_NODES 1 +#define MAX_DRAM_CH 1 +#define MAX_DIMMS_PER_CH 2 + +#define STONEY_I2C_DEV_MAX 4 + +struct soc_amd_stoneyridge_config { + u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH]; + enum { + DRAM_CONTENTS_KEEP, + DRAM_CONTENTS_CLEAR + } dram_clear_on_reset; + + enum { + /* Do not enable UMA in the system. */ + UMAMODE_NONE, + /* Enable UMA with a specific size. */ + UMAMODE_SPECIFIED_SIZE, + /* Let AGESA determine the proper size. Non-legacy requires + * the resolution to be specified PLATFORM_CONFIGURATION */ + UMAMODE_AUTO_LEGACY, + UMAMODE_AUTO_NON_LEGACY, + } uma_mode; + + /* Used if UMAMODE_SPECIFIED_SIZE is set. */ + size_t uma_size; + + /* + * If sb_reset_i2c_slaves() is called, this devicetree register + * defines which I2C SCL will be toggled 9 times at 100 KHz. + * For example, should we need I2C0 and I2C3 have their slave + * devices reseted by toggling SCL, use: + * + * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) + */ + u8 i2c_scl_reset; + struct dw_i2c_bus_config i2c[STONEY_I2C_DEV_MAX]; + u8 stapm_percent; + u32 stapm_time_ms; + u32 stapm_power_mw; + /* + * This specifies the LVDS/eDP power-up sequence time for the delay + * between VaryBL and BLON. + * 0 - Use the VBIOS default (default). The video BIOS default is 32ms. + * n - Values other than zero specify a setting of (4 * n) milliseconds + * time delay. + */ + u8 lvds_poseq_varybl_to_blon; + u8 lvds_poseq_blon_to_varybl; +}; + +typedef struct soc_amd_stoneyridge_config config_t; + +extern struct device_operations pci_domain_ops; + +#endif /* __STONEYRIDGE_CHIP_H__ */ diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c new file mode 100644 index 0000000000..1d9804d99c --- /dev/null +++ b/src/soc/amd/picasso/cpu.c @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * MP and SMM loading initialization. + */ +struct smm_relocation_attrs { + uint32_t smbase; + uint32_t tseg_base; + uint32_t tseg_mask; +}; + +static struct smm_relocation_attrs relo_attrs; + +/* + * Do essential initialization tasks before APs can be fired up - + * + * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This + * creates the MTRR solution that the APs will use. Otherwise APs will try to + * apply the incomplete solution as the BSP is calculating it. + */ +static void pre_mp_init(void) +{ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_cpu_count(void) +{ + return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) + + 1; +} + +static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + void *smm_base; + size_t smm_size; + void *handler_base; + size_t handler_size; + + /* Initialize global tracking state. */ + smm_region_info(&smm_base, &smm_size); + smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + + relo_attrs.smbase = (uint32_t)smm_base; + relo_attrs.tseg_base = relo_attrs.smbase; + relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB); + relo_attrs.tseg_mask |= SMM_TSEG_WB; + + *perm_smbase = (uintptr_t)handler_base; + *perm_smsize = handler_size; + *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); +} + +static void relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) +{ + msr_t tseg_base, tseg_mask; + amd64_smm_state_save_area_t *smm_state; + + tseg_base.lo = relo_attrs.tseg_base; + tseg_base.hi = 0; + wrmsr(SMM_ADDR_MSR, tseg_base); + tseg_mask.lo = relo_attrs.tseg_mask; + tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); + wrmsr(SMM_MASK_MSR, tseg_mask); + smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); + smm_state->smbase = staggered_smbase; +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = get_smm_info, + .relocation_handler = relocation_handler, + .post_mp_init = enable_smi_generation, +}; + +void stoney_init_cpus(struct device *dev) +{ + /* Clear for take-off */ + if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + printk(BIOS_ERR, "MP initialization failure.\n"); + + /* The flash is now no longer cacheable. Reset to WP for performance. */ + mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + set_warm_reset_flag(); +} + +static void model_15_init(struct device *dev) +{ + check_mca(); + setup_lapic(); + + /* + * Per AMD, sync an undocumented MSR with the PSP base address. + * Experiments showed that if you write to the MSR after it has + * been previously programmed, it causes a general protection fault. + * Also, the MSR survives warm reset and S3 cycles, so we need to + * test if it was previously written before writing to it. + */ + msr_t psp_msr; + uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */ + psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4); + psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + psp_msr = rdmsr(0xc00110a2); + if (psp_msr.lo == 0) { + psp_msr.lo = psp_bar; + wrmsr(0xc00110a2, psp_msr); + } +} + +static struct device_operations cpu_dev_ops = { + .init = model_15_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x670f00 }, + { 0, 0 }, +}; + +static const struct cpu_driver model_15 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/soc/amd/picasso/enable_usbdebug.c b/src/soc/amd/picasso/enable_usbdebug.c new file mode 100644 index 0000000000..19b9550847 --- /dev/null +++ b/src/soc/amd/picasso/enable_usbdebug.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include + +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + pm_io_write8(PM_USB_ENABLE, PM_USB_ALL_CONTROLLERS); + return SOC_EHCI1_DEV; +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +{ + u32 reg32, value; + + value = (port & 0x3) << DEBUG_PORT_SELECT_SHIFT; + value |= DEBUG_PORT_ENABLE; + reg32 = pci_read_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4); + reg32 &= ~DEBUG_PORT_MASK; + reg32 |= value; + pci_write_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4, reg32); +} diff --git a/src/soc/amd/picasso/finalize.c b/src/soc/amd/picasso/finalize.c new file mode 100644 index 0000000000..6572e1a201 --- /dev/null +++ b/src/soc/amd/picasso/finalize.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +static void per_core_finalize(void *unused) +{ + msr_t hwcr, mask; + + /* Finalize SMM settings */ + hwcr = rdmsr(HWCR_MSR); + if (hwcr.lo & SMM_LOCK) /* Skip if already locked, avoid GPF */ + return; + + if (CONFIG(SMM_TSEG)) { + mask = rdmsr(SMM_MASK_MSR); + mask.lo |= SMM_TSEG_VALID; + wrmsr(SMM_MASK_MSR, mask); + } + + hwcr.lo |= SMM_LOCK; + wrmsr(HWCR_MSR, hwcr); +} + +static void finalize_cores(void) +{ + int r; + printk(BIOS_SPEW, "Lock SMM configuration\n"); + + r = mp_run_on_all_cpus(per_core_finalize, NULL, 10 * USECS_PER_MSEC); + if (r) + printk(BIOS_WARNING, "Failed to finalize all cores\n"); +} + +static void soc_finalize(void *unused) +{ + finalize_cores(); + + post_code(POST_OS_BOOT); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); diff --git a/src/soc/amd/picasso/gpio.c b/src/soc/amd/picasso/gpio.c new file mode 100644 index 0000000000..f63a0d93a4 --- /dev/null +++ b/src/soc/amd/picasso/gpio.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static const struct soc_amd_event gpio_event_table[] = { + { GPIO_1, GEVENT_19 }, + { GPIO_2, GEVENT_8 }, + { GPIO_3, GEVENT_2 }, + { GPIO_4, GEVENT_4 }, + { GPIO_5, GEVENT_7 }, + { GPIO_6, GEVENT_10 }, + { GPIO_7, GEVENT_11 }, + { GPIO_8, GEVENT_23 }, + { GPIO_9, GEVENT_22 }, + { GPIO_11, GEVENT_18 }, + { GPIO_13, GEVENT_21 }, + { GPIO_14, GEVENT_6 }, + { GPIO_15, GEVENT_20 }, + { GPIO_16, GEVENT_12 }, + { GPIO_17, GEVENT_13 }, + { GPIO_18, GEVENT_14 }, + { GPIO_21, GEVENT_5 }, + { GPIO_22, GEVENT_3 }, + { GPIO_23, GEVENT_16 }, + { GPIO_24, GEVENT_15 }, + { GPIO_65, GEVENT_0 }, + { GPIO_66, GEVENT_1 }, + { GPIO_68, GEVENT_9 }, + { GPIO_69, GEVENT_17 }, +}; + +void soc_route_sci(uint8_t event) +{ + smi_write8(SMI_SCI_MAP(event), event); +} + +void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) +{ + *table = gpio_event_table; + *items = ARRAY_SIZE(gpio_event_table); +} + +void soc_gpio_hook(uint8_t gpio, uint8_t mux) +{ + /* Always program Gevent when WAKE_L_AGPIO2 is configured as WAKE_L */ + if ((gpio == 2) && !(mux & AMD_GPIO_MUX_MASK)) + soc_route_sci(GPIO_2_EVENT); +} diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c new file mode 100644 index 0000000000..7f65a4f3f3 --- /dev/null +++ b/src/soc/amd/picasso/i2c.c @@ -0,0 +1,241 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +#define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x)) +#define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0)) +#define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1)) +#define I2CC_BASE_ADDRESS (I2C_BUS_ADDRESS(2)) +#define I2CD_BASE_ADDRESS (I2C_BUS_ADDRESS(3)) + +/* Global to provide access to chip.c */ +const char *i2c_acpi_name(const struct device *dev); + +static const uintptr_t i2c_bus_address[] = { + I2CA_BASE_ADDRESS, + I2CB_BASE_ADDRESS, + I2CC_BASE_ADDRESS, + I2CD_BASE_ADDRESS, +}; + +uintptr_t dw_i2c_base_address(unsigned int bus) +{ + return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0; +} + +static const struct soc_amd_stoneyridge_config *get_soc_config(void) +{ + const struct device *dev = pcidev_path_on_root(GNB_DEVFN); + + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", + __func__); + return NULL; + } + + return dev->chip_info; +} + +const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) +{ + const struct soc_amd_stoneyridge_config *config; + + if (bus >= ARRAY_SIZE(i2c_bus_address)) + return NULL; + + config = get_soc_config(); + if (config == NULL) + return NULL; + + return &config->i2c[bus]; +} + +const char *i2c_acpi_name(const struct device *dev) +{ + switch (dev->path.mmio.addr) { + case I2CA_BASE_ADDRESS: + return "I2CA"; + case I2CB_BASE_ADDRESS: + return "I2CB"; + case I2CC_BASE_ADDRESS: + return "I2CC"; + case I2CD_BASE_ADDRESS: + return "I2CD"; + default: + return NULL; + } +} + +int dw_i2c_soc_dev_to_bus(struct device *dev) +{ + switch (dev->path.mmio.addr) { + case I2CA_BASE_ADDRESS: + return 0; + case I2CB_BASE_ADDRESS: + return 1; + case I2CC_BASE_ADDRESS: + return 2; + case I2CD_BASE_ADDRESS: + return 3; + } + return -1; +} + +static void dw_i2c_soc_init(bool is_early_init) +{ + size_t i; + const struct soc_amd_stoneyridge_config *config; + + config = get_soc_config(); + + if (config == NULL) + return; + + for (i = 0; i < ARRAY_SIZE(config->i2c); i++) { + const struct dw_i2c_bus_config *cfg = &config->i2c[i]; + + if (cfg->early_init != is_early_init) + continue; + + if (dw_i2c_init(i, cfg)) + printk(BIOS_ERR, "Failed to init i2c bus %zd\n", i); + } +} + +void i2c_soc_early_init(void) +{ + dw_i2c_soc_init(true); +} + +void i2c_soc_init(void) +{ + dw_i2c_soc_init(false); +} + +struct device_operations stoneyridge_i2c_mmio_ops = { + /* TODO(teravest): Move I2C resource info here. */ + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .scan_bus = scan_smbus, + .acpi_name = i2c_acpi_name, + .acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt, +}; + +/* + * I2C pins are open drain with external pull up, so in order to bit bang them + * all, SCL pins must become GPIO inputs with no pull, then they need to be + * toggled between input-no-pull and output-low. This table is for the initial + * conversion of all SCL pins to input with no pull. + */ +static const struct soc_amd_gpio i2c_2_gpi[] = { + PAD_GPI(I2C0_SCL_PIN, PULL_NONE), + PAD_GPI(I2C1_SCL_PIN, PULL_NONE), + PAD_GPI(I2C2_SCL_PIN, PULL_NONE), + PAD_GPI(I2C3_SCL_PIN, PULL_NONE), +}; +#define saved_pins_count ARRAY_SIZE(i2c_2_gpi) + +/* + * To program I2C pins without destroying their programming, the registers + * that will be changed need to be saved first. + */ +static void save_i2c_pin_registers(uint8_t gpio, + struct soc_amd_i2c_save *save_table) +{ + uint32_t *gpio_ptr; + + gpio_ptr = (uint32_t *)gpio_get_address(gpio); + save_table->mux_value = iomux_read8(gpio); + save_table->control_value = read32(gpio_ptr); +} + +static void restore_i2c_pin_registers(uint8_t gpio, + struct soc_amd_i2c_save *save_table) +{ + uint32_t *gpio_ptr; + + gpio_ptr = (uint32_t *)gpio_get_address(gpio); + iomux_write8(gpio, save_table->mux_value); + iomux_read8(gpio); + write32(gpio_ptr, save_table->control_value); + read32(gpio_ptr); +} + +/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ +void sb_reset_i2c_slaves(void) +{ + const struct soc_amd_stoneyridge_config *cfg; + const struct device *dev = pcidev_path_on_root(GNB_DEVFN); + struct soc_amd_i2c_save save_table[saved_pins_count]; + uint8_t i, j, control; + + if (!dev || !dev->chip_info) + return; + cfg = dev->chip_info; + control = cfg->i2c_scl_reset & GPIO_I2C_MASK; + if (control == 0) + return; + + /* Save and reprogram I2C SCL pins */ + for (i = 0; i < saved_pins_count; i++) + save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); + program_gpios(i2c_2_gpi, saved_pins_count); + + /* + * Toggle SCL back and forth 9 times under 100KHz. A single read is + * needed after the writes to force the posted write to complete. + */ + for (j = 0; j < 9; j++) { + if (control & GPIO_I2C0_SCL) + write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_LOW); + if (control & GPIO_I2C1_SCL) + write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_LOW); + if (control & GPIO_I2C2_SCL) + write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); + if (control & GPIO_I2C3_SCL) + write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW); + + read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */ + + if (control & GPIO_I2C0_SCL) + write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_HIGH); + if (control & GPIO_I2C1_SCL) + write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_HIGH); + if (control & GPIO_I2C2_SCL) + write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); + if (control & GPIO_I2C3_SCL) + write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH); + + read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + udelay(4); + } + + /* Restore I2C pins. */ + for (i = 0; i < saved_pins_count; i++) + restore_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); +} diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h new file mode 100644 index 0000000000..15a41edce6 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_STONEYRIDGE_ACPI_H__ +#define __SOC_STONEYRIDGE_ACPI_H__ + +#include + +#if CONFIG(STONEYRIDGE_LEGACY_FREE) + #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE +#else + #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) +#endif + +#ifndef FADT_PM_PROFILE + #define FADT_PM_PROFILE PM_UNSPECIFIED +#endif + +unsigned long southbridge_write_acpi_tables(struct device *device, + unsigned long current, struct acpi_rsdp *rsdp); + +void southbridge_inject_dsdt(struct device *device); + +const char *soc_acpi_name(const struct device *dev); + +#endif /* __SOC_STONEYRIDGE_ACPI_H__ */ diff --git a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h new file mode 100644 index 0000000000..beef2bcc81 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMD_PCI_INT_DEFS_H__ +#define __AMD_PCI_INT_DEFS_H__ + +/* + * PIRQ and device routing - these define the index into the + * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. + */ + +#define PIRQ_NC 0x1f /* Not Used */ +#define PIRQ_A 0x00 /* INT A */ +#define PIRQ_B 0x01 /* INT B */ +#define PIRQ_C 0x02 /* INT C */ +#define PIRQ_D 0x03 /* INT D */ +#define PIRQ_E 0x04 /* INT E */ +#define PIRQ_F 0x05 /* INT F */ +#define PIRQ_G 0x06 /* INT G */ +#define PIRQ_H 0x07 /* INT H */ +#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ +#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ +#define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */ +#define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */ +#define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0d /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */ +#define PIRQ_SCI 0x10 /* SCI IRQ */ +#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ +#define PIRQ_ASF 0x12 /* ASF */ +#define PIRQ_HDA 0x13 /* HDA 14h.2 */ +#define PIRQ_FC 0x14 /* FC */ +#define PIRQ_PMON 0x16 /* Performance Monitor */ +#define PIRQ_SD 0x17 /* SD */ +#define PIRQ_SDIO 0x1a /* SDIO */ +#define PIRQ_EHCI 0x30 /* USB EHCI 12h.0 */ +#define PIRQ_XHCI 0x34 /* USB XHCI 10h.0 */ +#define PIRQ_SATA 0x41 /* SATA 11h.0 */ +#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ +#define PIRQ_I2C0 0x70 +#define PIRQ_I2C1 0x71 +#define PIRQ_I2C2 0x72 +#define PIRQ_I2C3 0x73 +#define PIRQ_UART0 0x74 +#define PIRQ_UART1 0x75 + +#endif /* __AMD_PCI_INT_DEFS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h new file mode 100644 index 0000000000..934a9f2983 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __STONEYRIDGE_CPU_H__ +#define __STONEYRIDGE_CPU_H__ + +#include + +/* + * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest + * numbered registers. Any values defined below are subtracted from the + * highest numbered registers. + * + * todo: Revisit this once AGESA no longer programs MTRRs. + */ +#define SOC_EARLY_VMTRR_FLASH 1 +#define SOC_EARLY_VMTRR_CAR_HEAP 2 +#define SOC_EARLY_VMTRR_TEMPRAM 3 + +void stoney_init_cpus(struct device *dev); +void check_mca(void); + +#endif /* __STONEYRIDGE_CPU_H__ */ diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h new file mode 100644 index 0000000000..d8774f051a --- /dev/null +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -0,0 +1,308 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __STONEYRIDGE_GPIO_H__ +#define __STONEYRIDGE_GPIO_H__ + +#define GPIO_DEVICE_NAME "AMD0030" +#define GPIO_DEVICE_DESC "GPIO Controller" + +#ifndef __ACPI__ +#include +#include + +/* The following sections describe only the GPIOs defined for this SOC */ + +#define SOC_GPIO_TOTAL_PINS 149 + +/* Bank 0: GPIO_0 - GPIO_62 */ +#define GPIO_0 0 +#define GPIO_1 1 +#define GPIO_2 2 +#define GPIO_3 3 +#define GPIO_4 4 +#define GPIO_5 5 +#define GPIO_6 6 +#define GPIO_7 7 +#define GPIO_8 8 +#define GPIO_9 9 +#define GPIO_10 10 +#define GPIO_11 11 +#define GPIO_12 12 +#define GPIO_13 13 +#define GPIO_14 14 +#define GPIO_15 15 +#define GPIO_16 16 +#define GPIO_17 17 +#define GPIO_18 18 +#define GPIO_19 19 +#define GPIO_20 20 +#define GPIO_21 21 +#define GPIO_22 22 +#define GPIO_23 23 +#define GPIO_24 24 +#define GPIO_25 25 +#define GPIO_26 26 +#define GPIO_39 39 +#define GPIO_40 40 +#define GPIO_42 42 + +/* Bank 1: GPIO_64 - GPIO_127 */ +#define GPIO_64 64 +#define GPIO_65 65 +#define GPIO_66 66 +#define GPIO_67 67 +#define GPIO_68 68 +#define GPIO_69 69 +#define GPIO_70 70 +#define GPIO_71 71 +#define GPIO_72 72 +#define GPIO_74 74 +#define GPIO_75 75 +#define GPIO_76 76 +#define GPIO_84 84 +#define GPIO_85 85 +#define GPIO_86 86 +#define GPIO_87 87 +#define GPIO_88 88 +#define GPIO_89 89 +#define GPIO_90 90 +#define GPIO_91 91 +#define GPIO_92 92 +#define GPIO_93 93 +#define GPIO_95 95 +#define GPIO_96 96 +#define GPIO_97 97 +#define GPIO_98 98 +#define GPIO_99 99 +#define GPIO_100 100 +#define GPIO_101 101 +#define GPIO_102 102 +#define GPIO_113 113 +#define GPIO_114 114 +#define GPIO_115 115 +#define GPIO_116 116 +#define GPIO_117 117 +#define GPIO_118 118 +#define GPIO_119 119 +#define GPIO_120 120 +#define GPIO_121 121 +#define GPIO_122 122 +#define GPIO_126 126 + +/* Bank 2: GPIO_128 - GPIO_183 */ +#define GPIO_129 129 +#define GPIO_130 130 +#define GPIO_131 131 +#define GPIO_132 132 +#define GPIO_133 133 +#define GPIO_134 134 +#define GPIO_135 135 +#define GPIO_136 136 +#define GPIO_137 137 +#define GPIO_138 138 +#define GPIO_139 139 +#define GPIO_140 140 +#define GPIO_141 141 +#define GPIO_142 142 +#define GPIO_143 143 +#define GPIO_144 144 +#define GPIO_145 145 +#define GPIO_146 146 +#define GPIO_147 147 +#define GPIO_148 148 + +#define GPIO_SCL_HIGH 0 +#define GPIO_SCL_LOW GPIO_OUTPUT_ENABLE + +/* IOMUX function names and values generated from BKDG. */ +#define GPIO_0_IOMUX_PWR_BTN_L 0 +#define GPIO_0_IOMUX_GPIOxx 1 +#define GPIO_1_IOMUX_SYS_RESET_L 0 +#define GPIO_1_IOMUX_GPIOxx 1 +#define GPIO_2_IOMUX_WAKE_L 0 +#define GPIO_2_IOMUX_GPIOxx 1 +#define GPIO_3_IOMUX_GPIOxx 0 +#define GPIO_4_IOMUX_GPIOxx 0 +#define GPIO_5_IOMUX_GPIOxx 0 +#define GPIO_5_IOMUX_DEVSLP0_S5 1 +#define GPIO_6_IOMUX_GPIOxx 0 +#define GPIO_6_IOMUX_LDT_RST_L 1 +#define GPIO_7_IOMUX_GPIOxx 0 +#define GPIO_7_IOMUX_LDT_PWROK 1 +#define GPIO_8_IOMUX_GPIOxx 0 +#define GPIO_8_IOMUX_SerPortTX_OUT 1 +#define GPIO_9_IOMUX_GPIOxx 0 +#define GPIO_9_IOMUX_SerPortRX_OUT 1 +#define GPIO_10_IOMUX_S0A3_GPIO 0 +#define GPIO_10_IOMUX_GPIOxx 1 +#define GPIO_11_IOMUX_GPIOxx 0 +#define GPIO_11_IOMUX_USB_OC7_L 1 +#define GPIO_12_IOMUX_IR_LED_L 0 +#define GPIO_12_IOMUX_LLB_L 1 +#define GPIO_12_IOMUX_GPIOxx 2 +#define GPIO_13_IOMUX_USB_OC5_L 0 +#define GPIO_13_IOMUX_GPIOxx 1 +#define GPIO_14_IOMUX_USB_OC6_L 0 +#define GPIO_14_IOMUX_GPIOxx 1 +#define GPIO_15_IOMUX_IR_RX1 0 +#define GPIO_15_IOMUX_GPIOxx 1 +#define GPIO_16_IOMUX_USB_OC0_L 0 +#define GPIO_16_IOMUX_TRST_L 1 +#define GPIO_16_IOMUX_GPIOxx 2 +#define GPIO_17_IOMUX_USB_OC1_L 0 +#define GPIO_17_IOMUX_TDI 1 +#define GPIO_17_IOMUX_GPIOxx 2 +#define GPIO_18_IOMUX_USB_OC2_L 0 +#define GPIO_18_IOMUX_TCK 1 +#define GPIO_18_IOMUX_GPIOxx 2 +#define GPIO_19_IOMUX_SCL1 0 +#define GPIO_19_IOMUX_I2C3_SCL 1 +#define GPIO_19_IOMUX_GPIOxx 2 +#define GPIO_20_IOMUX_SDA1 0 +#define GPIO_20_IOMUX_I2C3_SDA 1 +#define GPIO_20_IOMUX_GPIOxx 2 +#define GPIO_21_IOMUX_LPC_PD_L 0 +#define GPIO_21_IOMUX_GPIOxx 1 +#define GPIO_22_IOMUX_LPC_PME_L 0 +#define GPIO_22_IOMUX_GPIOxx 1 +#define GPIO_23_IOMUX_USB_OC4_L 0 +#define GPIO_23_IOMUX_IR_RX0 1 +#define GPIO_23_IOMUX_GPIOxx 2 +#define GPIO_24_IOMUX_USB_OC3_L 0 +#define GPIO_24_IOMUX_GPIOxx 1 +#define GPIO_25_IOMUX_SD0_CD 0 +#define GPIO_25_IOMUX_GPIOxx 1 +#define GPIO_26_IOMUX_PCIE_RST_L 0 +#define GPIO_26_IOMUX_GPIOxx 1 +#define GPIO_39_IOMUX_VDDGFX_PD 0 +#define GPIO_39_IOMUX_GPIOxx 1 +#define GPIO_40_IOMUX_GPIOxx 0 +#define GPIO_42_IOMUX_S5_MUX_CTRL 0 +#define GPIO_42_IOMUX_GPIOxx 1 +#define GPIO_64_IOMUX_GPIOxx 0 +#define GPIO_65_IOMUX_GPIOxx 0 +#define GPIO_66_IOMUX_GPIOxx 0 +#define GPIO_67_IOMUX_GPIOxx 0 +#define GPIO_67_IOMUX_DEVSLP0 1 +#define GPIO_69_IOMUX_GPIOxx 0 +#define GPIO_69_IOMUX_SGPIO_LOAD 1 +#define GPIO_70_IOMUX_GPIOxx 0 +#define GPIO_70_IOMUX_DEVSLP1 1 +#define GPIO_74_IOMUX_LPCCLK0 0 +#define GPIO_74_IOMUX_GPIOxx 1 +#define GPIO_75_IOMUX_LPCCLK1 0 +#define GPIO_75_IOMUX_GPIOxx 1 +#define GPIO_76_IOMUX_GPIOxx 0 +#define GPIO_76_IOMUX_SPI_TPM_CS_L 1 +#define GPIO_84_IOMUX_FANIN0 0 +#define GPIO_84_IOMUX_GPIOxx 1 +#define GPIO_85_IOMUX_FANOUT0 0 +#define GPIO_85_IOMUX_GPIOxx 1 +#define GPIO_86_IOMUX_GPIOxx 1 +#define GPIO_87_IOMUX_SERIRQ 0 +#define GPIO_87_IOMUX_GPIOxx 1 +#define GPIO_88_IOMUX_LPC_CLKRUN_L 0 +#define GPIO_88_IOMUX_GPIOxx 1 +#define GPIO_90_IOMUX_GPIOxx 0 +#define GPIO_91_IOMUX_SPKR 0 +#define GPIO_91_IOMUX_GPIOxx 1 +#define GPIO_92_IOMUX_CLK_REQ0_L 0 +#define GPIO_92_IOMUX_SATA_IS0_L 1 +#define GPIO_92_IOMUX_SATA_ZP0_L 2 +#define GPIO_92_IOMUX_GPIOxx 3 +#define GPIO_93_IOMUX_SD0_LED 0 +#define GPIO_93_IOMUX_GPIOxx 1 +#define GPIO_95_IOMUX_GPIOxx 0 +#define GPIO_96_IOMUX_GPIOxx 0 +#define GPIO_97_IOMUX_GPIOxx 0 +#define GPIO_98_IOMUX_GPIOxx 0 +#define GPIO_99_IOMUX_GPIOxx 0 +#define GPIO_100_IOMUX_GPIOxx 0 +#define GPIO_101_IOMUX_SD0_WP 0 +#define GPIO_101_IOMUX_GPIOxx 1 +#define GPIO_102_IOMUX_SD0_PWR_CTRL 0 +#define GPIO_102_IOMUX_GPIOxx 1 +#define GPIO_113_IOMUX_SCL0 0 +#define GPIO_113_IOMUX_I2C2_SCL 1 +#define GPIO_113_IOMUX_GPIOxx 2 +#define GPIO_114_IOMUX_SDA0 0 +#define GPIO_114_IOMUX_I2C2_SDA 1 +#define GPIO_114_IOMUX_GPIOxx 2 +#define GPIO_115_IOMUX_CLK_REQ1_L 0 +#define GPIO_115_IOMUX_GPIOxx 1 +#define GPIO_116_IOMUX_CLK_REQ2_L 0 +#define GPIO_116_IOMUX_GPIOxx 1 +#define GPIO_117_IOMUX_ESPI_CLK 0 +#define GPIO_117_IOMUX_GPIOxx 1 +#define GPIO_118_IOMUX_SPI_CS1_L 0 +#define GPIO_118_IOMUX_GPIOxx 1 +#define GPIO_119_IOMUX_SPI_CS2_L 0 +#define GPIO_119_IOMUX_ESPI_CS_L 1 +#define GPIO_119_IOMUX_GPIOxx 2 +#define GPIO_120_IOMUX_ESPI_DAT1 0 +#define GPIO_120_IOMUX_GPIOxx 1 +#define GPIO_121_IOMUX_ESPI_DAT0 0 +#define GPIO_121_IOMUX_GPIOxx 1 +#define GPIO_122_IOMUX_ESPI_DAT2 0 +#define GPIO_122_IOMUX_GPIOxx 1 +#define GPIO_126_IOMUX_GA20IN 0 +#define GPIO_126_IOMUX_GPIOxx 1 +#define GPIO_129_IOMUX_KBRST_L 0 +#define GPIO_129_IOMUX_GPIOxx 1 +#define GPIO_130_IOMUX_SATA_ACT_L 0 +#define GPIO_130_IOMUX_GPIOxx 1 +#define GPIO_131_IOMUX_CLK_REQ3_L 0 +#define GPIO_131_IOMUX_SATA_IS1_L 1 +#define GPIO_131_IOMUX_SATA_ZP1_L 2 +#define GPIO_131_IOMUX_GPIOxx 3 +#define GPIO_132_IOMUX_CLK_REQG_L 0 +#define GPIO_132_IOMUX_OSCIN 1 +#define GPIO_132_IOMUX_GPIOxx 2 +#define GPIO_133_IOMUX_ESPI_DAT3 0 +#define GPIO_133_IOMUX_GPIOxx 1 +#define GPIO_135_IOMUX_UART0_CTS_L 0 +#define GPIO_135_IOMUX_GPIOxx 1 +#define GPIO_136_IOMUX_UART0_RXD 0 +#define GPIO_136_IOMUX_GPIOxx 1 +#define GPIO_137_IOMUX_UART0_RTS_L 0 +#define GPIO_137_IOMUX_GPIOxx 1 +#define GPIO_138_IOMUX_UART0_TXD 0 +#define GPIO_138_IOMUX_GPIOxx 1 +#define GPIO_139_IOMUX_UART0_INTR 0 +#define GPIO_139_IOMUX_GPIOxx 1 +#define GPIO_140_IOMUX_UART1_CTS_L 0 +#define GPIO_140_IOMUX_GPIOxx 1 +#define GPIO_141_IOMUX_UART1_RXD 0 +#define GPIO_141_IOMUX_GPIOxx 1 +#define GPIO_142_IOMUX_UART1_RTS_L 0 +#define GPIO_142_IOMUX_GPIOxx 1 +#define GPIO_143_IOMUX_UART1_TXD 0 +#define GPIO_143_IOMUX_GPIOxx 1 +#define GPIO_144_IOMUX_UART1_INTR 0 +#define GPIO_144_IOMUX_GPIOxx 1 +#define GPIO_145_IOMUX_I2C0_SCL 0 +#define GPIO_145_IOMUX_GPIOxx 1 +#define GPIO_146_IOMUX_I2C0_SDA 0 +#define GPIO_146_IOMUX_GPIOxx 1 +#define GPIO_147_IOMUX_I2C1_SCL 0 +#define GPIO_147_IOMUX_GPIOxx 1 +#define GPIO_148_IOMUX_I2C1_SDA 0 +#define GPIO_148_IOMUX_GPIOxx 1 + +#define GPIO_2_EVENT GEVENT_8 + +#endif /* __ACPI__ */ +#endif /* __STONEYRIDGE_GPIO_H__ */ diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h new file mode 100644 index 0000000000..62575d0fb8 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __STONEYRIDGE_I2C_H__ +#define __STONEYRIDGE_I2C_H__ + +#include + +struct soc_amd_i2c_save { + uint32_t control_value; + uint8_t mux_value; +}; + +#define GPIO_I2C0_SCL BIT(0) +#define GPIO_I2C1_SCL BIT(1) +#define GPIO_I2C2_SCL BIT(2) +#define GPIO_I2C3_SCL BIT(3) +#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + +#define I2C0_SCL_PIN GPIO_145 +#define I2C1_SCL_PIN GPIO_147 +#define I2C2_SCL_PIN GPIO_113 +#define I2C3_SCL_PIN GPIO_19 + +#define GPIO_I2C0_ADDRESS GPIO_BANK2_CONTROL(I2C0_SCL_PIN) +#define GPIO_I2C1_ADDRESS GPIO_BANK2_CONTROL(I2C1_SCL_PIN) +#define GPIO_I2C2_ADDRESS GPIO_BANK1_CONTROL(I2C2_SCL_PIN) +#define GPIO_I2C3_ADDRESS GPIO_BANK0_CONTROL(I2C3_SCL_PIN) + +#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx +#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx +#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx +#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx + +void sb_reset_i2c_slaves(void); + +#endif /* __STONEYRIDGE_I2C_H__ */ diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h new file mode 100644 index 0000000000..612b6e871b --- /dev/null +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Raptor Engineering, LLC + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_STONEYRIDGE_IOMAP_H__ +#define __SOC_STONEYRIDGE_IOMAP_H__ + +/* MMIO Ranges */ +#define PSP_MAILBOX_BAR3_BASE 0xf0a00000 +#define SPI_BASE_ADDRESS 0xfec10000 +#define IO_APIC2_ADDR 0xfec20000 + +/* + * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1]. + * All ranges not specified as supported below may, or may not, be listed in + * any documentation but should be considered reserved through FED8_1FFFh. + */ +#include +#define SUPPORTS_ACPIMMIO_SMI_BASE 1 /* 0xfed80100 */ +#define SUPPORTS_ACPIMMIO_PMIO_BASE 1 /* 0xfed80300 */ +#define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 1 /* 0xfed80500 */ +#define SUPPORTS_ACPIMMIO_ACPI_BASE 1 /* 0xfed80800 */ +#define SUPPORTS_ACPIMMIO_ASF_BASE 1 /* 0xfed80900 */ +#define SUPPORTS_ACPIMMIO_SMBUS_BASE 1 /* 0xfed80a00 */ +#define SUPPORTS_ACPIMMIO_IOMUX_BASE 1 /* 0xfed80d00 */ +#define SUPPORTS_ACPIMMIO_MISC_BASE 1 /* 0xfed80e00 */ +#define SUPPORTS_ACPIMMIO_GPIO0_BASE 1 /* 0xfed81500 */ +#define SUPPORTS_ACPIMMIO_GPIO1_BASE 1 /* 0xfed81800 */ +#define SUPPORTS_ACPIMMIO_GPIO2_BASE 1 /* 0xfed81700 */ +#define SUPPORTS_ACPIMMIO_XHCIPM_BASE 1 /* 0xfed81c00 */ +#define SUPPORTS_ACPIMMIO_AOAC_BASE 1 /* 0xfed81e00 */ + +#define ALINK_AHB_ADDRESS 0xfedc0000 + +/* I2C fixed address */ +#define I2C_BASE_ADDRESS 0xfedc2000 +#define I2C_DEVICE_SIZE 0x00001000 +#define I2C_DEVICE_COUNT 4 + +#if CONFIG(HPET_ADDRESS_OVERRIDE) +#error HPET address override is not allowed and must be fixed at 0xfed00000 +#endif +#define HPET_BASE_ADDRESS 0xfed00000 + +#define APU_UART0_BASE 0xfedc6000 +#define APU_UART1_BASE 0xfedc8000 + +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + +/* I/O Ranges */ +#define ACPI_SMI_CTL_PORT 0xb2 +#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE +#define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */ +#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ +#define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */ +#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */ +#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ +#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ +#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define SMB_BASE_ADDR 0xb00 +#define PM2_INDEX 0xcd0 +#define PM2_DATA 0xcd1 +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 +#define AB_INDX 0xcd8 +#define AB_DATA (AB_INDX+4) +#define SYS_RESET 0xcf9 + +/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ +#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ +#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ + +#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */ diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h new file mode 100644 index 0000000000..60a6ea22bb --- /dev/null +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__ +#define __PI_STONEYRIDGE_NORTHBRIDGE_H__ + +#include +#include + +/* D0F0 - Root Complex */ + +/* NB IOAPIC registers */ +#define NB_IOAPIC_INDEX 0xf8 +#define NB_IOAPIC_DATA 0xfc +#define NB_IOAPIC_FEATURE_CTRL 0x00 +#define NB_IOAPIC_ADDRESS_LOW 0x01 +#define NB_IOAPIC_ADDRESS_HIGH 0x02 +#define NB_IOAPIC_GBIF_IRR 0x0f +#define NB_IOAPIC_BR0_IRR 0x10 +#define NB_IOAPIC_BR1_IRR 0x11 +#define NB_IOAPIC_BR2_IRR 0x12 +#define NB_IOAPIC_BR3_IRR 0x13 +#define NB_IOAPIC_BR4_IRR 0x14 +#define NB_IOAPIC_APG_IRR 0x2f +#define NB_IOAPIC_SPG_IRR 0x30 +#define NB_IOAPIC_SER_IRQ_IRR 0x31 +#define NB_IOAPIC_SCRATCH0 0x3e +#define NB_IOAPIC_SCRATCH1 0x3f + +#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0 + +/* D1F1 - HDA Configuration Registers */ +#define HDA_DEV_CTRL_STATUS 0x60 +#define HDA_NO_SNOOP_EN BIT(11) + +/* D18F0 - HT Configuration Registers */ +#define D18F0_NODE_ID 0x60 +#define D18F0_CPU_CNT 0x62 /* BKDG defines as a field in DWORD 0x60 */ +# define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */ +#define HT_INIT_CONTROL 0x6c +# define HTIC_BIOSR_DETECT ((1 << 5) | (1 << 9) | (1 << 10)) +# define HTIC_COLD_RST_DET BIT(4) + +/* D18F1 - Address Map Registers */ + +/* MMIO base and limit */ +#define D18F1_MMIO_BASE0_LO 0x80 +# define MMIO_WE (1 << 1) +# define MMIO_RE (1 << 0) +#define D18F1_MMIO_LIMIT0_LO 0x84 +# define MMIO_NP (1 << 7) +#define D18F1_IO_BASE0_LO 0xc0 +#define D18F1_IO_BASE1_LO 0xc8 +#define D18F1_IO_BASE2_LO 0xd0 +#define D18F1_IO_BASE3_LO 0xd8 +#define D18F1_MMIO_BASE7_LO 0xb8 +#define D18F1_MMIO_BASELIM0_HI 0x180 +#define D18F1_MMIO_BASE8_LO 0x1a0 +#define D18F1_MMIO_LIMIT8_LO 0x1a4 +#define D18F1_MMIO_BASE11_LO 0x1b8 +#define D18F1_MMIO_BASELIM8_HI 0x1c0 +#define NB_MMIO_BASE_LO(reg) ((reg) * 2 * sizeof(uint32_t) + (((reg) < 8) \ + ? D18F1_MMIO_BASE0_LO \ + : D18F1_MMIO_BASE8_LO \ + - 8 * sizeof(uint64_t))) +#define NB_MMIO_LIMIT_LO(reg) (NB_MMIO_BASE_LO(reg) + sizeof(uint32_t)) +#define NB_MMIO_BASELIM_HI(reg) ((reg) * sizeof(uint32_t) + (((reg) < 8) \ + ? D18F1_MMIO_BASELIM0_HI \ + : D18F1_MMIO_BASELIM8_HI \ + - 8 * sizeof(uint32_t))) +/* I/O base and limit */ +#define D18F1_IO_BASE0 0xc0 +# define IO_WE (1 << 1) +# define IO_RE (1 << 0) +#define D18F1_IO_LIMIT0 0xc4 +#define NB_IO_BASE(reg) ((reg) * 2 * sizeof(uint32_t) + D18F1_IO_BASE0) +#define NB_IO_LIMIT(reg) (NB_IO_BASE(reg) + sizeof(uint32_t)) + +#define D18F1_DRAM_HOLE 0xf0 +# define DRAM_HOIST_VALID (1 << 1) +# define DRAM_HOLE_VALID (1 << 0) +#define D18F1_VGAEN 0xf4 +# define VGA_ADDR_ENABLE (1 << 0) + +/* D18F5 */ +#define NB_CAPABILITIES2 0x84 +#define CMP_CAP_MASK 0xff + +enum { + /* SMM handler area. */ + SMM_SUBREGION_HANDLER, + /* SMM cache region. */ + SMM_SUBREGION_CACHE, + /* Chipset specific area. */ + SMM_SUBREGION_CHIPSET, + /* Total sub regions supported. */ + SMM_SUBREGION_NUM, +}; + +/* + * Fills in the arguments for the entire SMM region covered by chipset + * protections. e.g. TSEG. + */ +void smm_region_info(void **start, size_t *size); +/* + * Fills in the start and size for the requested SMM subregion. Returns + * 0 on success, < 0 on failure. + */ +int smm_subregion(int sub, void **start, size_t *size); +void domain_enable_resources(struct device *dev); +void domain_set_resources(struct device *dev); +void fam15_finalize(void *chip_info); +uint32_t nb_ioapic_read(unsigned int index); +void nb_ioapic_write(unsigned int index, uint32_t value); +void *get_ap_entry_ptr(void); +void set_ap_entry_ptr(void *entry); +void set_warm_reset_flag(void); +int is_warm_reset(void); + +#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */ diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h new file mode 100644 index 0000000000..08d46973c0 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * NOTE: The layout of the global_nvs_t structure below must match the layout + * in soc/soc/amd/stoneyridge/acpi/globalnvs.asl !!! + * + */ + +#ifndef __SOC_STONEYRIDGE_NVS_H__ +#define __SOC_STONEYRIDGE_NVS_H__ + +#include +#include +#include +#include + +typedef struct global_nvs_t { + /* Miscellaneous */ + uint8_t pcnt; /* 0x00 - Processor Count */ + uint8_t ppcm; /* 0x01 - Max PPC State */ + uint8_t lids; /* 0x02 - LID State */ + uint8_t pwrs; /* 0x03 - AC Power State */ + uint8_t dpte; /* 0x04 - Enable DPTF */ + uint32_t cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ + uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */ + uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */ + uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */ + uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */ + uint8_t scdp; /* 0x29 - SD_CD GPIO portid */ + uint8_t scdo; /* 0x2A - GPIO pad relative offset */ + uint8_t tmps; /* 0x2B - Temperature Sensor ID */ + uint8_t tlvl; /* 0x2C - Throttle Level Limit */ + uint8_t flvl; /* 0x2D - Current FAN Level */ + uint8_t tcrt; /* 0x2E - Critical Threshold */ + uint8_t tpsv; /* 0x2F - Passive Threshold */ + uint8_t tmax; /* 0x30 - CPU Tj_max */ + uint8_t pad1[3]; + aoac_devs_t aoac; /* 0x34 - AOAC device enables */ + uint16_t fw00; /* 0x38 - XhciFwRomAddr_Rom, Boot RAM */ + uint16_t fw02; /* 0x3A - XhciFwRomAddr_Ram, Instr RAM */ + uint32_t fw01; /* 0x3C - XhciFwRamAddr_Rom, Boot RAM sz/base */ + uint32_t fw03; /* 0x40 - XhciFwRomAddr_Ram, Instr RAM sz/base */ + uint32_t eh10; /* 0x40 - EHCI BAR */ + uint8_t unused[184]; + + /* ChromeOS specific (0x100 - 0xfff) */ + chromeos_acpi_t chromeos; +} __packed global_nvs_t; +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); + +#endif /* __SOC_STONEYRIDGE_NVS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h new file mode 100644 index 0000000000..02fed7ab1e --- /dev/null +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -0,0 +1,198 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__ +#define __PI_STONEYRIDGE_PCI_DEVS_H__ + +#include + +#if !defined(__SIMPLE_DEVICE__) +#include +#define _SOC_DEV(slot, func) pcidev_on_root(slot, func) +#else +#define _SOC_DEV(slot, func) PCI_DEV(0, slot, func) +#endif + +/* GNB Root Complex */ +#define GNB_DEV 0x0 +#define GNB_FUNC 0 +#define GNB_DEVID 0x1576 +#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) +#define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC) + +/* IOMMU */ +#define IOMMU_DEV 0x0 +#define IOMMU_FUNC 2 +#define IOMMU_DEVID 0x1577 +#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) +#define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC) + +/* Internal Graphics */ +#define GFX_DEV 0x1 +#define GFX_FUNC 0 +#define GFX_DEVID 0x98e4 /* subject to SKU/OPN variation */ +#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) +#define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC) + +/* HD Audio 0 */ +#define HDA0_DEV 0x1 +#define HDA0_FUNC 1 +#define HDA0_DEVID 0x15b3 +#define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC) +#define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC) + +/* Host Bridge */ +#define HOST_DEV 0x2 +#define HOST_FUNC 0 +#define HOST_DEVID 0x157b +#define HOST_DEVFN PCI_DEVFN(HOST_DEV, HOST_FUNC) +#define SOC_HOST_DEV _SOC_DEV(HOST_DEV, HOST_FUNC) + +/* PCIe GPP Bridge 0 */ +#define PCIE0_DEV 0x2 +#define PCIE0_FUNC 1 +#define PCIE0_DEVID 0x157c +#define PCIE0_DEVFN PCI_DEVFN(PCIE0_DEV, PCIE0_FUNC) +#define SOC_PCIE0_DEV _SOC_DEV(PCIE0_DEV, PCIE0_FUNC) + +/* PCIe GPP Bridge 1 */ +#define PCIE1_DEV 0x2 +#define PCIE1_FUNC 2 +#define PCIE1_DEVID 0x157c +#define PCIE1_DEVFN PCI_DEVFN(PCIE1_DEV, PCIE1_FUNC) +#define SOC_PCIE1_DEV _SOC_DEV(PCIE1_DEV, PCIE1_FUNC) + +/* PCIe GPP Bridge 2 */ +#define PCIE2_DEV 0x2 +#define PCIE2_FUNC 3 +#define PCIE2_DEVID 0x157c +#define PCIE2_DEVFN PCI_DEVFN(PCIE2_DEV, PCIE2_FUNC) +#define SOC_PCIE2_DEV _SOC_DEV(PCIE2_DEV, PCIE2_FUNC) + +/* PCIe GPP Bridge 3 */ +#define PCIE3_DEV 0x2 +#define PCIE3_FUNC 4 +#define PCIE3_DEVID 0x157c +#define PCIE3_DEVFN PCI_DEVFN(PCIE3_DEV, PCIE3_FUNC) +#define SOC_PCIE3_DEV _SOC_DEV(PCIE3_DEV, PCIE3_FUNC) + +/* PCIe GPP Bridge 4 */ +#define PCIE4_DEV 0x2 +#define PCIE4_FUNC 5 +#define PCIE4_DEVID 0x157c +#define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC) +#define SOC_PCIE4_DEV _SOC_DEV(PCIE4_DEV, PCIE4_FUNC) + +/* Platform Security Processor */ +#define PSP_DEV 0x8 +#define PSP_FUNC 0 +#define PSP_DEVID 0x1578 +#define PSP_DEVFN PCI_DEVFN(PSP_DEV, PSP_FUNC) +#define SOC_PSP_DEV _SOC_DEV(PSP_DEV, PSP_FUNC) + +/* HD Audio 1 */ +#define HDA1_DEV 0x9 +#define HDA1_FUNC 2 +#define HDA1_DEVID 0x157a +#define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC) +#define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC) + +/* HT Configuration */ +#define HT_DEV 0x18 +#define HT_FUNC 0 +#define HT_DEVID 0x15b0 +#define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC) +#define SOC_HT_DEV _SOC_DEV(HT_DEV, HT_FUNC) + +/* Address Maps */ +#define ADDR_DEV 0x18 +#define ADDR_FUNC 1 +#define ADDR_DEVID 0x15b1 +#define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC) +#define SOC_ADDR_DEV _SOC_DEV(ADDR_DEV, ADDR_FUNC) + +/* DRAM Configuration */ +#define DCT_DEV 0x18 +#define DCT_FUNC 2 +#define DCT_DEVID 0x15b2 +#define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC) +#define SOC_DCT_DEV _SOC_DEV(DCT_DEV, DCT_FUNC) + +/* Misc. Configuration */ +#define MISC_DEV 0x18 +#define MISC_FUNC 3 +#define MISC_DEVID 0x15b3 +#define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC) +#define SOC_MISC_DEV _SOC_DEV(MISC_DEV, MISC_FUNC) + +/* PM Configuration */ +#define PM_DEV 0x18 +#define PM_FUNC 4 +#define PM_DEVID 0x15b4 +#define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC) +#define SOC_PM_DEV _SOC_DEV(PM_DEV, PM_FUNC) + +/* Northbridge Configuration */ +#define NB_DEV 0x18 +#define NB_FUNC 5 +#define NB_DEVID 0x15b5 +#define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC) +#define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC) + +/* XHCI */ +#define XHCI_DEV 0x10 +#define XHCI_FUNC 0 +#define XHCI_DEVID 0x7914 +#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) +#define SOC_XHCI_DEV _SOC_DEV(XHCI_DEV, XHCI_FUNC) + +/* SATA */ +#define SATA_DEV 0x11 +#define SATA_FUNC 0 +#define SATA_IDE_DEVID 0x7900 +#define AHCI_DEVID_MS 0x7901 +#define AHCI_DEVID_AMD 0x7904 +#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) +#define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) + +/* EHCI */ +#define EHCI_DEV 0x12 +#define EHCI_FUNC 0 +#define EHCI_DEVID 0x7908 +#define EHCI1_DEVFN PCI_DEVFN(EHCI_DEV, EHCI_FUNC) +#define SOC_EHCI1_DEV _SOC_DEV(EHCI_DEV, EHCI_FUNC) + +/* SMBUS */ +#define SMBUS_DEV 0x14 +#define SMBUS_FUNC 0 +#define SMBUS_DEVID 0x790b +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) +#define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC) + +/* LPC BUS */ +#define PCU_DEV 0x14 +#define LPC_FUNC 3 +#define LPC_DEVID 0x790e +#define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) +#define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) + +/* SD Controller */ +#define SD_DEV 0x14 +#define SD_FUNC 7 +#define SD_DEVID 0x7906 +#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) +#define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC) + +#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h new file mode 100644 index 0000000000..6ce79b424e --- /dev/null +++ b/src/soc/amd/picasso/include/soc/romstage.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __STONEYRIDGE_ROMSTAGE_H__ +#define __STONEYRIDGE_ROMSTAGE_H__ + +void mainboard_romstage_entry(int s3_resume); + +#endif /* __STONEYRIDGE_ROMSTAGE_H__ */ diff --git a/src/soc/amd/picasso/include/soc/smbus.h b/src/soc/amd/picasso/include/soc/smbus.h new file mode 100644 index 0000000000..391084d807 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/smbus.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __STONEYRIDGE_SMBUS_H__ +#define __STONEYRIDGE_SMBUS_H__ + +#include +#include + +#define SMB_SPEED_400KHZ (66000000 / (400000 * 4)) + +/* + * Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100 * 1000 * 10) + +int do_smbus_read_byte(u32 mmio, u8 device, u8 address); +int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val); +int do_smbus_recv_byte(u32 mmio, u8 device); +int do_smbus_send_byte(u32 mmio, u8 device, u8 val); + +#endif /* __STONEYRIDGE_SMBUS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h new file mode 100644 index 0000000000..000eed8554 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -0,0 +1,242 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Alexandru Gagniuc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ +#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ + + +#define SMI_GEVENTS 24 +#define SCIMAPS 58 +#define SCI_GPES 32 + +#define SMI_EVENT_STATUS 0x0 +#define SMI_EVENT_ENABLE 0x04 +#define SMI_SCI_TRIG 0x08 +#define SMI_SCI_LEVEL 0x0c +#define SMI_SCI_STATUS 0x10 +#define SMI_SCI_EN 0x14 +#define SMI_SCI_MAP0 0x40 +# define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X)) + +/* SMI source and status */ +#define SMITYPE_AGPIO65 0 +#define SMITYPE_AGPIO66 1 +#define SMITYPE_AGPIO3 2 +#define SMITYPE_LPCPME_AGPIO22 3 +#define SMITYPE_GPIO4 4 +#define SMITYPE_LPCPD_AGPIOG21 5 +#define SMITYPE_IRTX1_G15 6 +#define SMITYPE_AGPIO5_DEVSLP0 7 +#define SMITYPE_WAKE_AGPIO2 8 +#define SMITYPE_APIO68_SGPIOCLK 9 +#define SMITYPE_AGPIO6 10 +#define SMITYPE_GPIO7 11 +#define SMITYPE_USBOC0_TRST_AGPIO16 12 +#define SMITYPE_USB0C1_TDI_AGPIO17 13 +#define SMITYPE_USBOC2_TCK_AGPIO18 14 +#define SMITYPE_TDO_USB0C3_AGPIO24 15 +#define SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23 16 +/* 17 Reserved */ +#define SMITYPE_BLINK_AGPIO11_USBOC7 18 +#define SMITYPE_SYSRESET_AGPIO1 19 +#define SMITYPE_IRRX1_AGPIO15 20 +#define SMITYPE_IRTX0_USBOC5_AGPIO13 21 +#define SMITYPE_GPIO9_SERPORTRX 22 +#define SMITYPE_GPIO8_SEPORTTX 23 +#define GEVENT_MASK ((1 << SMITYPE_AGPIO65) \ + | (1 << SMITYPE_AGPIO66) \ + | (1 << SMITYPE_AGPIO3) \ + | (1 << SMITYPE_LPCPME_AGPIO22) \ + | (1 << SMITYPE_GPIO4) \ + | (1 << SMITYPE_LPCPD_AGPIOG21) \ + | (1 << SMITYPE_IRTX1_G15) \ + | (1 << SMITYPE_AGPIO5_DEVSLP0) \ + | (1 << SMITYPE_WAKE_AGPIO2) \ + | (1 << SMITYPE_APIO68_SGPIOCLK) \ + | (1 << SMITYPE_AGPIO6) \ + | (1 << SMITYPE_GPIO7) \ + | (1 << SMITYPE_USBOC0_TRST_AGPIO16) \ + | (1 << SMITYPE_USB0C1_TDI_AGPIO17) \ + | (1 << SMITYPE_USBOC2_TCK_AGPIO18) \ + | (1 << SMITYPE_TDO_USB0C3_AGPIO24) \ + | (1 << SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23) \ + | (1 << SMITYPE_BLINK_AGPIO11_USBOC7) \ + | (1 << SMITYPE_SYSRESET_AGPIO1) \ + | (1 << SMITYPE_IRRX1_AGPIO15) \ + | (1 << SMITYPE_IRTX0_USBOC5_AGPIO13) \ + | (1 << SMITYPE_GPIO9_SERPORTRX)) +#define SMITYPE_EHCI0_WAKE 24 +#define SMITYPE_EHCI1_WAKE 25 +#define SMITYPE_ESPI_SYS 26 +#define SMITYPE_ESPI_WAKE_PME 27 +/* 28-32 Reserved */ +#define SMITYPE_FCH_FAKE0 33 +#define SMITYPE_FCH_FAKE1 34 +#define SMITYPE_FCH_FAKE2 35 +/* 36 Reserved */ +#define SMITYPE_SATA_GEVENT0 37 +#define SMITYPE_SATA_GEVENT1 38 +#define SMITYPE_ACP_WAKE 39 +#define SMITYPE_ECG 40 +#define SMITYPE_GPIO_CTL 41 +#define SMITYPE_CIR_PME 42 +#define SMITYPE_ALT_HPET_ALARM 43 +#define SMITYPE_FAN_THERMAL 44 +#define SMITYPE_ASF_MASTER_SLAVE 45 +#define SMITYPE_I2S_WAKE 46 +#define SMITYPE_SMBUS0_MASTER 47 +#define SMITYPE_TWARN 48 +#define SMITYPE_TRAFFIC_MON 49 +#define SMITYPE_ILLB 50 +#define SMITYPE_PWRBUTTON_UP 51 +#define SMITYPE_PROCHOT 52 +#define SMITYPE_APU_HW 53 +#define SMITYPE_NB_SCI 54 +#define SMITYPE_RAS_SERR 55 +#define SMITYPE_XHC0_PME 56 +/* 57 Reserved */ +#define SMITYPE_ACDC_TIMER 58 +/* 59-62 Reserved */ +#define SMITYPE_TEMP_TSI 63 +#define SMITYPE_KB_RESET 64 +#define SMITYPE_SLP_TYP 65 +#define SMITYPE_AL2H_ACPI 66 +#define SMITYPE_AHCI 67 +/* 68-71 Reserved */ +#define SMITYPE_GBL_RLS 72 +#define SMITYPE_BIOS_RLS 73 +#define SMITYPE_PWRBUTTON_DOWN 74 +#define SMITYPE_SMI_CMD_PORT 75 +#define SMITYPE_USB_SMI 76 +#define SMITYPE_SERIRQ 77 +#define SMITYPE_SMBUS0_INTR 78 +#define SMITYPE_XHC_ERROR 80 +#define SMITYPE_INTRUDER 81 +#define SMITYPE_VBAT_LOW 82 +#define SMITYPE_PROTHOT 83 +#define SMITYPE_PCI_SERR 84 +#define SMITYPE_GPP_SERR 85 +/* 85-88 Reserved */ +#define SMITYPE_TMERTRIP 89 +#define SMITYPE_EMUL60_64 90 +#define SMITYPE_USB_FLR 91 +#define SMITYPE_SATA_FLR 92 +#define SMITYPE_AZ_FLR 93 +/* 94-132 Reserved */ +#define SMITYPE_FANIN0 133 +/* 134-137 Reserved */ +#define SMITYPE_FAKE0 138 +#define SMITYPE_FAKE1 139 +#define SMITYPE_FAKE2 140 +/* 141 Reserved */ +#define SMITYPE_SHORT_TIMER 142 +#define SMITYPE_LONG_TIMER 143 +#define SMITYPE_AB_SMI 144 +#define SMITYPE_SOFT_RESET 145 +/* 146-147 Reserved */ +#define SMITYPE_IOTRAP0 148 +/* 149-151 Reserved */ +#define SMITYPE_MEMTRAP0 152 +/* 153-155 Reserved */ +#define SMITYPE_CFGTRAP0 156 +/* 157-159 Reserved */ +#define NUMBER_SMITYPES 160 +#define TYPE_TO_MASK(X) (1 << (X) % 32) + +#define SMI_REG_SMISTS0 0x80 +#define SMI_REG_SMISTS1 0x84 +#define SMI_REG_SMISTS2 0x88 +#define SMI_REG_SMISTS3 0x8c +#define SMI_REG_SMISTS4 0x90 + +#define SMI_REG_POINTER 0x94 +# define SMI_STATUS_SRC_SCI (1 << 0) +# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */ +# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */ +# define SMI_STATUS_SRC_2 (1 << 3) +# define SMI_STATUS_SRC_3 (1 << 4) +# define SMI_STATUS_SRC_4 (1 << 5) + +#define SMI_TIMER 0x96 +#define SMI_TIMER_MASK 0x7fff +#define SMI_TIMER_EN (1 << 15) + +#define SMI_REG_SMITRIG0 0x98 +# define SMITRG0_EOS (1 << 28) +# define SMI_TIMER_SEL (1 << 29) +# define SMITRG0_SMIENB (1 << 31) + +#define SMI_REG_CONTROL0 0xa0 +#define SMI_REG_CONTROL1 0xa4 +#define SMI_REG_CONTROL2 0xa8 +#define SMI_REG_CONTROL3 0xac +#define SMI_REG_CONTROL4 0xb0 +#define SMI_REG_CONTROL5 0xb4 +#define SMI_REG_CONTROL6 0xb8 +#define SMI_REG_CONTROL7 0xbc +#define SMI_REG_CONTROL8 0xc0 +#define SMI_REG_CONTROL9 0xc4 + +enum smi_mode { + SMI_MODE_DISABLE = 0, + SMI_MODE_SMI = 1, + SMI_MODE_NMI = 2, + SMI_MODE_IRQ13 = 3, +}; + +enum smi_sci_type { + INTERRUPT_NONE, + INTERRUPT_SCI, + INTERRUPT_SMI, + INTERRUPT_BOTH, +}; + +enum smi_sci_lvl { + SMI_SCI_LVL_LOW, + SMI_SCI_LVL_HIGH, +}; + +enum smi_sci_dir { + SMI_SCI_EDG, + SMI_SCI_LVL, +}; + +struct smi_sources_t { + int type; + void (*handler)(void); +}; + +struct sci_source { + uint8_t scimap; /* SCIMAP 0-57 */ + uint8_t gpe; /* 32 GPEs */ + uint8_t direction; /* Active High or Low, smi_sci_lvl */ + uint8_t level; /* Edge or Level, smi_sci_dir */ +}; + +uint16_t pm_acpi_smi_cmd_port(void); +void configure_smi(uint8_t smi_num, uint8_t mode); +void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); +void configure_scimap(const struct sci_source *sci); +void disable_gevent_smi(uint8_t gevent); +void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); +void soc_route_sci(uint8_t event); + +#ifndef __SMM__ +void enable_smi_generation(void); +#endif + +#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h new file mode 100644 index 0000000000..ad4040759c --- /dev/null +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -0,0 +1,415 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __STONEYRIDGE_H__ +#define __STONEYRIDGE_H__ + +#include +#include +#include +#include +#include "chip.h" + +/* + * AcpiMmio Region + * - fixed addresses offset from 0xfed80000 + */ + +/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PM_DECODE_EN 0x00 +#define CF9_IO_EN BIT(1) +#define LEGACY_IO_EN BIT(0) +#define PM_ISA_CONTROL 0x04 +#define MMIO_EN BIT(1) +#define PM_PCI_CTRL 0x08 +#define FORCE_SLPSTATE_RETRY BIT(25) +#define FORCE_STPCLK_RETRY BIT(24) + +#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN */ + +#define PWR_RESET_CFG 0x10 +#define TOGGLE_ALL_PWR_GOOD BIT(1) + +#define PM_SERIRQ_CONF 0x54 +#define PM_SERIRQ_NUM_BITS_17 0x0000 +#define PM_SERIRQ_NUM_BITS_18 0x0004 +#define PM_SERIRQ_NUM_BITS_19 0x0008 +#define PM_SERIRQ_NUM_BITS_20 0x000c +#define PM_SERIRQ_NUM_BITS_21 0x0010 +#define PM_SERIRQ_NUM_BITS_22 0x0014 +#define PM_SERIRQ_NUM_BITS_23 0x0018 +#define PM_SERIRQ_NUM_BITS_24 0x001c +#define PM_SERIRQ_MODE BIT(6) +#define PM_SERIRQ_ENABLE BIT(7) + +#define PM_RTC_SHADOW 0x5b /* state when power resumes */ +#define PM_S5_AT_POWER_RECOVERY 0x04 /* S5 */ +#define PM_RESTORE_S0_IF_PREV_S0 0x07 /* S0 if previously at S0 */ + +#define PM_EVT_BLK 0x60 +#define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */ +#define PCIEXPWAK_STS BIT(14) +#define RTC_STS BIT(10) +#define PWRBTN_STS BIT(8) +#define GBL_STS BIT(5) +#define BM_STS BIT(4) +#define TIMER_STS BIT(0) +#define PCIEXPWAK_DIS BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */ +#define RTC_EN BIT(10) +#define PWRBTN_EN BIT(8) +#define GBL_EN BIT(5) +#define TIMER_STS BIT(0) +#define PM1_CNT_BLK 0x62 +#define PM_TMR_BLK 0x64 +#define PM_CPU_CTRL 0x66 +#define PM_GPE0_BLK 0x68 +#define PM_ACPI_SMI_CMD 0x6a +#define PM_ACPI_CONF 0x74 +#define PM_ACPI_DECODE_STD BIT(0) +#define PM_ACPI_GLOBAL_EN BIT(1) +#define PM_ACPI_RTC_EN_EN BIT(2) +#define PM_ACPI_TIMER_EN_EN BIT(4) +#define PM_ACPI_MASK_ARB_DIS BIT(6) +#define PM_ACPI_BIOS_RLS BIT(7) +#define PM_ACPI_PWRBTNEN_EN BIT(8) +#define PM_ACPI_REDUCED_HW_EN BIT(9) +#define PM_ACPI_BLOCK_PCIE_PME BIT(24) +#define PM_ACPI_PCIE_WAK_MASK BIT(25) +#define PM_ACPI_WAKE_AS_GEVENT BIT(27) +#define PM_ACPI_NB_PME_GEVENT BIT(28) +#define PM_ACPI_RTC_WAKE_EN BIT(29) +#define PM_RST_CTRL1 0xbe +#define SLPTYPE_CONTROL_EN BIT(5) +#define PM_RST_STATUS 0xc0 +#define PM_PCIB_CFG 0xea +#define PM_GENINT_DISABLE BIT(0) +#define PM_LPC_GATING 0xec +#define PM_LPC_AB_NO_BYPASS_EN BIT(2) +#define PM_LPC_A20_EN BIT(1) +#define PM_LPC_ENABLE BIT(0) +#define PM_USB_ENABLE 0xef +#define PM_USB_ALL_CONTROLLERS 0x7f + +/* SMBUS MMIO offsets 0xfed80a00 */ +#define SMBHSTSTAT 0x0 +#define SMBHST_STAT_FAILED 0x10 +#define SMBHST_STAT_COLLISION 0x08 +#define SMBHST_STAT_ERROR 0x04 +#define SMBHST_STAT_INTERRUPT 0x02 +#define SMBHST_STAT_BUSY 0x01 +#define SMBHST_STAT_CLEAR 0xff +#define SMBHST_STAT_NOERROR 0x02 +#define SMBHST_STAT_VAL_BITS 0x1f +#define SMBHST_STAT_ERROR_BITS 0x1c + +#define SMBSLVSTAT 0x1 +#define SMBSLV_STAT_ALERT 0x20 +#define SMBSLV_STAT_SHADOW2 0x10 +#define SMBSLV_STAT_SHADOW1 0x08 +#define SMBSLV_STAT_SLV_STS 0x04 +#define SMBSLV_STAT_SLV_INIT 0x02 +#define SMBSLV_STAT_SLV_BUSY 0x01 +#define SMBSLV_STAT_CLEAR 0x1f + +#define SMBHSTCTRL 0x2 +#define SMBHST_CTRL_RST 0x80 +#define SMBHST_CTRL_STRT 0x40 +#define SMBHST_CTRL_QCK_RW 0x00 +#define SMBHST_CTRL_BTE_RW 0x04 +#define SMBHST_CTRL_BDT_RW 0x08 +#define SMBHST_CTRL_WDT_RW 0x0c +#define SMBHST_CTRL_BLK_RW 0x14 +#define SMBHST_CTRL_MODE_BITS 0x1c +#define SMBHST_CTRL_KILL 0x02 +#define SMBHST_CTRL_IEN 0x01 + +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc +#define SMBTIMING 0xe + +/* FCH MISC Registers 0xfed80e00 */ +#define GPP_CLK_CNTRL 0x00 +#define GPP_CLK2_REQ_MAP_SHIFT 8 +#define GPP_CLK2_REQ_MAP_MASK (0xf << GPP_CLK2_REQ_MAP_SHIFT) +#define GPP_CLK2_REQ_MAP_CLK_REQ2 3 +#define GPP_CLK0_REQ_MAP_SHIFT 0 +#define GPP_CLK0_REQ_MAP_MASK (0xf << GPP_CLK0_REQ_MAP_SHIFT) +#define GPP_CLK0_REQ_MAP_CLK_REQ0 1 +#define MISC_CGPLL_CONFIG1 0x08 +#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) +#define MISC_CGPLL_CONFIG3 0x10 +#define CG1PLL_REFDIV_SHIFT 0 +#define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT) +#define CG1PLL_FBDIV_SHIFT 10 +#define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT) +#define MISC_CGPLL_CONFIG4 0x14 +#define SS_STEP_SIZE_DSFRAC_SHIFT 0 +#define SS_STEP_SIZE_DSFRAC_MASK (0xffff << SS_STEP_SIZE_DSFRAC_SHIFT) +#define SS_AMOUNT_DSFRAC_SHIFT 16 +#define SS_AMOUNT_DSFRAC_MASK (0xffff << SS_AMOUNT_DSFRAC_SHIFT) +#define MISC_CGPLL_CONFIG5 0x18 +#define SS_AMOUNT_NFRAC_SLIP_SHIFT 8 +#define SS_AMOUNT_NFRAC_SLIP_MASK (0xf << SS_AMOUNT_NFRAC_SLIP_SHIFT) +#define MISC_CGPLL_CONFIG6 0x1c +#define CG1PLL_LF_MODE_SHIFT 9 +#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT) +#define MISC_CLK_CNTL1 0x40 +#define CG1PLL_FBDIV_TEST BIT(26) +#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ +#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ + +/* XHCI_PM Registers: 0xfed81c00 */ +#define XHCI_PM_INDIRECT_INDEX 0x48 +#define XHCI_PM_INDIRECT_DATA 0x4c +#define XHCI_OVER_CURRENT_CONTROL 0x30 +#define USB_OC0 0 +#define USB_OC1 1 +#define USB_OC2 2 +#define USB_OC3 3 +#define USB_OC4 4 +#define USB_OC5 5 +#define USB_OC6 6 +#define USB_OC7 7 +#define USB_OC_DISABLE 0xf +#define USB_OC_DISABLE_ALL 0xffff +#define OC_PORT0_SHIFT 0 +#define OC_PORT1_SHIFT 4 +#define OC_PORT2_SHIFT 8 +#define OC_PORT3_SHIFT 12 + +#define EHCI_OVER_CURRENT_CONTROL 0x70 +#define EHCI_HUB_CONFIG4 0x90 +#define DEBUG_PORT_SELECT_SHIFT 16 +#define DEBUG_PORT_ENABLE BIT(18) +#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18)) + +/* FCH AOAC Registers 0xfed81e00 */ +#define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 +#define FCH_AOAC_D3_CONTROL_I2C0 0x4a +#define FCH_AOAC_D3_CONTROL_I2C1 0x4c +#define FCH_AOAC_D3_CONTROL_I2C2 0x4e +#define FCH_AOAC_D3_CONTROL_I2C3 0x50 +#define FCH_AOAC_D3_CONTROL_UART0 0x56 +#define FCH_AOAC_D3_CONTROL_UART1 0x58 +#define FCH_AOAC_D3_CONTROL_AMBA 0x62 +#define FCH_AOAC_D3_CONTROL_USB2 0x64 +#define FCH_AOAC_D3_CONTROL_USB3 0x6e +/* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */ +#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) +#define FCH_AOAC_DEVICE_STATE BIT(2) +#define FCH_AOAC_PWR_ON_DEV BIT(3) +#define FCH_AOAC_SW_PWR_ON_RSTB BIT(4) +#define FCH_AOAC_SW_REF_CLK_OK BIT(5) +#define FCH_AOAC_SW_RST_B BIT(6) +#define FCH_AOAC_IS_SW_CONTROL BIT(7) + +#define FCH_AOAC_D3_STATE_CLK_GEN 0x41 +#define FCH_AOAC_D3_STATE_I2C0 0x4b +#define FCH_AOAC_D3_STATE_I2C1 0x4d +#define FCH_AOAC_D3_STATE_I2C2 0x4f +#define FCH_AOAC_D3_STATE_I2C3 0x51 +#define FCH_AOAC_D3_STATE_UART0 0x57 +#define FCH_AOAC_D3_STATE_UART1 0x59 +#define FCH_AOAC_D3_STATE_AMBA 0x63 +#define FCH_AOAC_D3_STATE_USB2 0x65 +#define FCH_AOAC_D3_STATE_USB3 0x6f +/* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */ +#define FCH_AOAC_PWR_RST_STATE BIT(0) +#define FCH_AOAC_RST_CLK_OK_STATE BIT(1) +#define FCH_AOAC_RST_B_STATE BIT(2) +#define FCH_AOAC_DEV_OFF_GATING_STATE BIT(3) +#define FCH_AOAC_D3COLD BIT(4) +#define FCH_AOAC_CLK_OK_STATE BIT(5) +#define FCH_AOAC_STAT0 BIT(6) +#define FCH_AOAC_STAT1 BIT(7) + +#define PM1_LIMIT 16 +#define GPE0_LIMIT 28 +#define TOTAL_BITS(a) (8 * sizeof(a)) + +/* SATA Controller D11F0 */ +#define SATA_MISC_CONTROL_REG 0x40 +#define SATA_MISC_SUBCLASS_WREN BIT(0) +/* Register in AHCIBaseAddress (BAR5 at D11F0x24) */ +#define SATA_CAPABILITIES_REG 0xfc +#define SATA_CAPABILITY_SPM BIT(12) + +/* SPI Controller (base address in D14F3xA0) */ +#define SPI_BASE_ALIGNMENT BIT(6) + +#define SPI_CNTRL0 0x00 +#define SPI_BUSY BIT(31) +#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) +/* Nominal is 16.7MHz on older devices, 33MHz on newer */ +#define SPI_READ_MODE_NOM 0x00000000 +#define SPI_READ_MODE_DUAL112 ( BIT(29) ) +#define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18)) +#define SPI_READ_MODE_DUAL122 (BIT(30) ) +#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) +#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) +#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) +#define SPI_FIFO_PTR_CLR BIT(20) +#define SPI_ARB_ENABLE BIT(19) +#define EXEC_OPCODE BIT(16) +#define SPI_CNTRL1 0x0c +#define SPI_CMD_CODE 0x45 +#define SPI_CMD_TRIGGER 0x47 +#define SPI_CMD_TRIGGER_EXECUTE BIT(7) +#define SPI_TX_BYTE_COUNT 0x48 +#define SPI_RX_BYTE_COUNT 0x4b +#define SPI_STATUS 0x4c +#define SPI_DONE_BYTE_COUNT_SHIFT 0 +#define SPI_DONE_BYTE_COUNT_MASK 0xff +#define SPI_FIFO_WR_PTR_SHIFT 8 +#define SPI_FIFO_WR_PTR_MASK 0x7f +#define SPI_FIFO_RD_PTR_SHIFT 16 +#define SPI_FIFO_RD_PTR_MASK 0x7f +#define SPI_FIFO 0x80 +#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO) + +#define SPI100_ENABLE 0x20 +#define SPI_USE_SPI100 BIT(0) + +/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ +#define SPI100_SPEED_CONFIG 0x22 +#define SPI_SPEED_66M (0x0) +#define SPI_SPEED_33M ( BIT(0)) +#define SPI_SPEED_22M ( BIT(1) ) +#define SPI_SPEED_16M ( BIT(1) | BIT(0)) +#define SPI_SPEED_100M (BIT(2) ) +#define SPI_SPEED_800K (BIT(2) | BIT(0)) +#define SPI_NORM_SPEED_NEW_SH 12 +#define SPI_FAST_SPEED_NEW_SH 8 +#define SPI_ALT_SPEED_NEW_SH 4 +#define SPI_TPM_SPEED_NEW_SH 0 + +#define SPI100_HOST_PREF_CONFIG 0x2c +#define SPI_RD4DW_EN_HOST BIT(15) + +/* Platform Security Processor D8F0 */ +#define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */ +#define PSP_BAR_ENABLES 0x48 +#define PSP_MAILBOX_BAR_EN 0x10 + +/* IO 0xcf9 - Reset control port*/ +#define FULL_RST BIT(3) +#define RST_CMD BIT(2) +#define SYS_RST BIT(1) + +struct stoneyridge_aoac { + int enable; + int status; +}; + +typedef struct aoac_devs { + unsigned int :5; + unsigned int ic0e:1; /* 5: I2C0 */ + unsigned int ic1e:1; /* 6: I2C1 */ + unsigned int ic2e:1; /* 7: I2C2 */ + unsigned int ic3e:1; /* 8: I2C3 */ + unsigned int :2; + unsigned int ut0e:1; /* 11: UART0 */ + unsigned int ut1e:1; /* 12: UART1 */ + unsigned int :2; + unsigned int st_e:1; /* 15: SATA */ + unsigned int :2; + unsigned int ehce:1; /* 18: EHCI */ + unsigned int :4; + unsigned int xhce:1; /* 23: xHCI */ + unsigned int sd_e:1; /* 24: SDIO */ + unsigned int :2; + unsigned int espi:1; /* 27: ESPI */ + unsigned int :4; +} __packed aoac_devs_t; + +struct soc_power_reg { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t gpe0_sts; + uint32_t gpe0_en; + uint16_t wake_from; +}; + +#define XHCI_FW_SIG_OFFSET 0xc +#define XHCI_FW_ADDR_OFFSET 0x6 +#define XHCI_FW_SIZE_OFFSET 0x8 +#define XHCI_FW_BOOTRAM_SIZE 0x8000 + +void enable_aoac_devices(void); +void sb_clk_output_48Mhz(u32 osc); +void sb_disable_4dw_burst(void); +void sb_enable(struct device *dev); +void southbridge_final(void *chip_info); +void southbridge_init(void *chip_info); +void sb_read_mode(u32 mode); +void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); +void bootblock_fch_early_init(void); +void bootblock_fch_init(void); +/** + * @brief Save the UMA bize returned by AGESA + * + * @param size = in bytes + * + * @return none + */ +void save_uma_size(uint32_t size); +/** + * @brief Save the UMA base address returned by AGESA + * + * @param base = 64bit base address + * + * @return none + */ +void save_uma_base(uint64_t base); +/** + * @brief Get the saved UMA size + * + * @param none + * + * @return size in bytes + */ +uint32_t get_uma_size(void); +/** + * @brief Get the saved UMA base + * + * @param none + * + * @return 64bit base address + */ +uint64_t get_uma_base(void); +/* + * Call the mainboard to get the USB Over Current Map. The mainboard + * returns the map and 0 on Success or -1 on error or no map. There is + * a default weak function in usb.c if the mainboard doesn't have any + * over current support. + */ +int mainboard_get_xhci_oc_map(uint16_t *usb_oc_map); +int mainboard_get_ehci_oc_map(uint16_t *usb_oc_map); + +/* Initialize all the i2c buses that are marked with early init. */ +void i2c_soc_early_init(void); + +/* Initialize all the i2c buses that are not marked with early init. */ +void i2c_soc_init(void); + +#endif /* __STONEYRIDGE_H__ */ diff --git a/src/soc/amd/picasso/makefile.inc b/src/soc/amd/picasso/makefile.inc new file mode 100644 index 0000000000..babd878524 --- /dev/null +++ b/src/soc/amd/picasso/makefile.inc @@ -0,0 +1,316 @@ +#***************************************************************************** +# +# Copyright (c) 2012, 2016-2017 Advanced Micro Devices, Inc. +# 2013 - 2014 Sage Electronic Engineering, LLC +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#***************************************************************************** +ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) + +subdirs-y += ../../../cpu/amd/mtrr/ +subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/cache +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/pae +subdirs-y += ../../../cpu/x86/smm + +bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c +bootblock-y += BiosCallOuts.c +bootblock-y += bootblock/bootblock.c +bootblock-y += gpio.c +bootblock-y += i2c.c +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +bootblock-y += monotonic_timer.c +bootblock-y += pmutil.c +bootblock-y += reset.c +bootblock-y += tsc_freq.c +bootblock-y += southbridge.c +bootblock-y += nb_util.c +bootblock-$(CONFIG_SPI_FLASH) += spi.c +bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c + +romstage-y += BiosCallOuts.c +romstage-y += i2c.c +romstage-y += romstage.c +romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +romstage-y += gpio.c +romstage-y += monotonic_timer.c +romstage-y += pmutil.c +romstage-y += reset.c +romstage-y += smbus.c +romstage-y += smbus_spd.c +romstage-y += ramtop.c +romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +romstage-y += tsc_freq.c +romstage-y += southbridge.c +romstage-y += nb_util.c +romstage-$(CONFIG_SPI_FLASH) += spi.c +romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c + +verstage-y += gpio.c +verstage-y += i2c.c +verstage-y += monotonic_timer.c +verstage-y += pmutil.c +verstage-y += reset.c +verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +verstage-y += tsc_freq.c +verstage-y += nb_util.c +verstage-$(CONFIG_SPI_FLASH) += spi.c + +postcar-y += monotonic_timer.c +postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c +postcar-y += ramtop.c +postcar-y += nb_util.c +postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c +postcar-y += tsc_freq.c + +ramstage-y += BiosCallOuts.c +ramstage-y += i2c.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += mca.c +ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-y += gpio.c +ramstage-y += monotonic_timer.c +ramstage-y += southbridge.c +ramstage-y += northbridge.c +ramstage-y += pmutil.c +ramstage-y += reset.c +ramstage-y += sata.c +ramstage-y += sm.c +ramstage-y += smbus.c +ramstage-y += ramtop.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +ramstage-y += usb.c +ramstage-y += tsc_freq.c +ramstage-$(CONFIG_SPI_FLASH) += spi.c +ramstage-y += finalize.c +ramstage-y += nb_util.c + +smm-y += monotonic_timer.c +smm-y += smihandler.c +smm-y += smi_util.c +smm-y += tsc_freq.c +smm-$(CONFIG_DEBUG_SMI) += uart.c +smm-$(CONFIG_SPI_FLASH) += spi.c +smm-y += nb_util.c +smm-y += gpio.c + +CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge +CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include +CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/acpi + +# ROMSIG Normally At ROMBASE + 0x20000 +# Overridden by CONFIG_AMD_FWM_POSITION_INDEX +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# +-----------+---------------+----------------+------------+ +# |PSPDIR ADDR| +# +-----------+ +# +# EC ROM should be 64K aligned. +STONEYRIDGE_FWM_POSITION=$(call int-add, \ + $(call int-subtract, 0xffffffff \ + $(call int-shift-left, \ + 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) + +### 0 +FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) +FIRMWARE_TYPE=ST + +###5 +PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key + +###1 +PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin + +###3 +PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin + +###4 +PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin + +###8 - Check for SMU firmware named either *.sbin or *.csbin +### TODO: Remove *.sbin section after the blobs repo is updated. +SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE).csbin +SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE)_FN.csbin +ifeq ("$(wildcard $(SMUFWM_FILE))","") +SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin +SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin +endif + +###95 +SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin + +###9 +PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key + +ifeq ($(CONFIG_USE_PSPSECUREOS),y) +###2 +PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin + +###12 +PSPTRUSTLETS_FILE=$(wildcard $(top)/$(FIRMWARE_LOCATE)/PspTrustlets*_prod_$(FIRMWARE_TYPE).cbin) + +###13 +TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin +endif + +###18- Check for SMU firmware2 named either *.sbin or *.csbin +### TODO: Remove *.sbin section after the blobs repo is updated. +SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).csbin +SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE)_FN.csbin +ifeq ("$(wildcard $(SMUFIRMWARE2_FILE))","") +SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin +SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE)_FN.sbin +endif + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) +OPT_STONEYRIDGE_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_GEC_FWM_FILEddd), --gec) + +OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) +OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) +OPT_SMUFWM_FILE=$(call add_opt_prefix, $(SMUFWM_FILE), --smufirmware) +OPT_PSPRCVR_FILE=$(call add_opt_prefix, $(PSPRCVR_FILE), --recovery) +OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(PUBSIGNEDKEY_FILE), --rtmpubkey) +OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) +OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(PSPSECUREDEBUG_FILE), --securedebug) +ifeq ($(CONFIG_USE_PSPSECUREOS),y) +OPT_PSPSCUREOS_FILE=$(call add_opt_prefix, $(PSPSCUREOS_FILE), --secureos) +OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(PSPTRUSTLETS_FILE), --trustlets) +OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(TRUSTLETKEY_FILE), --trustletkey) +endif +OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware2) +OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) +SUBPROG_FN_SMU_FW=1 +OPT_SMUFWM_FN_FILE=$(call add_opt_prefix, $(SMUFWM_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware) +OPT_SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware2) + + +$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ + $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ + $(call strip_quotes, $(PSPBTLDR_FILE)) \ + $(call strip_quotes, $(PSPRCVR_FILE)) \ + $(call strip_quotes, $(PSPSCUREOS_FILE)) \ + $(call strip_quotes, $(PSPNVRAM_FILE)) \ + $(call strip_quotes, $(SMUFWM_FILE)) \ + $(call strip_quotes, $(SMUFWM_FN_FILE)) \ + $(call strip_quotes, $(SMUSCS_FILE)) \ + $(call strip_quotes, $(PSPSECUREDEBUG_FILE)) \ + $(call strip_quotes, $(PSPTRUSTLETS_FILE)) \ + $(call strip_quotes, $(TRUSTLETKEY_FILE)) \ + $(call strip_quotes, $(SMUFIRMWARE2_FILE)) \ + $(call strip_quotes, $(SMUFIRMWARE2_FN_FILE)) \ + $(AMDFWTOOL) + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(OPT_STONEYRIDGE_XHCI_FWM_FILE) \ + $(OPT_STONEYRIDGE_GEC_FWM_FILE) \ + $(OPT_AMD_PUBKEY_FILE) \ + $(OPT_PSPBTLDR_FILE) \ + $(OPT_SMUFWM_FILE) \ + $(OPT_PSPRCVR_FILE) \ + $(OPT_PUBSIGNEDKEY_FILE) \ + $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSPNVRAM_FILE) \ + $(OPT_PSPSECUREDEBUG_FILE) \ + $(OPT_PSPTRUSTLETS_FILE) \ + $(OPT_TRUSTLETKEY_FILE) \ + $(OPT_SMUFIRMWARE2_FILE) \ + $(OPT_SMUSCS_FILE) \ + $(OPT_AMD_PUBKEY_FILE) \ + $(OPT_PSPBTLDR_FILE) \ + $(OPT_SMUFWM_FILE) \ + $(OPT_SMUFWM_FN_FILE) \ + $(OPT_PSPRCVR_FILE) \ + $(OPT_PUBSIGNEDKEY_FILE) \ + $(OPT_PSPSCUREOS_FILE) \ + $(OPT_PSPNVRAM_FILE) \ + $(OPT_PSPSECUREDEBUG_FILE) \ + $(OPT_PSPTRUSTLETS_FILE) \ + $(OPT_TRUSTLETKEY_FILE) \ + $(OPT_SMUFIRMWARE2_FILE) \ + $(OPT_SMUFIRMWARE2_FN_FILE) \ + $(OPT_SMUSCS_FILE) \ + --combo-capable \ + --flashsize $(CONFIG_ROM_SIZE) \ + --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ + --output $@ + +ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) +PHONY+=add_amdfw +INTERMEDIATE+=add_amdfw + +# Calculate firmware position inside the ROM +STONEYRIDGE_FWM_ROM_POSITION=$(call int-add, \ + $(call int-subtract, $(CONFIG_ROM_SIZE) \ + $(call int-shift-left, \ + 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000) + +add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom + printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \ + "$(STONEYRIDGE_FWM_ROM_POSITION)" + dd if=$(obj)/amdfw.rom \ + of=$(obj)/coreboot.pre conv=notrunc bs=1 \ + seek=$(STONEYRIDGE_FWM_ROM_POSITION) >/dev/null 2>&1 + +else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) + +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(STONEYRIDGE_FWM_POSITION) +apu/amdfw-type := raw + +endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) + +ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) + +cbfs-files-y += smu_fw +cbfs-files-y += smu_fw2 +smu_fw-type := raw +smu_fw2-type := raw + +ifeq ($(CONFIG_SOC_AMD_SMU_FANLESS),y) +smu_fw-file := $(SMUFWM_FN_FILE) +smu_fw2-file := $(SMUFIRMWARE2_FN_FILE) +else ifeq ($(CONFIG_SOC_AMD_SMU_FANNED),y) +smu_fw-file := $(SMUFWM_FILE) +smu_fw2-file := $(SMUFIRMWARE2_FILE) +else +$(error "Proper SMU Firmware not selected") +endif + +endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) + +endif # ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c new file mode 100644 index 0000000000..8a875d9206 --- /dev/null +++ b/src/soc/amd/picasso/mca.c @@ -0,0 +1,214 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +struct mca_bank { + int bank; + msr_t ctl; + msr_t sts; + msr_t addr; + msr_t misc; + msr_t cmask; +}; + +static inline size_t mca_report_size_reqd(void) +{ + size_t size; + + size = sizeof(acpi_generic_error_status_t); + + size += sizeof(acpi_hest_generic_data_v300_t); + size += sizeof(cper_proc_generic_error_section_t); + + size += sizeof(acpi_hest_generic_data_v300_t); + size += sizeof(cper_ia32x64_proc_error_section_t); + + /* Check Error */ + size += cper_ia32x64_check_sz(); + + /* Context of MCG_CAP, MCG_STAT, MCG_CTL */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 3); + + /* Context of MCi_CTL, MCi_STATUS, MCi_ADDR, MCi_MISC */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 4); + + /* Context of CTL_MASK */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 1); + + return size; +} + +static enum cper_x86_check_type error_to_chktype(struct mca_bank *mci) +{ + int error = mca_err_type(mci->sts); + + if (error == MCA_ERRTYPE_BUS) + return X86_PROCESSOR_BUS_CHK; + if (error == MCA_ERRTYPE_INT) + return X86_PROCESSOR_MS_CHK; + if (error == MCA_ERRTYPE_MEM) + return X86_PROCESSOR_CACHE_CHK; + if (error == MCA_ERRTYPE_TLB) + return X86_PROCESSOR_TLB_CHK; + + return X86_PROCESSOR_MS_CHK; /* unrecognized */ +} + +/* Fill additional information in the Generic Processor Error Section. */ +static void fill_generic_section(cper_proc_generic_error_section_t *sec, + struct mca_bank *mci) +{ + int type = mca_err_type(mci->sts); + + if (type == MCA_ERRTYPE_BUS) /* try to map MCA errors to CPER types */ + sec->error_type = GENPROC_ERRTYPE_BUS; + else if (type == MCA_ERRTYPE_INT) + sec->error_type = GENPROC_ERRTYPE_UARCH; + else if (type == MCA_ERRTYPE_MEM) + sec->error_type = GENPROC_ERRTYPE_CACHE; + else if (type == MCA_ERRTYPE_TLB) + sec->error_type = GENPROC_ERRTYPE_TLB; + else + sec->error_type = GENPROC_ERRTYPE_UNKNOWN; + sec->validation |= GENPROC_VALID_PROC_ERR_TYPE; +} + +/* Convert an error reported by an MCA bank into BERT information to be reported + * by the OS. The ACPI driver doesn't recognize/parse the IA32/X64 structure, + * which is the best method to report MSR context. As a result, add two + * structures: A "processor generic error" that is parsed, and an IA32/X64 one + * to capture complete information. + * + * Future work may attempt to interpret the specific Family 15h error symptoms + * found in the MCA registers. This data could enhance the reporting of the + * Processor Generic section and the failing error/check added to the + * IA32/X64 section. + */ +static void build_bert_mca_error(struct mca_bank *mci) +{ + acpi_generic_error_status_t *status; + acpi_hest_generic_data_v300_t *gen_entry; + acpi_hest_generic_data_v300_t *x86_entry; + cper_proc_generic_error_section_t *gen_sec; + cper_ia32x64_proc_error_section_t *x86_sec; + cper_ia32x64_proc_error_info_t *chk; + cper_ia32x64_context_t *ctx; + + if (mca_report_size_reqd() > bert_storage_remaining()) + goto failed; + + status = bert_new_event(&CPER_SEC_PROC_GENERIC_GUID); + if (!status) + goto failed; + + gen_entry = acpi_hest_generic_data3(status); + gen_sec = section_of_acpientry(gen_sec, gen_entry); + + fill_generic_section(gen_sec, mci); + + x86_entry = bert_append_ia32x64(status); + x86_sec = section_of_acpientry(x86_sec, x86_entry); + + chk = new_cper_ia32x64_check(status, x86_sec, error_to_chktype(mci)); + if (!chk) + goto failed; + + ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); + if (!ctx) + goto failed; + ctx = cper_new_ia32x64_context_msr(status, x86_sec, + IA32_MC0_CTL + (mci->bank * 4), 4); + if (!ctx) + goto failed; + ctx = cper_new_ia32x64_context_msr(status, x86_sec, + MC0_CTL_MASK + mci->bank, 1); + if (!ctx) + goto failed; + + return; + +failed: + /* We're here because of a hardware error, don't break something else */ + printk(BIOS_ERR, "Error: Not enough room in BERT region for Machine Check error\n"); +} + +static const char *const mca_bank_name[] = { + "Load-store unit", + "Instruction fetch unit", + "Combined unit", + "Reserved", + "Northbridge", + "Execution unit", + "Floating point unit" +}; + +void check_mca(void) +{ + int i; + msr_t cap; + struct mca_bank mci; + int num_banks; + + cap = rdmsr(IA32_MCG_CAP); + num_banks = cap.lo & MCA_BANKS_MASK; + + if (is_warm_reset()) { + for (i = 0 ; i < num_banks ; i++) { + if (i == 3) /* Reserved in Family 15h */ + continue; + + mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); + if (mci.sts.hi || mci.sts.lo) { + int core = cpuid_ebx(1) >> 24; + + printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", + core, i, mca_bank_name[i]); + + printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", + i, mci.sts.hi, mci.sts.lo); + mci.addr = rdmsr(MC0_ADDR + (i * 4)); + printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", + i, mci.addr.hi, mci.addr.lo); + mci.misc = rdmsr(MC0_MISC + (i * 4)); + printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", + i, mci.misc.hi, mci.misc.lo); + mci.ctl = rdmsr(IA32_MC0_CTL + (i * 4)); + printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", + i, mci.ctl.hi, mci.ctl.lo); + mci.cmask = rdmsr(MC0_CTL_MASK + i); + printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", + i, mci.cmask.hi, mci.cmask.lo); + + mci.bank = i; + if (CONFIG(ACPI_BERT) + && mca_valid(mci.sts)) + build_bert_mca_error(&mci); + } + } + } + + /* zero the machine check error status registers */ + mci.sts.lo = 0; + mci.sts.hi = 0; + for (i = 0 ; i < num_banks ; i++) + wrmsr(IA32_MC0_STATUS + (i * 4), mci.sts); +} diff --git a/src/soc/amd/picasso/monotonic_timer.c b/src/soc/amd/picasso/monotonic_timer.c new file mode 100644 index 0000000000..7ea571f635 --- /dev/null +++ b/src/soc/amd/picasso/monotonic_timer.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#define CU_PTSC_MSR 0xc0010280 +#define PTSC_FREQ_MHZ 100 + +void timer_monotonic_get(struct mono_time *mt) +{ + mono_time_set_usecs(mt, timestamp_get()); +} + +uint64_t timestamp_get(void) +{ + unsigned long long val; + msr_t msr; + + msr = rdmsr(CU_PTSC_MSR); + + val = ((unsigned long long)msr.hi << 32) | msr.lo; + + return val / PTSC_FREQ_MHZ; +} diff --git a/src/soc/amd/picasso/nb_util.c b/src/soc/amd/picasso/nb_util.c new file mode 100644 index 0000000000..d5de067814 --- /dev/null +++ b/src/soc/amd/picasso/nb_util.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +uint32_t nb_ioapic_read(unsigned int index) +{ + pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); + return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA); +} + +void nb_ioapic_write(unsigned int index, uint32_t value) +{ + pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); + pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value); +} + +void *get_ap_entry_ptr(void) +{ + return (void *)nb_ioapic_read(AP_SCRATCH_REG); +} + +void set_ap_entry_ptr(void *entry) +{ + nb_ioapic_write(AP_SCRATCH_REG, (uintptr_t)entry); +} diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c new file mode 100644 index 0000000000..5985832c81 --- /dev/null +++ b/src/soc/amd/picasso/northbridge.c @@ -0,0 +1,492 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max) +{ + u32 tempreg; + + /* io range allocation. Limit */ + tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) + | ((io_max & 0xf0) << (12 - 4)); + pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); + tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */ + pci_write_config32(SOC_ADDR_DEV, reg, tempreg); +} + +static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 mmio_min, u32 mmio_max) +{ + u32 tempreg; + + /* io range allocation. Limit */ + tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); + pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); + tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); + pci_write_config32(SOC_ADDR_DEV, reg, tempreg); +} + +static void read_resources(struct device *dev) +{ + struct resource *res; + + /* + * This MMCONF resource must be reserved in the PCI domain. + * It is not honored by the coreboot resource allocator if it is in + * the CPU_CLUSTER. + */ + mmconf_resource(dev, MMIO_CONF_BASE); + + /* NB IOAPIC2 resource */ + res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ + res->base = IO_APIC2_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void set_resource(struct device *dev, struct resource *res, u32 nodeid) +{ + resource_t rbase, rend; + unsigned int reg, link_num; + char buf[50]; + + /* Make certain the resource has actually been set */ + if (!(res->flags & IORESOURCE_ASSIGNED)) + return; + + /* If I have already stored this resource don't worry about it */ + if (res->flags & IORESOURCE_STORED) + return; + + /* Only handle PCI memory and IO resources */ + if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + return; + + /* Ensure I am actually looking at a resource of function 1 */ + if ((res->index & 0xffff) < 0x1000) + return; + + /* Get the base address */ + rbase = res->base; + + /* Get the limit (rounded up) */ + rend = resource_end(res); + + /* Get the register and link */ + reg = res->index & 0xfff; /* 4k */ + link_num = IOINDEX_LINK(res->index); + + if (res->flags & IORESOURCE_IO) + set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); + else if (res->flags & IORESOURCE_MEM) + set_mmio_addr_reg(nodeid, link_num, reg, + (res->index >> 24), rbase >> 8, rend >> 8); + + res->flags |= IORESOURCE_STORED; + snprintf(buf, sizeof(buf), " ", + nodeid, link_num); + report_resource_stored(dev, res, buf); +} + +/** + * I tried to reuse the resource allocation code in set_resource() + * but it is too difficult to deal with the resource allocation magic. + */ + +static void create_vga_resource(struct device *dev) +{ + struct bus *link; + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = dev->link_list ; link ; link = link->next) + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) + break; + + /* no VGA card installed */ + if (link == NULL) + return; + + printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev)); + /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */ + pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); +} + +static void set_resources(struct device *dev) +{ + struct bus *bus; + struct resource *res; + + + /* do we need this? */ + create_vga_resource(dev); + + /* Set each resource we have found */ + for (res = dev->resource_list ; res ; res = res->next) + set_resource(dev, res, 0); + + for (bus = dev->link_list ; bus ; bus = bus->next) + if (bus->children) + assign_resources(bus); +} + +static void northbridge_init(struct device *dev) +{ + setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, + 0, + 0, + CONFIG_MMCONF_BUS_NUMBER); + + return current; +} + +static unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, + (void *)((u32)addr + 2), *(uint16_t *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, + (void *)((u32)addr + 2), *(uint16_t *)addr - 2); + + return (unsigned long)current; +} + +static void northbridge_fill_ssdt_generator(struct device *device) +{ + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_pop_len(); +} + +static unsigned long agesa_write_acpi_tables(struct device *device, + unsigned long current, + acpi_rsdp_t *rsdp) +{ + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *alib; + acpi_header_t *ivrs; + acpi_hest_t *hest; + acpi_bert_t *bert; + + /* HEST */ + current = ALIGN(current, 8); + hest = (acpi_hest_t *)current; + acpi_write_hest(hest, acpi_fill_hest); + acpi_add_table(rsdp, (void *)current); + current += hest->header.length; + + /* BERT */ + if (CONFIG(ACPI_BERT) && bert_errors_present()) { + /* Skip the table if no errors are present. ACPI driver reports + * a table with a 0-length region: + * BERT: [Firmware Bug]: table invalid. + */ + void *rgn; + size_t size; + bert_errors_region(&rgn, &size); + if (!rgn) { + printk(BIOS_ERR, "Error: Can't find BERT storage area\n"); + } else { + current = ALIGN(current, 8); + bert = (acpi_bert_t *)current; + acpi_write_bert(bert, (uintptr_t)rgn, size); + acpi_add_table(rsdp, (void *)current); + current += bert->header.length; + } + } + + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = agesawrapper_getlateinitptr(PICK_IVRS); + if (ivrs != NULL) { + memcpy((void *)current, ivrs, ivrs->length); + ivrs = (acpi_header_t *)current; + current += ivrs->length; + acpi_add_table(rsdp, ivrs); + } else { + printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); + } + + /* SRAT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *)current; + current += srat->header.length; + acpi_add_table(rsdp, srat); + } else { + printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); + } + + /* SLIT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *)current; + current += slit->header.length; + acpi_add_table(rsdp, slit); + } else { + printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); + } + + /* ALIB */ + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + alib = (acpi_header_t *)current; + current += alib->length; + acpi_add_table(rsdp, (void *)alib); + } else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL." + " Skipping.\n"); + } + + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *)current; + current += ssdt->length; + } else { + printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); + } + acpi_add_table(rsdp, ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + return current; +} + +static struct device_operations northbridge_operations = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, + .write_acpi_tables = agesa_write_acpi_tables, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver family15_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT, +}; + +/* + * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET, + * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining + * MMIO to posted. Route all I/O to the southbridge. + */ +void amd_initcpuio(void) +{ + uintptr_t topmem = bsp_topmem(); + uintptr_t base, limit; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); + + /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */ + base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE; + limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP; + pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit); + pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base); + + /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */ + base = (topmem >> 8) | MMIO_WE | MMIO_RE; + limit = ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8; + pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(1), limit); + pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(1), base); + + /* Route all I/O downstream */ + base = 0 | IO_WE | IO_RE; + limit = ALIGN_DOWN(0xffff, 4 * KiB); + pci_write_config32(SOC_ADDR_DEV, NB_IO_LIMIT(0), limit); + pci_write_config32(SOC_ADDR_DEV, NB_IO_BASE(0), base); +} + +void fam15_finalize(void *chip_info) +{ + u32 value; + + /* TODO: move IOAPIC code to dsdt.asl */ + pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, 0); + pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, 5); + + /* disable No Snoop */ + value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS); + value &= ~HDA_NO_SNOOP_EN; + pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value); +} + +void domain_enable_resources(struct device *dev) +{ + /* Must be called after PCI enumeration and resource allocation */ + if (!romstage_handoff_is_resume()) + do_agesawrapper(AMD_INIT_MID, "amdinitmid"); +} + +void domain_set_resources(struct device *dev) +{ + uint64_t uma_base = get_uma_base(); + uint32_t uma_size = get_uma_size(); + uint32_t mem_useable = (uintptr_t)cbmem_top(); + msr_t tom = rdmsr(TOP_MEM); + msr_t high_tom = rdmsr(TOP_MEM2); + uint64_t high_mem_useable; + int idx = 0x10; + + /* 0x0 -> 0x9ffff */ + ram_resource(dev, idx++, 0, 0xa0000 / KiB); + + /* 0xa0000 -> 0xbffff: legacy VGA */ + mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); + + /* 0xc0000 -> 0xfffff: Option ROM */ + reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); + + /* + * 0x100000 (1MiB) -> low top useable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_resource(dev, idx++, (1 * MiB) / KiB, + (mem_useable - (1 * MiB)) / KiB); + + /* Low top useable RAM -> Low top RAM (bottom pci mmio hole) */ + reserved_ram_resource(dev, idx++, mem_useable / KiB, + (tom.lo - mem_useable) / KiB); + + /* If there is memory above 4GiB */ + if (high_tom.hi) { + /* 4GiB -> high top useable */ + if (uma_base >= (4ull * GiB)) + high_mem_useable = uma_base; + else + high_mem_useable = ((uint64_t)high_tom.lo | + ((uint64_t)high_tom.hi << 32)); + + ram_resource(dev, idx++, (4ull * GiB) / KiB, + ((high_mem_useable - (4ull * GiB)) / KiB)); + + /* High top useable RAM -> high top RAM */ + if (uma_base >= (4ull * GiB)) { + reserved_ram_resource(dev, idx++, uma_base / KiB, + uma_size / KiB); + } + } + + assign_resources(dev->link_list); +} + +/********************************************************************* + * Change the vendor / device IDs to match the generic VBIOS header. * + *********************************************************************/ +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev; + new_vendev = + ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) ? + 0x100298e0 : vendev; + + if (vendev != new_vendev) + printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", + vendev, new_vendev); + + return new_vendev; +} + +__weak void set_board_env_params(GNB_ENV_CONFIGURATION *params) { } + +void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) +{ + const struct device *dev = SOC_IOMMU_DEV; + params->IommuSupport = dev && dev->enabled; + set_board_env_params(params); +} + +void SetNbMidParams(GNB_MID_CONFIGURATION *params) +{ + /* 0=Primary and decode all VGA resources, 1=Secondary - decode none */ + params->iGpuVgaMode = 0; + params->GnbIoapicAddress = IO_APIC2_ADDR; +} diff --git a/src/soc/amd/picasso/pmutil.c b/src/soc/amd/picasso/pmutil.c new file mode 100644 index 0000000000..59de34890f --- /dev/null +++ b/src/soc/amd/picasso/pmutil.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +int vbnv_cmos_failed(void) +{ + /* If CMOS power has failed, the century will be set to 0xff */ + return cmos_read(RTC_CLK_ALTCENTURY) == 0xff; +} diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c new file mode 100644 index 0000000000..7c855bb1e1 --- /dev/null +++ b/src/soc/amd/picasso/ramtop.c @@ -0,0 +1,151 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void backup_top_of_low_cacheable(uintptr_t ramtop) +{ + biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); +} + +uintptr_t restore_top_of_low_cacheable(void) +{ + return biosram_read32(BIOSRAM_CBMEM_TOP); +} + +#if CONFIG(ACPI_BERT) + #if CONFIG_SMM_TSEG_SIZE == 0x0 + #define BERT_REGION_MAX_SIZE 0x100000 + #else + /* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */ + #define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE + #endif +#else + #define BERT_REGION_MAX_SIZE 0 +#endif + +void bert_reserved_region(void **start, size_t *size) +{ + if (CONFIG(ACPI_BERT)) + *start = cbmem_top(); + else + start = NULL; + *size = BERT_REGION_MAX_SIZE; +} + +void *cbmem_top(void) +{ + msr_t tom = rdmsr(TOP_MEM); + + if (!tom.lo) + return 0; + + /* 8MB alignment to keep MTRR usage low */ + return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() + - CONFIG_SMM_TSEG_SIZE + - BERT_REGION_MAX_SIZE, 8*MiB); +} + +static uintptr_t smm_region_start(void) +{ + return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; +} + +static size_t smm_region_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; +} + +void stage_cache_external_region(void **base, size_t *size) +{ + if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { + printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); + *base = NULL; + *size = 0; + } +} + +void smm_region_info(void **start, size_t *size) +{ + *start = (void *)smm_region_start(); + *size = smm_region_size(); +} + +/* + * For data stored in TSEG, ensure TValid is clear so R/W access can reach + * the DRAM when not in SMM. + */ +static void clear_tvalid(void) +{ + msr_t hwcr = rdmsr(HWCR_MSR); + msr_t mask = rdmsr(SMM_MASK_MSR); + int tvalid = !!(mask.lo & SMM_TSEG_VALID); + + if (hwcr.lo & SMM_LOCK) { + if (!tvalid) /* not valid but locked means still accessible */ + return; + + printk(BIOS_ERR, "Error: can't clear TValid, already locked\n"); + return; + } + + mask.lo &= ~SMM_TSEG_VALID; + wrmsr(SMM_MASK_MSR, mask); +} + +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + sub_base = smm_region_start(); + sub_size = smm_region_size(); + + assert(sub_size > CONFIG_SMM_RESERVED_SIZE); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + clear_tvalid(); + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c new file mode 100644 index 0000000000..ec5ee910d9 --- /dev/null +++ b/src/soc/amd/picasso/reset.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +void set_warm_reset_flag(void) +{ + u32 htic; + htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL); + htic |= HTIC_COLD_RST_DET; + pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic); +} + +int is_warm_reset(void) +{ + u32 htic; + htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL); + return !!(htic & HTIC_COLD_RST_DET); +} + +/* Clear bits 5, 9 & 10, used to signal the reset type */ +static void clear_bios_reset(void) +{ + u32 htic; + htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_DETECT; + pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic); +} + +void do_cold_reset(void) +{ + clear_bios_reset(); + + /* De-assert and then assert all PwrGood signals on CF9 reset. */ + pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | + TOGGLE_ALL_PWR_GOOD); + outb(RST_CMD | SYS_RST, SYS_RESET); +} + +void do_warm_reset(void) +{ + set_warm_reset_flag(); + clear_bios_reset(); + + /* Assert reset signals only. */ + outb(RST_CMD | SYS_RST, SYS_RESET); +} + +void do_board_reset(void) +{ + /* TODO: Would a warm_reset() suffice? */ + do_cold_reset(); +} diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c new file mode 100644 index 0000000000..12ee2a8aca --- /dev/null +++ b/src/soc/amd/picasso/romstage.c @@ -0,0 +1,247 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +void __weak mainboard_romstage_entry(int s3_resume) +{ + /* By default, don't do anything */ +} + +static void load_smu_fw1(void) +{ + u32 base, limit, cmd; + + /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ + base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; + limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); + pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit); + pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base); + + /* Preload a value into "BAR3" and enable it */ + pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); + pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); + + /* Enable memory access and master */ + cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); + cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); + + psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); +} + +static void agesa_call(void) +{ + post_code(0x37); + do_agesawrapper(AMD_INIT_RESET, "amdinitreset"); + + post_code(0x38); + /* APs will not exit amdinitearly */ + do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); +} + +static void bsp_agesa_call(void) +{ + set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */ + agesa_call(); +} + +asmlinkage void car_stage_entry(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + void *smm_base; + size_t smm_size; + uintptr_t tseg_base; + msr_t base, mask; + msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); + int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; + int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); + int i; + + console_init(); + + if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) + load_smu_fw1(); + + mainboard_romstage_entry(s3_resume); + + bsp_agesa_call(); + + if (!s3_resume) { + post_code(0x40); + do_agesawrapper(AMD_INIT_POST, "amdinitpost"); + + post_code(0x41); + /* + * TODO: This is a hack to work around current AGESA behavior. + * AGESA needs to change to reflect that coreboot owns + * the MTRRs. + * + * After setting up DRAM, AGESA also completes the configuration + * of the MTRRs, setting regions to WB. Anything written to + * memory between now and and when CAR is dismantled will be + * in cache and lost. For now, set the regions UC to ensure + * the writes get to DRAM. + */ + for (i = 0 ; i < vmtrrs ; i++) { + base = rdmsr(MTRR_PHYS_BASE(i)); + mask = rdmsr(MTRR_PHYS_MASK(i)); + if (!(mask.lo & MTRR_PHYS_MASK_VALID)) + continue; + + if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) { + base.lo &= ~0x7; + base.lo |= MTRR_TYPE_UNCACHEABLE; + wrmsr(MTRR_PHYS_BASE(i), base); + } + } + /* Disable WB from to region 4GB-TOM2. */ + msr_t sys_cfg = rdmsr(SYSCFG_MSR); + sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; + wrmsr(SYSCFG_MSR, sys_cfg); + if (CONFIG(ELOG_BOOT_COUNT)) + boot_count_increment(); + } else { + printk(BIOS_INFO, "S3 detected\n"); + post_code(0x60); + do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); + + post_code(0x61); + } + + post_code(0x42); + psp_notify_dram(); + + post_code(0x43); + if (cbmem_recovery(s3_resume)) + printk(BIOS_CRIT, "Failed to recover cbmem\n"); + if (romstage_handoff_init(s3_resume)) + printk(BIOS_ERR, "Failed to set romstage handoff data\n"); + + post_code(0x44); + if (postcar_frame_init(&pcf, 1 * KiB)) + die("Unable to initialize postcar frame.\n"); + + /* + * We need to make sure ramstage will be run cached. At this point exact + * location of ramstage in cbmem is not known. Instruct postcar to cache + * 16 megs under cbmem top which is a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, + MTRR_TYPE_WRBACK); + + /* Cache the memory-mapped boot media. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region_info(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + + post_code(0x45); + run_postcar_phase(&pcf); + + post_code(0x50); /* Should never see this post code. */ +} + +void SetMemParams(AMD_POST_PARAMS *PostParams) +{ + const struct soc_amd_stoneyridge_config *cfg; + const struct device *dev = pcidev_path_on_root(GNB_DEVFN); + + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n"); + /* In case of a BIOS error, only attempt to set UMA. */ + PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? + UMA_AUTO : UMA_NONE; + return; + } + + cfg = dev->chip_info; + + PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset; + + switch (cfg->uma_mode) { + case UMAMODE_NONE: + PostParams->MemConfig.UmaMode = UMA_NONE; + break; + case UMAMODE_SPECIFIED_SIZE: + PostParams->MemConfig.UmaMode = UMA_SPECIFIED; + /* 64 KiB blocks. */ + PostParams->MemConfig.UmaSize = cfg->uma_size / (64 * KiB); + break; + case UMAMODE_AUTO_LEGACY: + PostParams->MemConfig.UmaMode = UMA_AUTO; + PostParams->MemConfig.UmaVersion = UMA_LEGACY; + break; + case UMAMODE_AUTO_NON_LEGACY: + PostParams->MemConfig.UmaMode = UMA_AUTO; + PostParams->MemConfig.UmaVersion = UMA_NON_LEGACY; + break; + } +} + +void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) +{ + const struct soc_amd_stoneyridge_config *cfg; + const struct device *dev = pcidev_path_on_root(GNB_DEVFN); + struct _PLATFORM_CONFIGURATION *platform; + + if (!dev || !dev->chip_info) { + printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree" + " config, STAPM unchanged\n"); + return; + } + cfg = dev->chip_info; + platform = &InitEarly->PlatformConfig; + if ((cfg->stapm_percent) && (cfg->stapm_time_ms) && + (cfg->stapm_power_mw)) { + platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent; + platform->PlatStapmConfig.CfgStapmTimeConstant = + cfg->stapm_time_ms; + platform->PkgPwrLimitDC = cfg->stapm_power_mw; + platform->PkgPwrLimitAC = cfg->stapm_power_mw; + platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled; + } +} diff --git a/src/soc/amd/picasso/sata.c b/src/soc/amd/picasso/sata.c new file mode 100644 index 0000000000..6740698dd2 --- /dev/null +++ b/src/soc/amd/picasso/sata.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +void soc_enable_sata_features(struct device *dev) +{ + u8 *ahci_ptr; + u32 misc_ctl, cap_cfg; + + u32 temp; + + /* unlock the write-protect */ + misc_ctl = pci_read_config32(dev, SATA_MISC_CONTROL_REG); + misc_ctl |= SATA_MISC_SUBCLASS_WREN; + pci_write_config32(dev, SATA_MISC_CONTROL_REG, misc_ctl); + + /* set the SATA AHCI mode to allow port expanders */ + ahci_ptr = (u8 *)(uintptr_t)ALIGN_DOWN( + pci_read_config32(dev, PCI_BASE_ADDRESS_5), 256); + + cap_cfg = read32(ahci_ptr + SATA_CAPABILITIES_REG); + cap_cfg |= SATA_CAPABILITY_SPM; + write32(ahci_ptr + SATA_CAPABILITIES_REG, cap_cfg); + + /* lock the write-protect */ + temp = pci_read_config32(dev, SATA_MISC_CONTROL_REG); + temp &= ~SATA_MISC_SUBCLASS_WREN; + pci_write_config32(dev, SATA_MISC_CONTROL_REG, temp); +}; diff --git a/src/soc/amd/picasso/sm.c b/src/soc/amd/picasso/sm.c new file mode 100644 index 0000000000..803e628320 --- /dev/null +++ b/src/soc/amd/picasso/sm.c @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* +* The southbridge enables all USB controllers by default in SMBUS Control. +* The southbridge enables SATA by default in SMBUS Control. +*/ + +static void sm_init(struct device *dev) +{ + setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); +} + +static u32 get_sm_mmio(struct device *dev) +{ + struct resource *res; + struct bus *pbus; + + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x90); + if (res->base == SMB_BASE_ADDR) + return ACPIMMIO_SMBUS_BASE; + + return ACPIMMIO_ASF_BASE; +} + +static int lsmbus_recv_byte(struct device *dev) +{ + u8 device; + + device = dev->path.i2c.device; + return do_smbus_recv_byte(get_sm_mmio(dev), device); +} + +static int lsmbus_send_byte(struct device *dev, u8 val) +{ + u8 device; + + device = dev->path.i2c.device; + return do_smbus_send_byte(get_sm_mmio(dev), device, val); +} + +static int lsmbus_read_byte(struct device *dev, u8 address) +{ + u8 device; + + device = dev->path.i2c.device; + return do_smbus_read_byte(get_sm_mmio(dev), device, address); +} + +static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) +{ + u8 device; + + device = dev->path.i2c.device; + return do_smbus_write_byte(get_sm_mmio(dev), device, address, val); +} +static struct smbus_bus_operations lops_smbus_bus = { + .recv_byte = lsmbus_recv_byte, + .send_byte = lsmbus_send_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, +}; + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; +static struct device_operations smbus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = pci_dev_enable_resources, + .init = sm_init, + .scan_bus = scan_smbus, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, +}; +static const struct pci_driver smbus_driver __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_CZ_SMBUS, +}; diff --git a/src/soc/amd/picasso/smbus.c b/src/soc/amd/picasso/smbus.c new file mode 100644 index 0000000000..31457f98b8 --- /dev/null +++ b/src/soc/amd/picasso/smbus.c @@ -0,0 +1,191 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +static u8 controller_read8(u32 base, u8 reg) +{ + switch (base) { + case ACPIMMIO_SMBUS_BASE: + return smbus_read8(reg); + case ACPIMMIO_ASF_BASE: + return asf_read8(reg); + default: + printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%x\n", + base); + } + return 0xff; +} + +static void controller_write8(u32 base, u8 reg, u8 val) +{ + switch (base) { + case ACPIMMIO_SMBUS_BASE: + smbus_write8(reg, val); + break; + case ACPIMMIO_ASF_BASE: + asf_write8(reg, val); + break; + default: + printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%x\n", + base); + } +} + +static int smbus_wait_until_ready(u32 mmio) +{ + u32 loops; + loops = SMBUS_TIMEOUT; + do { + u8 val; + val = controller_read8(mmio, SMBHSTSTAT); + val &= SMBHST_STAT_VAL_BITS; + if (val == 0) { /* ready now */ + return 0; + } + controller_write8(mmio, SMBHSTSTAT, val); + } while (--loops); + return -2; /* time out */ +} + +static int smbus_wait_until_done(u32 mmio) +{ + u32 loops; + loops = SMBUS_TIMEOUT; + do { + u8 val; + + val = controller_read8(mmio, SMBHSTSTAT); + val &= SMBHST_STAT_VAL_BITS; /* mask off reserved bits */ + if (val & SMBHST_STAT_ERROR_BITS) + return -5; /* error */ + if (val == SMBHST_STAT_NOERROR) { + controller_write8(mmio, SMBHSTSTAT, val); /* clr sts */ + return 0; + } + } while (--loops); + return -3; /* timeout */ +} + +int do_smbus_recv_byte(u32 mmio, u8 device) +{ + u8 byte; + + if (smbus_wait_until_ready(mmio) < 0) + return -2; /* not ready */ + + /* set the device I'm talking to */ + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); + + byte = controller_read8(mmio, SMBHSTCTRL); + byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ + byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ + controller_write8(mmio, SMBHSTCTRL, byte); + + /* poll for transaction completion */ + if (smbus_wait_until_done(mmio) < 0) + return -3; /* timeout or error */ + + /* read results of transaction */ + byte = controller_read8(mmio, SMBHSTDAT0); + + return byte; +} + +int do_smbus_send_byte(u32 mmio, u8 device, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(mmio) < 0) + return -2; /* not ready */ + + /* set the command... */ + controller_write8(mmio, SMBHSTDAT0, val); + + /* set the device I'm talking to */ + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); + + byte = controller_read8(mmio, SMBHSTCTRL); + byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ + byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ + controller_write8(mmio, SMBHSTCTRL, byte); + + /* poll for transaction completion */ + if (smbus_wait_until_done(mmio) < 0) + return -3; /* timeout or error */ + + return 0; +} + +int do_smbus_read_byte(u32 mmio, u8 device, u8 address) +{ + u8 byte; + + if (smbus_wait_until_ready(mmio) < 0) + return -2; /* not ready */ + + /* set the command/address... */ + controller_write8(mmio, SMBHSTCMD, address & 0xff); + + /* set the device I'm talking to */ + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); + + byte = controller_read8(mmio, SMBHSTCTRL); + byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ + byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ + controller_write8(mmio, SMBHSTCTRL, byte); + + /* poll for transaction completion */ + if (smbus_wait_until_done(mmio) < 0) + return -3; /* timeout or error */ + + /* read results of transaction */ + byte = controller_read8(mmio, SMBHSTDAT0); + + return byte; +} + +int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(mmio) < 0) + return -2; /* not ready */ + + /* set the command/address... */ + controller_write8(mmio, SMBHSTCMD, address & 0xff); + + /* set the device I'm talking to */ + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); + + /* output value */ + controller_write8(mmio, SMBHSTDAT0, val); + + byte = controller_read8(mmio, SMBHSTCTRL); + byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ + byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ + controller_write8(mmio, SMBHSTCTRL, byte); + + /* poll for transaction completion */ + if (smbus_wait_until_done(mmio) < 0) + return -3; /* timeout or error */ + + return 0; +} diff --git a/src/soc/amd/picasso/smbus_spd.c b/src/soc/amd/picasso/smbus_spd.c new file mode 100644 index 0000000000..e57ecde578 --- /dev/null +++ b/src/soc/amd/picasso/smbus_spd.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * readspd - Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. + */ +static int readspd(uint8_t SmbusSlaveAddress, char *buffer, size_t count) +{ + uint8_t dev_addr; + size_t index; + int error; + char *pbuf = buffer; + + printk(BIOS_SPEW, "-------------READING SPD-----------\n"); + printk(BIOS_SPEW, "SmbusSlave: 0x%08X, count: %zd\n", + SmbusSlaveAddress, count); + + /* + * Convert received device address to the format accepted by + * do_smbus_read_byte and do_smbus_recv_byte. + */ + dev_addr = (SmbusSlaveAddress >> 1); + + /* Read the first SPD byte */ + error = do_smbus_read_byte(ACPIMMIO_SMBUS_BASE, dev_addr, 0); + if (error < 0) { + printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); + return error; + } + *pbuf = (char) error; + pbuf++; + + /* Read the remaining SPD bytes using do_smbus_recv_byte for speed */ + for (index = 1 ; index < count ; index++) { + error = do_smbus_recv_byte(ACPIMMIO_SMBUS_BASE, dev_addr); + if (error < 0) { + printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); + return error; + } + *pbuf = (char) error; + pbuf++; + } + printk(BIOS_SPEW, "\n"); + printk(BIOS_SPEW, "-------------FINISHED READING SPD-----------\n"); + + return 0; +} + +int sb_read_spd(uint8_t spdAddress, char *buf, size_t len) +{ + return readspd(spdAddress, buf, len); +} diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c new file mode 100644 index 0000000000..4a0d833c7b --- /dev/null +++ b/src/soc/amd/picasso/smi.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Alexandru Gagniuc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Utilities for SMM setup + */ + +#include +#include +#include +#include + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1) +{ + printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); +} + +/** Set the EOS bit and enable SMI generation from southbridge */ +void enable_smi_generation(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ + reg |= SMITRG0_EOS; /* Set EOS bit */ + smi_write32(SMI_REG_SMITRIG0, reg); +} diff --git a/src/soc/amd/picasso/smi_util.c b/src/soc/amd/picasso/smi_util.c new file mode 100644 index 0000000000..8759e2acb1 --- /dev/null +++ b/src/soc/amd/picasso/smi_util.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Alexandru Gagniuc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * SMM utilities used in both SMM and normal mode + */ + +#include +#include +#include +#include + +void configure_smi(uint8_t smi_num, uint8_t mode) +{ + uint8_t reg32_offset, bit_offset; + uint32_t reg32; + + if (smi_num >= NUMBER_SMITYPES) { + printk(BIOS_WARNING, "BUG: Invalid SMI: %u\n", smi_num); + return; + } + + /* 16 sources per register, 2 bits per source; registers are 4 bytes */ + reg32_offset = (smi_num / 16) * 4; + bit_offset = (smi_num % 16) * 2; + + reg32 = smi_read32(SMI_REG_CONTROL0 + reg32_offset); + reg32 &= ~(0x3 << (bit_offset)); + reg32 |= (mode & 0x3) << bit_offset; + smi_write32(SMI_REG_CONTROL0 + reg32_offset, reg32); +} + +/** + * Configure generation of interrupts for given GEVENT pin + * + * @param gevent The GEVENT pin number. Valid values are 0 thru 23 + * @param mode The type of event this pin should generate. Note that only + * SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events. + * @param level SMI__SCI_LVL_LOW or SMI_SCI_LVL_HIGH + */ +void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) +{ + uint32_t reg32; + /* GEVENT pins range from [0:23] */ + if (gevent >= SMI_GEVENTS) { + printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); + return; + } + + /* SMI0 source is GEVENT0 and so on */ + configure_smi(gevent, mode); + + /* And set set the trigger level */ + reg32 = smi_read32(SMI_REG_SMITRIG0); + reg32 &= ~(1 << gevent); + reg32 |= (level & 0x1) << gevent; + smi_write32(SMI_REG_SMITRIG0, reg32); +} + +/** + * Configure generation of SCIs. + */ +void configure_scimap(const struct sci_source *sci) +{ + uint32_t reg32; + + /* GEVENT pins range */ + if (sci->scimap >= SCIMAPS) { + printk(BIOS_WARNING, "BUG: Invalid SCIMAP: %u\n", + sci->scimap); + return; + } + + /* GPEs range from [0:31] */ + if (sci->gpe >= SCI_GPES) { + printk(BIOS_WARNING, "BUG: Invalid SCI GPE: %u\n", sci->gpe); + return; + } + + printk(BIOS_DEBUG, "SCIMAP %u maps to GPE %u (active %s, %s trigger)\n", + sci->scimap, sci->gpe, + (!!sci->direction) ? "high" : "low", + (!!sci->level) ? "level" : "edge"); + + /* Map Gevent to SCI GPE# */ + smi_write8(SMI_SCI_MAP(sci->scimap), sci->gpe); + + /* Set the trigger direction (high/low) */ + reg32 = smi_read32(SMI_SCI_TRIG); + reg32 &= ~(1 << sci->gpe); + reg32 |= !!sci->direction << sci->gpe; + smi_write32(SMI_SCI_TRIG, reg32); + + /* Set the trigger level (edge/level) */ + reg32 = smi_read32(SMI_SCI_LEVEL); + reg32 &= ~(1 << sci->gpe); + reg32 |= !!sci->level << sci->gpe; + smi_write32(SMI_SCI_LEVEL, reg32); +} + +void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes) +{ + size_t i; + + for (i = 0; i < num_gpes; i++) + configure_scimap(scis + i); +} + +/** Disable events from given GEVENT pin */ +void disable_gevent_smi(uint8_t gevent) +{ + /* GEVENT pins range from [0:23] */ + if (gevent > 23) { + printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); + return; + } + + /* SMI0 source is GEVENT0 and so on */ + configure_smi(gevent, SMI_MODE_DISABLE); +} + +uint16_t pm_acpi_smi_cmd_port(void) +{ + return pm_read16(PM_ACPI_SMI_CMD); +} diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c new file mode 100644 index 0000000000..d8438bb366 --- /dev/null +++ b/src/soc/amd/picasso/smihandler.c @@ -0,0 +1,287 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Alexandru Gagniuc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* bits in smm_io_trap */ +#define SMM_IO_TRAP_PORT_OFFSET 16 +#define SMM_IO_TRAP_PORT_ADDRESS_MASK 0xffff +#define SMM_IO_TRAP_RW (1 << 0) +#define SMM_IO_TRAP_VALID (1 << 1) + +static inline u16 get_io_address(u32 info) +{ + return ((info >> SMM_IO_TRAP_PORT_OFFSET) & + SMM_IO_TRAP_PORT_ADDRESS_MASK); +} + +static void *find_save_state(int cmd) +{ + int core; + amd64_smm_state_save_area_t *state; + u32 smm_io_trap; + u8 reg_al; + + /* Check all nodes looking for the one that issued the IO */ + for (core = 0; core < CONFIG_MAX_CPUS; core++) { + state = smm_get_save_state(core); + smm_io_trap = state->smm_io_trap_offset; + /* Check for Valid IO Trap Word (bit1==1) */ + if (!(smm_io_trap & SMM_IO_TRAP_VALID)) + continue; + /* Make sure it was a write (bit0==0) */ + if (smm_io_trap & SMM_IO_TRAP_RW) + continue; + /* Check for APMC IO port */ + if (pm_acpi_smi_cmd_port() != get_io_address(smm_io_trap)) + continue; + /* Check AL against the requested command */ + reg_al = state->rax; + if (reg_al == cmd) + return state; + } + return NULL; +} + +static void southbridge_smi_gsmi(void) +{ + u8 sub_command; + amd64_smm_state_save_area_t *io_smi; + u32 reg_ebx; + + io_smi = find_save_state(APM_CNT_ELOG_GSMI); + if (!io_smi) + return; + /* Command and return value in EAX */ + sub_command = (io_smi->rax >> 8) & 0xff; + + /* Parameter buffer in EBX */ + reg_ebx = io_smi->rbx; + + /* drivers/elog/gsmi.c */ + io_smi->rax = gsmi_exec(sub_command, ®_ebx); +} + +static void sb_apmc_smi_handler(void) +{ + const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); + + switch (cmd) { + case APM_CNT_ACPI_ENABLE: + acpi_enable_sci(); + break; + case APM_CNT_ACPI_DISABLE: + acpi_disable_sci(); + break; + case APM_CNT_ELOG_GSMI: + if (CONFIG(ELOG_GSMI)) + southbridge_smi_gsmi(); + break; + } + + mainboard_smi_apmc(cmd); +} + +static void disable_all_smi_status(void) +{ + smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS)); + smi_write32(SMI_EVENT_STATUS, smi_read32(SMI_EVENT_STATUS)); + smi_write32(SMI_REG_SMISTS0, smi_read32(SMI_REG_SMISTS0)); + smi_write32(SMI_REG_SMISTS1, smi_read32(SMI_REG_SMISTS1)); + smi_write32(SMI_REG_SMISTS2, smi_read32(SMI_REG_SMISTS2)); + smi_write32(SMI_REG_SMISTS3, smi_read32(SMI_REG_SMISTS3)); + smi_write32(SMI_REG_SMISTS4, smi_read32(SMI_REG_SMISTS4)); +} + +static void sb_slp_typ_handler(void) +{ + uint32_t pci_ctrl, reg32; + uint16_t pm1cnt, reg16; + uint8_t slp_typ, rst_ctrl; + + /* Figure out SLP_TYP */ + pm1cnt = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); + printk(BIOS_SPEW, "SMI#: SLP = 0x%04x\n", pm1cnt); + slp_typ = acpi_sleep_from_pm1(pm1cnt); + + /* Do any mainboard sleep handling */ + mainboard_smi_sleep(slp_typ); + + switch (slp_typ) { + case ACPI_S0: + printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); + break; + case ACPI_S3: + printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); + break; + case ACPI_S4: + printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); + break; + case ACPI_S5: + printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + break; + default: + printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); + break; + } + + if (slp_typ >= ACPI_S3) { + /* Sleep Type Elog S3, S4, and S5 entry */ + if (CONFIG(ELOG_GSMI)) + elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); + + wbinvd(); + + disable_all_smi_status(); + + /* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */ + pci_ctrl = pm_read32(PM_PCI_CTRL); + pci_ctrl &= ~FORCE_SLPSTATE_RETRY; + pci_ctrl |= FORCE_STPCLK_RETRY; + pm_write32(PM_PCI_CTRL, pci_ctrl); + + /* Enable SlpTyp */ + rst_ctrl = pm_read8(PM_RST_CTRL1); + rst_ctrl |= SLPTYPE_CONTROL_EN; + pm_write8(PM_RST_CTRL1, rst_ctrl); + + /* + * Before the final command, check if there's pending wake + * event. Read enable first, so that reading the actual status + * is as close as possible to entering S3. The idea is to + * minimize the opportunity for a wake event to happen before + * actually entering S3. If there's a pending wake event, log + * it and continue normal path. S3 will fail and the wake event + * becomes a SCI. + */ + if (CONFIG(ELOG_GSMI)) { + reg16 = acpi_read16(MMIO_ACPI_PM1_EN); + reg16 &= acpi_read16(MMIO_ACPI_PM1_STS); + if (reg16) + elog_add_extended_event( + ELOG_SLEEP_PENDING_PM1_WAKE, + (u32)reg16); + + reg32 = acpi_read32(MMIO_ACPI_GPE0_EN); + reg32 &= acpi_read32(MMIO_ACPI_GPE0_STS); + if (reg32) + elog_add_extended_event( + ELOG_SLEEP_PENDING_GPE0_WAKE, + reg32); + } /* if (CONFIG(ELOG_GSMI)) */ + + /* + * An IO cycle is required to trigger the STPCLK/STPGNT + * handshake when the Pm1 write is reissued. + */ + outw(pm1cnt | SLP_EN, pm_read16(PM1_CNT_BLK)); + hlt(); + } +} + +int southbridge_io_trap_handler(int smif) +{ + return 0; +} + +/* + * Table of functions supported in the SMI handler. Note that SMI source setup + * in southbridge.c is unrelated to this list. + */ +static const struct smi_sources_t smi_sources[] = { + { .type = SMITYPE_SMI_CMD_PORT, .handler = sb_apmc_smi_handler }, + { .type = SMITYPE_SLP_TYP, .handler = sb_slp_typ_handler}, +}; + +static void process_smi_sci(void) +{ + const uint32_t status = smi_read32(SMI_SCI_STATUS); + + /* Clear events to prevent re-entering SMI if event isn't handled */ + smi_write32(SMI_SCI_STATUS, status); +} + +static void *get_source_handler(int source) +{ + int i; + + for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++) + if (smi_sources[i].type == source) + return smi_sources[i].handler; + + return NULL; +} + +static void process_smi_sources(uint32_t reg) +{ + const uint32_t status = smi_read32(reg); + int bit_zero = 32 / sizeof(uint32_t) * (reg - SMI_REG_SMISTS0); + void (*source_handler)(void); + int i; + + for (i = 0 ; i < 32 ; i++) { + if (status & (1 << i)) { + source_handler = get_source_handler(i + bit_zero); + if (source_handler) + source_handler(); + } + } + + if (reg == SMI_REG_SMISTS0) + if (status & GEVENT_MASK) + /* Gevent[23:0] are assumed to be mainboard-specific */ + mainboard_smi_gpi(status & GEVENT_MASK); + + /* Clear all events in this register */ + smi_write32(reg, status); +} + +void southbridge_smi_handler(void) +{ + const uint16_t smi_src = smi_read16(SMI_REG_POINTER); + + if (smi_src & SMI_STATUS_SRC_SCI) + process_smi_sci(); + if (smi_src & SMI_STATUS_SRC_0) + process_smi_sources(SMI_REG_SMISTS0); + if (smi_src & SMI_STATUS_SRC_1) + process_smi_sources(SMI_REG_SMISTS1); + if (smi_src & SMI_STATUS_SRC_2) + process_smi_sources(SMI_REG_SMISTS2); + if (smi_src & SMI_STATUS_SRC_3) + process_smi_sources(SMI_REG_SMISTS3); + if (smi_src & SMI_STATUS_SRC_4) + process_smi_sources(SMI_REG_SMISTS4); +} + +void southbridge_smi_set_eos(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg |= SMITRG0_EOS; + smi_write32(SMI_REG_SMITRIG0, reg); +} diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c new file mode 100644 index 0000000000..45408ead02 --- /dev/null +++ b/src/soc/amd/picasso/southbridge.c @@ -0,0 +1,675 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Table of devices that need their AOAC registers enabled and waited + * upon (usually about .55 milliseconds). Instead of individual delays + * waiting for each device to become available, a single delay will be + * executed. + */ +const static struct stoneyridge_aoac aoac_devs[] = { + { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), + (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, + { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, + { FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 }, + { FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 }, + { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 }, + { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } +}; + +static int is_sata_config(void) +{ + return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) + || (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE)); +} + +static inline int sb_sata_enable(void) +{ + /* True if IDE or AHCI. */ + return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || + (SataAhci == CONFIG_STONEYRIDGE_SATA_MODE); +} + +static inline int sb_ide_enable(void) +{ + /* True if IDE or LEGACY IDE. */ + return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || + (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE); +} + +void SetFchResetParams(FCH_RESET_INTERFACE *params) +{ + const struct device *dev = pcidev_path_on_root(SATA_DEVFN); + params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE); + if (dev && dev->enabled) { + params->SataEnable = sb_sata_enable(); + params->IdeEnable = sb_ide_enable(); + } else { + params->SataEnable = FALSE; + params->IdeEnable = FALSE; + } +} + +void SetFchEnvParams(FCH_INTERFACE *params) +{ + const struct device *dev = pcidev_path_on_root(SATA_DEVFN); + params->AzaliaController = AzEnable; + params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; + if (dev && dev->enabled) { + params->SataEnable = is_sata_config(); + params->IdeEnable = !params->SataEnable; + params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == + SataLegacyIde); + } else { + params->SataEnable = FALSE; + params->IdeEnable = FALSE; + params->SataIdeMode = FALSE; + } +} + +void SetFchMidParams(FCH_INTERFACE *params) +{ + SetFchEnvParams(params); +} + +/* + * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME + * provides a visible association with the index, therefore helping + * maintainability of table. If a new index/name is defined in + * amd_pci_int_defs.h, just add the pair at the end of this table. + * Order is not important. + */ +const static struct irq_idx_name irq_association[] = { + { PIRQ_A, "INTA#" }, + { PIRQ_B, "INTB#" }, + { PIRQ_C, "INTC#" }, + { PIRQ_D, "INTD#" }, + { PIRQ_E, "INTE#" }, + { PIRQ_F, "INTF#" }, + { PIRQ_G, "INTG#" }, + { PIRQ_H, "INTH#" }, + { PIRQ_MISC, "Misc" }, + { PIRQ_MISC0, "Misc0" }, + { PIRQ_MISC1, "Misc1" }, + { PIRQ_MISC2, "Misc2" }, + { PIRQ_SIRQA, "Ser IRQ INTA" }, + { PIRQ_SIRQB, "Ser IRQ INTB" }, + { PIRQ_SIRQC, "Ser IRQ INTC" }, + { PIRQ_SIRQD, "Ser IRQ INTD" }, + { PIRQ_SCI, "SCI" }, + { PIRQ_SMBUS, "SMBUS" }, + { PIRQ_ASF, "ASF" }, + { PIRQ_HDA, "HDA" }, + { PIRQ_FC, "FC" }, + { PIRQ_PMON, "PerMon" }, + { PIRQ_SD, "SD" }, + { PIRQ_SDIO, "SDIOt" }, + { PIRQ_EHCI, "EHCI" }, + { PIRQ_XHCI, "XHCI" }, + { PIRQ_SATA, "SATA" }, + { PIRQ_GPIO, "GPIO" }, + { PIRQ_I2C0, "I2C0" }, + { PIRQ_I2C1, "I2C1" }, + { PIRQ_I2C2, "I2C2" }, + { PIRQ_I2C3, "I2C3" }, + { PIRQ_UART0, "UART0" }, + { PIRQ_UART1, "UART1" }, +}; + +const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) +{ + *size = ARRAY_SIZE(irq_association); + return irq_association; +} + +static void power_on_aoac_device(int aoac_device_control_register) +{ + uint8_t byte; + + /* Power on the UART and AMBA devices */ + byte = aoac_read8(aoac_device_control_register); + byte |= FCH_AOAC_PWR_ON_DEV; + aoac_write8(aoac_device_control_register, byte); +} + +static bool is_aoac_device_enabled(int aoac_device_status_register) +{ + uint8_t byte; + + byte = aoac_read8(aoac_device_status_register); + byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); + if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) + return true; + else + return false; +} + +void enable_aoac_devices(void) +{ + bool status; + int i; + + for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) + power_on_aoac_device(aoac_devs[i].enable); + + /* Wait for AOAC devices to indicate power and clock OK */ + do { + udelay(100); + status = true; + for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) + status &= is_aoac_device_enabled(aoac_devs[i].status); + } while (!status); +} + +static void sb_enable_lpc(void) +{ + u8 byte; + + /* Enable LPC controller */ + byte = pm_io_read8(PM_LPC_GATING); + byte |= PM_LPC_ENABLE; + pm_io_write8(PM_LPC_GATING, byte); +} + +static void sb_lpc_decode(void) +{ + u32 tmp = 0; + + /* Enable I/O decode to LPC bus */ + tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 + | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 + | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 + | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 + | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 + | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 + | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 + | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 + | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 + | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT + | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT + | DECODE_ENABLE_ADLIB_PORT; + + /* Decode SIOs at 2E/2F and 4E/4F */ + if (CONFIG(STONEYRIDGE_LEGACY_FREE)) + tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; + + lpc_enable_decode(tmp); +} + +static void sb_enable_cf9_io(void) +{ + uint32_t reg = pm_read32(PM_DECODE_EN); + + pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); +} + +static void sb_enable_legacy_io(void) +{ + uint32_t reg = pm_read32(PM_DECODE_EN); + + pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); +} + +void sb_clk_output_48Mhz(u32 osc) +{ + u32 ctrl; + + /* + * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) + * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. + */ + ctrl = misc_read32(MISC_CLK_CNTL1); + + switch (osc) { + case 1: + ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; + break; + case 2: + ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB; + break; + default: + return; /* do nothing if invalid */ + } + misc_write32(MISC_CLK_CNTL1, ctrl); +} + +static uintptr_t sb_init_spi_base(void) +{ + uintptr_t base; + + /* Make sure the base address is predictable */ + base = lpc_get_spibase(); + + if (base) + return base; + + lpc_set_spibase(SPI_BASE_ADDRESS, SPI_ROM_ENABLE); + return SPI_BASE_ADDRESS; +} + +void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) +{ + uintptr_t base = sb_init_spi_base(); + write16((void *)(base + SPI100_SPEED_CONFIG), + (norm << SPI_NORM_SPEED_NEW_SH) | + (fast << SPI_FAST_SPEED_NEW_SH) | + (alt << SPI_ALT_SPEED_NEW_SH) | + (tpm << SPI_TPM_SPEED_NEW_SH)); + write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); +} + +void sb_disable_4dw_burst(void) +{ + uintptr_t base = sb_init_spi_base(); + write16((void *)(base + SPI100_HOST_PREF_CONFIG), + read16((void *)(base + SPI100_HOST_PREF_CONFIG)) + & ~SPI_RD4DW_EN_HOST); +} + +void sb_read_mode(u32 mode) +{ + uintptr_t base = sb_init_spi_base(); + write32((void *)(base + SPI_CNTRL0), + (read32((void *)(base + SPI_CNTRL0)) + & ~SPI_READ_MODE_MASK) | mode); +} + +static void setup_spread_spectrum(int *reboot) +{ + uint16_t rstcfg = pm_read16(PWR_RESET_CFG); + + rstcfg &= ~TOGGLE_ALL_PWR_GOOD; + pm_write16(PWR_RESET_CFG, rstcfg); + + uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1); + + if (cntl1 & CG1PLL_FBDIV_TEST) { + printk(BIOS_DEBUG, "Spread spectrum is ready\n"); + misc_write32(MISC_CGPLL_CONFIG1, + misc_read32(MISC_CGPLL_CONFIG1) | + CG1PLL_SPREAD_SPECTRUM_ENABLE); + + return; + } + + printk(BIOS_DEBUG, "Setting up spread spectrum\n"); + + uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6); + cfg6 &= ~CG1PLL_LF_MODE_MASK; + cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK; + misc_write32(MISC_CGPLL_CONFIG6, cfg6); + + uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3); + cfg3 &= ~CG1PLL_REFDIV_MASK; + cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK; + cfg3 &= ~CG1PLL_FBDIV_MASK; + cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK; + misc_write32(MISC_CGPLL_CONFIG3, cfg3); + + uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5); + cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK; + cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK; + misc_write32(MISC_CGPLL_CONFIG5, cfg5); + + uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4); + cfg4 &= ~SS_AMOUNT_DSFRAC_MASK; + cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK; + cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK; + cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT) + & SS_STEP_SIZE_DSFRAC_MASK; + misc_write32(MISC_CGPLL_CONFIG4, cfg4); + + rstcfg |= TOGGLE_ALL_PWR_GOOD; + pm_write16(PWR_RESET_CFG, rstcfg); + + cntl1 |= CG1PLL_FBDIV_TEST; + misc_write32(MISC_CLK_CNTL1, cntl1); + + *reboot = 1; +} + +static void setup_misc(int *reboot) +{ + /* Undocumented register */ + uint32_t reg = misc_read32(0x50); + if (!(reg & BIT(16))) { + reg |= BIT(16); + + misc_write32(0x50, reg); + *reboot = 1; + } +} + +static void fch_smbus_init(void) +{ + pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); + smbus_write8(SMBTIMING, SMB_SPEED_400KHZ); + /* Clear all SMBUS status bits */ + smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); + smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); + asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); + asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); +} + +/* Before console init */ +void bootblock_fch_early_init(void) +{ + int reboot = 0; + + lpc_enable_rom(); + sb_enable_lpc(); + lpc_enable_port80(); + sb_lpc_decode(); + lpc_enable_spi_prefetch(); + sb_init_spi_base(); + sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ + enable_acpimmio_decode(); + fch_smbus_init(); + sb_enable_cf9_io(); + setup_spread_spectrum(&reboot); + setup_misc(&reboot); + + if (reboot) + warm_reset(); + + sb_enable_legacy_io(); + enable_aoac_devices(); +} + +static void print_num_status_bits(int num_bits, uint32_t status, + const char *const bit_names[]) +{ + int i; + + if (!status) + return; + + for (i = num_bits - 1; i >= 0; i--) { + if (status & (1 << i)) { + if (bit_names[i]) + printk(BIOS_DEBUG, "%s ", bit_names[i]); + else + printk(BIOS_DEBUG, "BIT%d ", i); + } + } +} + +static void sb_print_pmxc0_status(void) +{ + /* PMxC0 S5/Reset Status shows the source of previous reset. */ + uint32_t pmxc0_status = pm_read32(PM_RST_STATUS); + + static const char *const pmxc0_status_bits[32] = { + [0] = "ThermalTrip", + [1] = "FourSecondPwrBtn", + [2] = "Shutdown", + [3] = "ThermalTripFromTemp", + [4] = "RemotePowerDownFromASF", + [5] = "ShutDownFan0", + [16] = "UserRst", + [17] = "SoftPciRst", + [18] = "DoInit", + [19] = "DoReset", + [20] = "DoFullReset", + [21] = "SleepReset", + [22] = "KbReset", + [23] = "LtReset", + [24] = "FailBootRst", + [25] = "WatchdogIssueReset", + [26] = "RemoteResetFromASF", + [27] = "SyncFlood", + [28] = "HangReset", + [29] = "EcWatchdogRst", + }; + + printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status); + print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status, + pmxc0_status_bits); + printk(BIOS_DEBUG, "\n"); +} + +/* After console init */ +void bootblock_fch_init(void) +{ + sb_print_pmxc0_status(); +} + +void sb_enable(struct device *dev) +{ + printk(BIOS_DEBUG, "%s\n", __func__); +} + +static void sb_init_acpi_ports(void) +{ + u32 reg; + + /* We use some of these ports in SMM regardless of whether or not + * ACPI tables are generated. Enable these ports indiscriminately. + */ + + pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); + pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); + pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); + pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); + /* CpuControl is in \_PR.CP00, 6 bytes */ + pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); + + if (CONFIG(HAVE_SMI_HANDLER)) { + /* APMC - SMI Command Port */ + pm_write16(PM_ACPI_SMI_CMD, APM_CNT); + configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); + + /* SMI on SlpTyp requires sending SMI before completion + * response of the I/O write. The BKDG also specifies + * clearing ForceStpClkRetry for SMI trapping. + */ + reg = pm_read32(PM_PCI_CTRL); + reg |= FORCE_SLPSTATE_RETRY; + reg &= ~FORCE_STPCLK_RETRY; + pm_write32(PM_PCI_CTRL, reg); + + /* Disable SlpTyp feature */ + reg = pm_read8(PM_RST_CTRL1); + reg &= ~SLPTYPE_CONTROL_EN; + pm_write8(PM_RST_CTRL1, reg); + + configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); + } else { + pm_write16(PM_ACPI_SMI_CMD, 0); + } + + /* Decode ACPI registers and enable standard features */ + pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | + PM_ACPI_GLOBAL_EN | + PM_ACPI_RTC_EN_EN | + PM_ACPI_TIMER_EN_EN); +} + +static int get_index_bit(uint32_t value, uint16_t limit) +{ + uint16_t i; + uint32_t t; + + if (limit >= TOTAL_BITS(uint32_t)) + return -1; + + /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ + t = (1 << limit) - 1; + if ((value & t) == 0) + return -1; + t = 1; + for (i = 0; i < limit; i++) { + if (value & t) + break; + t <<= 1; + } + return i; +} + +static void set_nvs_sws(void *unused) +{ + struct soc_power_reg *sws; + struct global_nvs_t *gnvs; + int index; + + sws = cbmem_find(CBMEM_ID_POWER_STATE); + if (sws == NULL) + return; + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (gnvs == NULL) + return; + + index = get_index_bit(sws->pm1_sts & sws->pm1_en, PM1_LIMIT); + if (index < 0) + gnvs->pm1i = ~0ULL; + else + gnvs->pm1i = index; + + index = get_index_bit(sws->gpe0_sts & sws->gpe0_en, GPE0_LIMIT); + if (index < 0) + gnvs->gpei = ~0ULL; + else + gnvs->gpei = index; +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); + +void southbridge_init(void *chip_info) +{ + sb_init_acpi_ports(); + acpi_clear_pm1_status(); +} + +static void set_sb_final_nvs(void) +{ + uintptr_t amdfw_rom; + uintptr_t xhci_fw; + uintptr_t fwaddr; + size_t fwsize; + const struct device *sd, *sata; + + struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (gnvs == NULL) + return; + + gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); + gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); + gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); + gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); + gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); + gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); + gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2); + gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); + /* Rely on these being in sync with devicetree */ + sd = pcidev_path_on_root(SD_DEVFN); + gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0; + sata = pcidev_path_on_root(SATA_DEVFN); + gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; + gnvs->aoac.espi = 1; + + amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); + xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET)); + + fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET + + XHCI_FW_BOOTRAM_SIZE)); + fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET + + XHCI_FW_BOOTRAM_SIZE)); + gnvs->fw00 = 0; + gnvs->fw01 = ((32 * KiB) << 16) + 0; + gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; + gnvs->fw03 = fwsize << 16; + + gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) + & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; +} + +void southbridge_final(void *chip_info) +{ + uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; + + if (CONFIG(MAINBOARD_POWER_RESTORE)) + restored_power = PM_RESTORE_S0_IF_PREV_S0; + pm_write8(PM_RTC_SHADOW, restored_power); + + set_sb_final_nvs(); +} + +/* + * Update the PCI devices with a valid IRQ number + * that is set in the mainboard PCI_IRQ structures. + */ +static void set_pci_irqs(void *unused) +{ + /* Write PCI_INTR regs 0xC00/0xC01 */ + write_pci_int_table(); + + /* Write IRQs for all devicetree enabled devices */ + write_pci_cfg_irqs(); +} + +/* + * Hook this function into the PCI state machine + * on entry into BS_DEV_ENABLE. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); + +void save_uma_size(uint32_t size) +{ + biosram_write32(BIOSRAM_UMA_SIZE, size); +} + +void save_uma_base(uint64_t base) +{ + biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); + biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); +} + +uint32_t get_uma_size(void) +{ + return biosram_read32(BIOSRAM_UMA_SIZE); +} + +uint64_t get_uma_base(void) +{ + uint64_t base; + base = biosram_read32(BIOSRAM_UMA_BASE); + base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); + return base; +} diff --git a/src/soc/amd/picasso/spi.c b/src/soc/amd/picasso/spi.c new file mode 100644 index 0000000000..8abfa160f4 --- /dev/null +++ b/src/soc/amd/picasso/spi.c @@ -0,0 +1,189 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SPI_DEBUG_DRIVER CONFIG(DEBUG_SPI_FLASH) + +static uintptr_t spibar; + +static void set_spibar(uintptr_t base) +{ + spibar = base; +} + +static inline uint8_t spi_read8(uint8_t reg) +{ + return read8((void *)(spibar + reg)); +} + +static inline uint32_t spi_read32(uint8_t reg) +{ + return read32((void *)(spibar + reg)); +} + +static inline void spi_write8(uint8_t reg, uint8_t val) +{ + write8((void *)(spibar + reg), val); +} + +static inline void spi_write32(uint8_t reg, uint32_t val) +{ + write32((void *)(spibar + reg), val); +} + +static void dump_state(const char *str) +{ + if (!SPI_DEBUG_DRIVER) + return; + + printk(BIOS_DEBUG, "SPI: %s\n", str); + printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0)); + printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS)); + printk(BIOS_DEBUG, "TxByteCount: %x\n", spi_read8(SPI_TX_BYTE_COUNT)); + printk(BIOS_DEBUG, "RxByteCount: %x\n", spi_read8(SPI_RX_BYTE_COUNT)); + printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE)); + hexdump((void *)(spibar + SPI_FIFO), SPI_FIFO_DEPTH); +} + +static int wait_for_ready(void) +{ + const uint32_t timeout_ms = 500; + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, timeout_ms); + + do { + if (!(spi_read32(SPI_STATUS) & SPI_BUSY)) + return 0; + } while (!stopwatch_expired(&sw)); + + return -1; +} + +static int execute_command(void) +{ + dump_state("Before Execute"); + + spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE); + + if (wait_for_ready()) + printk(BIOS_DEBUG, + "FCH SPI Error: Timeout executing command\n"); + + dump_state("Transaction finished"); + + return 0; +} + +void spi_init(void) +{ + set_spibar(lpc_get_spibase()); +} + +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytesout, void *din, size_t bytesin) +{ + size_t count; + uint8_t cmd; + uint8_t *bufin = din; + const uint8_t *bufout = dout; + + if (SPI_DEBUG_DRIVER) + printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout, + bytesin); + + /* First byte is cmd which cannot be sent through FIFO */ + cmd = bufout[0]; + bufout++; + bytesout--; + + /* + * Check if this is a write command attempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (bytesout + bytesin > SPI_FIFO_DEPTH) { + printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI" + " chip driver use spi_crop_chunk()?\n"); + return -1; + } + + if (wait_for_ready()) + return -1; + + spi_write8(SPI_CMD_CODE, cmd); + spi_write8(SPI_TX_BYTE_COUNT, bytesout); + spi_write8(SPI_RX_BYTE_COUNT, bytesin); + + for (count = 0; count < bytesout; count++) + spi_write8(SPI_FIFO + count, bufout[count]); + + if (execute_command()) + return -1; + + for (count = 0; count < bytesin; count++) + bufin[count] = spi_read8(SPI_FIFO + count + bytesout); + + return 0; +} + +int chipset_volatile_group_begin(const struct spi_flash *flash) +{ + return 0; +} + +int chipset_volatile_group_end(const struct spi_flash *flash) +{ + return 0; +} + +static int xfer_vectors(const struct spi_slave *slave, + struct spi_op vectors[], size_t count) +{ + return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); +} + +static const struct spi_ctrlr spi_ctrlr = { + .xfer_vector = xfer_vectors, + .max_xfer_size = SPI_FIFO_DEPTH, + .flags = SPI_CNTRLR_DEDUCT_CMD_LEN | SPI_CNTRLR_DEDUCT_OPCODE_LEN, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = 0, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c new file mode 100644 index 0000000000..29121b955e --- /dev/null +++ b/src/soc/amd/picasso/tsc_freq.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Advanced Micro Devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +unsigned long tsc_freq_mhz(void) +{ + msr_t msr; + uint8_t cpufid; + uint8_t cpudid; + uint8_t boost_states; + + /* + * See the Family 15h Models 70h-7Fh BKDG (PID 55072) definition for + * MSR0000_0010. The TSC increments at the P0 frequency. According + * to the "Software P-state Numbering" section, P0 is the highest + * non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)). + */ + boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) + >> 2) & 0x7; + + msr = rdmsr(PSTATE_0_MSR + boost_states); + if (!(msr.hi & 0x80000000)) + die("Unknown error: cannot determine P-state 0\n"); + + cpufid = (msr.lo & 0x3f); + cpudid = (msr.lo & 0x1c0) >> 6; + + return (100 * (cpufid + 0x10)) / (0x01 << cpudid); +} diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c new file mode 100644 index 0000000000..d5d30061bf --- /dev/null +++ b/src/soc/amd/picasso/uart.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +uintptr_t uart_platform_base(int idx) +{ + if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) + return 0; + + return (uintptr_t)(APU_UART0_BASE + 0x2000 * (idx & 1)); +} + +unsigned int uart_platform_refclk(void) +{ + return 48000000; +} diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c new file mode 100644 index 0000000000..00f82375e8 --- /dev/null +++ b/src/soc/amd/picasso/usb.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void set_usb_over_current(struct device *dev) +{ + uint16_t map = USB_OC_DISABLE_ALL; + + if (dev->path.pci.devfn == XHCI_DEVFN) { + if (mainboard_get_xhci_oc_map(&map) == 0) { + xhci_pm_write32(XHCI_PM_INDIRECT_INDEX, + XHCI_OVER_CURRENT_CONTROL); + xhci_pm_write16(XHCI_PM_INDIRECT_DATA, map); + } + } + + if (dev->path.pci.devfn == EHCI1_DEVFN) { + if (mainboard_get_ehci_oc_map(&map) == 0) + pci_write_config16(dev, EHCI_OVER_CURRENT_CONTROL, map); + } +} + +int __weak mainboard_get_xhci_oc_map(uint16_t *map) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return -1; +} + +int __weak mainboard_get_ehci_oc_map(uint16_t *map) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return -1; +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations usb_ops = { + .read_resources = pci_ehci_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = set_usb_over_current, + .scan_bus = scan_usb_bus, + .acpi_name = soc_acpi_name, + .ops_pci = &lops_pci, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_SB900_USB_18_0, + PCI_DEVICE_ID_AMD_SB900_USB_18_2, + PCI_DEVICE_ID_AMD_SB900_USB_20_5, + PCI_DEVICE_ID_AMD_CZ_USB_0, + PCI_DEVICE_ID_AMD_CZ_USB_1, + PCI_DEVICE_ID_AMD_CZ_USB3_0, + 0 +}; + +static const struct pci_driver usb_0_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_AMD, + .devices = pci_device_ids, +}; From 360035ee5b83ab9a1c4f09f30f207edb103ab51c Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 22 Apr 2019 15:35:17 -0600 Subject: [PATCH 013/231] soc/amd/picasso: Remove ST files not used for PCO Remove files that aren't needed for the picasso port. Remove traces of AGESA v5 (includes binaryPI support files). Remove SPD helper. Picasso (and all AMD Family 17h processors) have a very different boot flow from previous products. Memory is initialized by the PSP before the x86 processor is released from reset. The SPD is read by the PSP, so it's not needed in coreboot. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth Change-Id: I743ffd6058982f8f182ea4d73172a029967f3ea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32408 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel Reviewed-by: Edward O'Callaghan --- src/soc/amd/picasso/BiosCallOuts.c | 166 -------------------------- src/soc/amd/picasso/enable_usbdebug.c | 42 ------- src/soc/amd/picasso/makefile.inc | 13 -- src/soc/amd/picasso/nb_util.c | 40 ------- src/soc/amd/picasso/smbus_spd.c | 76 ------------ 5 files changed, 337 deletions(-) delete mode 100644 src/soc/amd/picasso/BiosCallOuts.c delete mode 100644 src/soc/amd/picasso/enable_usbdebug.c delete mode 100644 src/soc/amd/picasso/nb_util.c delete mode 100644 src/soc/amd/picasso/smbus_spd.c diff --git a/src/soc/amd/picasso/BiosCallOuts.c b/src/soc/amd/picasso/BiosCallOuts.c deleted file mode 100644 index c55e73499a..0000000000 --- a/src/soc/amd/picasso/BiosCallOuts.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011, 2017 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * Copyright (C) 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "chip.h" - -void __weak platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset) {} - -AGESA_STATUS agesa_fch_initreset(uint32_t Func, uintptr_t FchData, - void *ConfigPtr) -{ - AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - - if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams_reset; - FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - - /* Get platform specific configuration changes */ - platform_FchParams_reset(FchParams_reset); - - printk(BIOS_DEBUG, "Done\n"); - } - - return AGESA_SUCCESS; -} - -AGESA_STATUS agesa_fch_initenv(uint32_t Func, uintptr_t FchData, - void *ConfigPtr) -{ - AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - - if (StdHeader->Func == AMD_INIT_ENV) { - FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - - /* XHCI configuration */ - if (CONFIG(STONEYRIDGE_XHCI_ENABLE)) - FchParams_env->Usb.Xhci0Enable = TRUE; - else - FchParams_env->Usb.Xhci0Enable = FALSE; - FchParams_env->Usb.Xhci1Enable = FALSE; - - /* SATA configuration */ - FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE; - if (dev && dev->enabled) { - switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { - case SataRaid: - case SataAhci: - case SataAhci7804: - case SataLegacyIde: - FchParams_env->Sata.SataIdeMode = FALSE; - break; - case SataIde2Ahci: - case SataIde2Ahci7804: - default: /* SataNativeIde */ - FchParams_env->Sata.SataIdeMode = TRUE; - break; - } - } else - FchParams_env->Sata.SataIdeMode = FALSE; - - /* Platform updates */ - platform_FchParams_env(FchParams_env); - - printk(BIOS_DEBUG, "Done\n"); - } - - return AGESA_SUCCESS; -} - -AGESA_STATUS agesa_ReadSpd(uint32_t Func, uintptr_t Data, void *ConfigPtr) -{ - uint8_t spd_address; - int err; - DEVTREE_CONST struct device *dev; - DEVTREE_CONST struct soc_amd_stoneyridge_config *conf; - AGESA_READ_SPD_PARAMS *info = ConfigPtr; - - if (!ENV_ROMSTAGE) - return AGESA_UNSUPPORTED; - - dev = pcidev_path_on_root(DCT_DEVFN); - if (dev == NULL) - return AGESA_ERROR; - - conf = dev->chip_info; - if (conf == NULL) - return AGESA_ERROR; - - if (info->SocketId >= ARRAY_SIZE(conf->spd_addr_lookup)) - return AGESA_ERROR; - if (info->MemChannelId >= ARRAY_SIZE(conf->spd_addr_lookup[0])) - return AGESA_ERROR; - if (info->DimmId >= ARRAY_SIZE(conf->spd_addr_lookup[0][0])) - return AGESA_ERROR; - - spd_address = conf->spd_addr_lookup - [info->SocketId][info->MemChannelId][info->DimmId]; - if (spd_address == 0) - return AGESA_ERROR; - - err = mainboard_read_spd(spd_address, (void *)info->Buffer, - CONFIG_DIMM_SPD_SIZE); - - /* Read the SPD if the mainboard didn't fill the buffer */ - if (err || (*info->Buffer == 0)) - err = sb_read_spd(spd_address, (void *)info->Buffer, - CONFIG_DIMM_SPD_SIZE); - - if (err) - return AGESA_ERROR; - - return AGESA_SUCCESS; -} - -AGESA_STATUS agesa_HaltThisAp(uint32_t Func, uintptr_t Data, void *ConfigPtr) -{ - AGESA_HALT_THIS_AP_PARAMS *info = ConfigPtr; - uint32_t flags = 0; - - if (info->PrimaryCore == TRUE) - return AGESA_UNSUPPORTED; /* force normal path */ - if (info->ExecWbinvd == TRUE) - flags |= 1; - if (info->CacheEn == TRUE) - flags |= 2; - - ap_teardown_car(flags); /* does not return */ - - /* Should never reach here */ - return AGESA_UNSUPPORTED; -} - -/* Allow mainboards to fill the SPD buffer */ -__weak int mainboard_read_spd(uint8_t spdAddress, char *buf, - size_t len) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); - return -1; /* SPD not read */ -} diff --git a/src/soc/amd/picasso/enable_usbdebug.c b/src/soc/amd/picasso/enable_usbdebug.c deleted file mode 100644 index 19b9550847..0000000000 --- a/src/soc/amd/picasso/enable_usbdebug.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include -#include - -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) -{ - pm_io_write8(PM_USB_ENABLE, PM_USB_ALL_CONTROLLERS); - return SOC_EHCI1_DEV; -} - -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) -{ - u32 reg32, value; - - value = (port & 0x3) << DEBUG_PORT_SELECT_SHIFT; - value |= DEBUG_PORT_ENABLE; - reg32 = pci_read_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4); - reg32 &= ~DEBUG_PORT_MASK; - reg32 |= value; - pci_write_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4, reg32); -} diff --git a/src/soc/amd/picasso/makefile.inc b/src/soc/amd/picasso/makefile.inc index babd878524..05529d9a97 100644 --- a/src/soc/amd/picasso/makefile.inc +++ b/src/soc/amd/picasso/makefile.inc @@ -38,35 +38,28 @@ subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c -bootblock-y += BiosCallOuts.c bootblock-y += bootblock/bootblock.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c bootblock-y += monotonic_timer.c bootblock-y += pmutil.c bootblock-y += reset.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c -bootblock-y += nb_util.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c -romstage-y += BiosCallOuts.c romstage-y += i2c.c romstage-y += romstage.c -romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += gpio.c romstage-y += monotonic_timer.c romstage-y += pmutil.c romstage-y += reset.c romstage-y += smbus.c -romstage-y += smbus_spd.c romstage-y += ramtop.c romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c -romstage-y += nb_util.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c @@ -77,22 +70,18 @@ verstage-y += pmutil.c verstage-y += reset.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c -verstage-y += nb_util.c verstage-$(CONFIG_SPI_FLASH) += spi.c postcar-y += monotonic_timer.c postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c postcar-y += ramtop.c -postcar-y += nb_util.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c -ramstage-y += BiosCallOuts.c ramstage-y += i2c.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += mca.c -ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += gpio.c ramstage-y += monotonic_timer.c @@ -111,7 +100,6 @@ ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += finalize.c -ramstage-y += nb_util.c smm-y += monotonic_timer.c smm-y += smihandler.c @@ -119,7 +107,6 @@ smm-y += smi_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c smm-$(CONFIG_SPI_FLASH) += spi.c -smm-y += nb_util.c smm-y += gpio.c CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge diff --git a/src/soc/amd/picasso/nb_util.c b/src/soc/amd/picasso/nb_util.c deleted file mode 100644 index d5de067814..0000000000 --- a/src/soc/amd/picasso/nb_util.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Advanced Micro Devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -uint32_t nb_ioapic_read(unsigned int index) -{ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); - return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA); -} - -void nb_ioapic_write(unsigned int index, uint32_t value) -{ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value); -} - -void *get_ap_entry_ptr(void) -{ - return (void *)nb_ioapic_read(AP_SCRATCH_REG); -} - -void set_ap_entry_ptr(void *entry) -{ - nb_ioapic_write(AP_SCRATCH_REG, (uintptr_t)entry); -} diff --git a/src/soc/amd/picasso/smbus_spd.c b/src/soc/amd/picasso/smbus_spd.c deleted file mode 100644 index e57ecde578..0000000000 --- a/src/soc/amd/picasso/smbus_spd.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -/* - * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. - */ -static int readspd(uint8_t SmbusSlaveAddress, char *buffer, size_t count) -{ - uint8_t dev_addr; - size_t index; - int error; - char *pbuf = buffer; - - printk(BIOS_SPEW, "-------------READING SPD-----------\n"); - printk(BIOS_SPEW, "SmbusSlave: 0x%08X, count: %zd\n", - SmbusSlaveAddress, count); - - /* - * Convert received device address to the format accepted by - * do_smbus_read_byte and do_smbus_recv_byte. - */ - dev_addr = (SmbusSlaveAddress >> 1); - - /* Read the first SPD byte */ - error = do_smbus_read_byte(ACPIMMIO_SMBUS_BASE, dev_addr, 0); - if (error < 0) { - printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); - return error; - } - *pbuf = (char) error; - pbuf++; - - /* Read the remaining SPD bytes using do_smbus_recv_byte for speed */ - for (index = 1 ; index < count ; index++) { - error = do_smbus_recv_byte(ACPIMMIO_SMBUS_BASE, dev_addr); - if (error < 0) { - printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); - return error; - } - *pbuf = (char) error; - pbuf++; - } - printk(BIOS_SPEW, "\n"); - printk(BIOS_SPEW, "-------------FINISHED READING SPD-----------\n"); - - return 0; -} - -int sb_read_spd(uint8_t spdAddress, char *buf, size_t len) -{ - return readspd(spdAddress, buf, len); -} From 5f672636d6990414edaad8e2ce5c75f335122e9a Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 22 Apr 2019 16:04:13 -0600 Subject: [PATCH 014/231] soc/amd/picasso: Change header guards from stoney to picasso TEST=None BUG=b:130804851 Signed-off-by: Martin Roth Change-Id: I32b7dbeae7538884311ccfc3a0e8db63c48fe356 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32409 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel Reviewed-by: Edward O'Callaghan Reviewed-by: HAOUAS Elyes --- src/soc/amd/picasso/chip.h | 6 +++--- src/soc/amd/picasso/include/soc/acpi.h | 6 +++--- src/soc/amd/picasso/include/soc/cpu.h | 6 +++--- src/soc/amd/picasso/include/soc/gpio.h | 6 +++--- src/soc/amd/picasso/include/soc/i2c.h | 6 +++--- src/soc/amd/picasso/include/soc/iomap.h | 6 +++--- src/soc/amd/picasso/include/soc/northbridge.h | 6 +++--- src/soc/amd/picasso/include/soc/nvs.h | 6 +++--- src/soc/amd/picasso/include/soc/pci_devs.h | 6 +++--- src/soc/amd/picasso/include/soc/romstage.h | 6 +++--- src/soc/amd/picasso/include/soc/smbus.h | 6 +++--- src/soc/amd/picasso/include/soc/smi.h | 6 +++--- src/soc/amd/picasso/include/soc/southbridge.h | 6 +++--- 13 files changed, 39 insertions(+), 39 deletions(-) diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index d1a7d30199..4f241e7b6b 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_CHIP_H__ -#define __STONEYRIDGE_CHIP_H__ +#ifndef __PICASSO_CHIP_H__ +#define __PICASSO_CHIP_H__ #include #include @@ -78,4 +78,4 @@ typedef struct soc_amd_stoneyridge_config config_t; extern struct device_operations pci_domain_ops; -#endif /* __STONEYRIDGE_CHIP_H__ */ +#endif /* __PICASSO_CHIP_H__ */ diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 15a41edce6..71fe10eb26 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -15,8 +15,8 @@ * GNU General Public License for more details. */ -#ifndef __SOC_STONEYRIDGE_ACPI_H__ -#define __SOC_STONEYRIDGE_ACPI_H__ +#ifndef __SOC_PICASSO_ACPI_H__ +#define __SOC_PICASSO_ACPI_H__ #include @@ -37,4 +37,4 @@ void southbridge_inject_dsdt(struct device *device); const char *soc_acpi_name(const struct device *dev); -#endif /* __SOC_STONEYRIDGE_ACPI_H__ */ +#endif /* __SOC_PICASSO_ACPI_H__ */ diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 934a9f2983..d9d48ad27c 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_CPU_H__ -#define __STONEYRIDGE_CPU_H__ +#ifndef __PICASSO_CPU_H__ +#define __PICASSO_CPU_H__ #include @@ -32,4 +32,4 @@ void stoney_init_cpus(struct device *dev); void check_mca(void); -#endif /* __STONEYRIDGE_CPU_H__ */ +#endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index d8774f051a..411144beb6 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_GPIO_H__ -#define __STONEYRIDGE_GPIO_H__ +#ifndef __PICASSO_GPIO_H__ +#define __PICASSO_GPIO_H__ #define GPIO_DEVICE_NAME "AMD0030" #define GPIO_DEVICE_DESC "GPIO Controller" @@ -305,4 +305,4 @@ #define GPIO_2_EVENT GEVENT_8 #endif /* __ACPI__ */ -#endif /* __STONEYRIDGE_GPIO_H__ */ +#endif /* __PICASSO_GPIO_H__ */ diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index 62575d0fb8..fb9b113c8e 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_I2C_H__ -#define __STONEYRIDGE_I2C_H__ +#ifndef __PICASSO_I2C_H__ +#define __PICASSO_I2C_H__ #include @@ -46,4 +46,4 @@ struct soc_amd_i2c_save { void sb_reset_i2c_slaves(void); -#endif /* __STONEYRIDGE_I2C_H__ */ +#endif /* __PICASSO_I2C_H__ */ diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 612b6e871b..a63b16462b 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#ifndef __SOC_STONEYRIDGE_IOMAP_H__ -#define __SOC_STONEYRIDGE_IOMAP_H__ +#ifndef __SOC_PICASSO_IOMAP_H__ +#define __SOC_PICASSO_IOMAP_H__ /* MMIO Ranges */ #define PSP_MAILBOX_BAR3_BASE 0xf0a00000 @@ -85,4 +85,4 @@ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ -#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */ +#endif /* __SOC_PICASSO_IOMAP_H__ */ diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index 60a6ea22bb..f7df2772c5 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__ -#define __PI_STONEYRIDGE_NORTHBRIDGE_H__ +#ifndef __PI_PICASSO_NORTHBRIDGE_H__ +#define __PI_PICASSO_NORTHBRIDGE_H__ #include #include @@ -130,4 +130,4 @@ void set_ap_entry_ptr(void *entry); void set_warm_reset_flag(void); int is_warm_reset(void); -#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */ +#endif /* __PI_PICASSO_NORTHBRIDGE_H__ */ diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 08d46973c0..8ce5da623a 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -21,8 +21,8 @@ * */ -#ifndef __SOC_STONEYRIDGE_NVS_H__ -#define __SOC_STONEYRIDGE_NVS_H__ +#ifndef __SOC_PICASSO_NVS_H__ +#define __SOC_PICASSO_NVS_H__ #include #include @@ -64,4 +64,4 @@ typedef struct global_nvs_t { } __packed global_nvs_t; check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -#endif /* __SOC_STONEYRIDGE_NVS_H__ */ +#endif /* __SOC_PICASSO_NVS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 02fed7ab1e..478a2cb623 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__ -#define __PI_STONEYRIDGE_PCI_DEVS_H__ +#ifndef __PI_PICASSO_PCI_DEVS_H__ +#define __PI_PICASSO_PCI_DEVS_H__ #include @@ -195,4 +195,4 @@ #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) #define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC) -#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */ +#endif /* __PI_PICASSO_PCI_DEVS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h index 6ce79b424e..d8b2900fb5 100644 --- a/src/soc/amd/picasso/include/soc/romstage.h +++ b/src/soc/amd/picasso/include/soc/romstage.h @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_ROMSTAGE_H__ -#define __STONEYRIDGE_ROMSTAGE_H__ +#ifndef __PICASSO_ROMSTAGE_H__ +#define __PICASSO_ROMSTAGE_H__ void mainboard_romstage_entry(int s3_resume); -#endif /* __STONEYRIDGE_ROMSTAGE_H__ */ +#endif /* __PICASSO_ROMSTAGE_H__ */ diff --git a/src/soc/amd/picasso/include/soc/smbus.h b/src/soc/amd/picasso/include/soc/smbus.h index 391084d807..c4bc28fdf2 100644 --- a/src/soc/amd/picasso/include/soc/smbus.h +++ b/src/soc/amd/picasso/include/soc/smbus.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_SMBUS_H__ -#define __STONEYRIDGE_SMBUS_H__ +#ifndef __PICASSO_SMBUS_H__ +#define __PICASSO_SMBUS_H__ #include #include @@ -32,4 +32,4 @@ int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val); int do_smbus_recv_byte(u32 mmio, u8 device); int do_smbus_send_byte(u32 mmio, u8 device, u8 val); -#endif /* __STONEYRIDGE_SMBUS_H__ */ +#endif /* __PICASSO_SMBUS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index 000eed8554..da32610eed 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -15,8 +15,8 @@ * GNU General Public License for more details. */ -#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ -#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ +#ifndef __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ +#define __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ #define SMI_GEVENTS 24 @@ -239,4 +239,4 @@ void soc_route_sci(uint8_t event); void enable_smi_generation(void); #endif -#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */ +#endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index ad4040759c..fa9206e33a 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_H__ -#define __STONEYRIDGE_H__ +#ifndef __PICASSO_SB_H__ +#define __PICASSO_SB_H__ #include #include @@ -412,4 +412,4 @@ void i2c_soc_early_init(void); /* Initialize all the i2c buses that are not marked with early init. */ void i2c_soc_init(void); -#endif /* __STONEYRIDGE_H__ */ +#endif /* __PICASSO_SB_H__ */ From 1f33762d77ad29a90125f47417b76b3c3314f79d Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 22 Apr 2019 16:08:31 -0600 Subject: [PATCH 015/231] soc/amd/picasso: Change SOC_AMD_STONEY* to SOC_AMD_PICASSO TEST=None BUG=b:130804851 Signed-off-by: Martin Roth Change-Id: Ie466bc39ed6aa9d2a8651bd9290090b83cd97d74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32410 Reviewed-by: Richard Spiegel Reviewed-by: Edward O'Callaghan Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Kconfig | 13 ++++--------- src/soc/amd/picasso/makefile.inc | 4 ++-- 2 files changed, 6 insertions(+), 11 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index ba82565bf4..5863640b24 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -13,17 +13,12 @@ ## GNU General Public License for more details. ## -config SOC_AMD_STONEYRIDGE_FP4 +config SOC_AMD_PICASSO bool help - AMD Stoney Ridge FP4 support + AMD Picasso support -config SOC_AMD_STONEYRIDGE_FT4 - bool - help - AMD Stoney Ridge FT4 support - -if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 +if SOC_AMD_PICASSO config CPU_SPECIFIC_OPTIONS def_bool y @@ -386,4 +381,4 @@ config MAINBOARD_POWER_RESTORE return to S0. Otherwise the system will remain in S5 once power is restored. -endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 +endif # SOC_AMD_PICASSO diff --git a/src/soc/amd/picasso/makefile.inc b/src/soc/amd/picasso/makefile.inc index 05529d9a97..f38f8ad1f2 100644 --- a/src/soc/amd/picasso/makefile.inc +++ b/src/soc/amd/picasso/makefile.inc @@ -27,7 +27,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_PICASSO),y) subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/tsc @@ -300,4 +300,4 @@ endif endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) -endif # ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +endif # ($(CONFIG_SOC_AMD_PICASSO),y) From 070e79ea926795738d0cb744afa1673d285d7dfd Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 22 Apr 2019 19:04:02 -0600 Subject: [PATCH 016/231] soc/amd/picasso: Rename makefile.inc back to Makefile.inc Now that the Makefile is updated, we can change the name back without it affecting the Stoney build. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth Change-Id: I18ee48865fb64265f38179560265827783d50820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32411 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel Reviewed-by: Edward O'Callaghan Reviewed-by: HAOUAS Elyes --- src/soc/amd/picasso/{makefile.inc => Makefile.inc} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename src/soc/amd/picasso/{makefile.inc => Makefile.inc} (100%) diff --git a/src/soc/amd/picasso/makefile.inc b/src/soc/amd/picasso/Makefile.inc similarity index 100% rename from src/soc/amd/picasso/makefile.inc rename to src/soc/amd/picasso/Makefile.inc From d7e3ead8358ac76d432e26849951defb9ab28a9b Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 22 Apr 2019 16:32:58 -0600 Subject: [PATCH 017/231] soc/amd/picasso: Update stoney paths to picasso Update paths. There are still a few paths in Kconfig relating to PSP and the firmware directory table. Those will be updated in a follow-on commit. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth Change-Id: I18f3d80dbeabd754ebcee6593864fd613fc2ef7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/32412 Reviewed-by: Richard Spiegel Reviewed-by: Edward O'Callaghan Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Kconfig | 2 +- src/soc/amd/picasso/Makefile.inc | 6 +++--- src/soc/amd/picasso/acpi/globalnvs.asl | 2 +- src/soc/amd/picasso/include/soc/nvs.h | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5863640b24..382aaef96e 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -137,7 +137,7 @@ config VGA_BIOS_ID config VGA_BIOS_FILE string - default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin" + default "3rdparty/blobs/soc/amd/picasso/VBIOS.bin" config S3_VGA_ROM_RUN bool diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index f38f8ad1f2..bb24c67b05 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -109,9 +109,9 @@ smm-$(CONFIG_DEBUG_SMI) += uart.c smm-$(CONFIG_SPI_FLASH) += spi.c smm-y += gpio.c -CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge -CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include -CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/acpi +CPPFLAGS_common += -I$(src)/soc/amd/picasso +CPPFLAGS_common += -I$(src)/soc/amd/picasso/include +CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi # ROMSIG Normally At ROMBASE + 0x20000 # Overridden by CONFIG_AMD_FWM_POSITION_INDEX diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 03d205f8d3..e780a642c6 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -17,7 +17,7 @@ /* * NOTE: The layout of the GNVS structure below must match the layout in - * soc/amd/stoneyridge/include/soc/nvs.h !!! + * soc/amd/picasso/include/soc/nvs.h !!! * */ diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 8ce5da623a..5023df6b27 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -17,7 +17,7 @@ /* * NOTE: The layout of the global_nvs_t structure below must match the layout - * in soc/soc/amd/stoneyridge/acpi/globalnvs.asl !!! + * in soc/soc/amd/picasso/acpi/globalnvs.asl !!! * */ From 778c8a77c1fc468b320f3471e7e753fd6f4afed7 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 22 Apr 2019 16:14:12 -0600 Subject: [PATCH 018/231] soc/amd/picasso: Stub out bootblock Remove all Picasso bootblock support. CAR is not a supportable feature, and the first code executed at the reset vector will be a hybrid romstage. Details for this implementation may be found in Documentation/soc/amd/picasso/family17h.md. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth Change-Id: I8edf45c02dc5bfcdca03abf1294db4be508682cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/32413 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel Reviewed-by: Edward O'Callaghan Reviewed-by: HAOUAS Elyes --- src/soc/amd/picasso/Makefile.inc | 15 ++-- src/soc/amd/picasso/bootblock/bootblock.c | 105 +--------------------- src/soc/amd/picasso/cache_as_ram.S | 20 +++++ 3 files changed, 26 insertions(+), 114 deletions(-) create mode 100644 src/soc/amd/picasso/cache_as_ram.S diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index bb24c67b05..e8c022fcda 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -37,17 +37,12 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm -bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c +# TODO: Make coreboot modifications so bootblock can be removed. This soc +# also selects C_ENVIRONMENT_BOOTBLOCK to enforce certain codepaths +# in romstage. As a result, the bootblock build also needs a +# dummy cache_as_ram.S +bootblock-y += cache_as_ram.S bootblock-y += bootblock/bootblock.c -bootblock-y += gpio.c -bootblock-y += i2c.c -bootblock-y += monotonic_timer.c -bootblock-y += pmutil.c -bootblock-y += reset.c -bootblock-y += tsc_freq.c -bootblock-y += southbridge.c -bootblock-$(CONFIG_SPI_FLASH) += spi.c -bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += i2c.c romstage-y += romstage.c diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 9239030d6c..62e4e1589f 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation.. - * Copyright (C) 2017 Advanced Micro Devices - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -14,109 +11,9 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include -#include -#include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000 -#error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB" -#endif -#if CONFIG_PI_AGESA_CAR_HEAP_BASE < 0x100000 -#error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB" -#endif - -/* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ -static void amd_initmmio(void) -{ - msr_t mmconf; - msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); - int mtrr; - - mmconf.hi = 0; - mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN - | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; - wrmsr(MMIO_CONF_BASE, mmconf); - - /* - * todo: AGESA currently writes variable MTRRs. Once that is - * corrected, un-hardcode this MTRR. - * - * Be careful not to use get_free_var_mtrr/set_var_mtrr pairs - * where all cores execute the path. Both cores within a compute - * unit share MTRRs. Programming core0 has the appearance of - * modifying core1 too. Using the pair again will create - * duplicate copies. - */ - mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH; - set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - - mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_CAR_HEAP; - set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE, - CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK); - - mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_TEMPRAM; - set_var_mtrr(mtrr, CONFIG_PI_AGESA_TEMP_RAM_BASE, - CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE); -} asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - amd_initmmio(); - /* - * Call lib/bootblock.c main with BSP, shortcut for APs - */ - if (!boot_cpu()) { - void (*ap_romstage_entry)(void) = - (void (*)(void))get_ap_entry_ptr(); - - ap_romstage_entry(); /* execution does not return */ - halt(); - } - - /* TSC cannot be relied upon. Override the TSC value passed in. */ - bootblock_main_with_timestamp(timestamp_get(), NULL, 0); -} - -void bootblock_soc_early_init(void) -{ - /* - * This call (sb_reset_i2c_slaves) was originally early at - * bootblock_c_entry, but had to be moved here. There was an - * unexplained delay in the middle of the i2c transaction when - * we had it in bootblock_c_entry. Moving it to this point - * (or adding delays) fixes the issue. It seems like the processor - * just pauses but we don't know why. - */ - sb_reset_i2c_slaves(); - bootblock_fch_early_init(); - post_code(0x90); -} - -void bootblock_soc_init(void) -{ - if (CONFIG(STONEYRIDGE_UART)) - assert(CONFIG_UART_FOR_CONSOLE >= 0 - && CONFIG_UART_FOR_CONSOLE <= 1); - - u32 val = cpuid_eax(1); - printk(BIOS_DEBUG, "Family_Model: %08x\n", val); - - bootblock_fch_init(); - - /* Initialize any early i2c buses. */ - i2c_soc_early_init(); + /* This function is here for building/linking only */ } diff --git a/src/soc/amd/picasso/cache_as_ram.S b/src/soc/amd/picasso/cache_as_ram.S new file mode 100644 index 0000000000..28690628d6 --- /dev/null +++ b/src/soc/amd/picasso/cache_as_ram.S @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * TODO: This is a dummy file for making bootblock build and link. At some + * point, this should be removed from picasso since bootblock is + * ignored. + */ +.global bootblock_pre_c_entry +bootblock_pre_c_entry: From c645ae069b42bd91683e99049644fc100bb60521 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 11 Jun 2019 13:04:37 -0600 Subject: [PATCH 019/231] soc/amd: Add picasso to Kconfig Change-Id: I7031b07ae105a14be3c5d4e52ecc1364956fd845 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/33750 Reviewed-by: Richard Spiegel Reviewed-by: Edward O'Callaghan Tested-by: build bot (Jenkins) --- src/soc/amd/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/Kconfig b/src/soc/amd/Kconfig index 0c33b54cb2..7c08f031b0 100644 --- a/src/soc/amd/Kconfig +++ b/src/soc/amd/Kconfig @@ -1,4 +1,5 @@ # Load all chipsets before common +source "src/soc/amd/picasso/Kconfig" source "src/soc/amd/stoneyridge/Kconfig" # Load common defaults last From ad23778d235e57fc2c7264f3f3f97919db0e81d3 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Wed, 26 Jun 2019 14:46:45 -0700 Subject: [PATCH 020/231] mb/google/hatch: Add INVERT to all IOAPIC pads Now that ITSS config is fixed, we can set the IOAPIC pad configs correctly. BUG=b:123967687 BRANCH=None TEST=Make sure Hatch is booting and tested out trackpad to make sure can move cursor and wake by clicking on the trackpad after running powerd_dbus_suspend. Change-Id: I0b125996338b6f16e03b7ca184f6337c696a5f64 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/33819 Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Fagerburg Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../google/hatch/variants/baseboard/gpio.c | 34 ++++++------------- .../google/hatch/variants/hatch/gpio.c | 7 ++-- 2 files changed, 12 insertions(+), 29 deletions(-) diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 9529cc750a..a4fb4c9711 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -52,8 +52,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_A18, 1, DEEP), /* A19 : WWAN_RADIO_DISABLE_1V8_ODL */ PAD_CFG_GPO(GPP_A19, 1, DEEP), - /* A20 : M2_INT_L */ - PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, NONE), + /* A20 : WLAN_INT_L */ + PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, INVERT), /* * A21 : TRACKPAD_INT_ODL (wake) * TODO Combine into single gpio, when ITSS IPCx configuration @@ -62,11 +62,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), /* A22 : FPMCU_PCH_BOOT0 */ PAD_CFG_GPO(GPP_A22, 0, DEEP), - /* A23 : FPMCU_PCH_INT_ODL - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, NONE), + /* A23 : FPMCU_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), /* B0 : CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), @@ -143,11 +140,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_C11, 1, DEEP), /* C12 : GPP_C12 ==> NC */ PAD_NC(GPP_C12, NONE), - /* C13 : EC_PCH_INT_L - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, NONE), + /* C13 : EC_PCH_INT_L */ + PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, INVERT), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 1, DEEP), /* C15 : WWAN_DPR_SAR_ODL @@ -166,12 +160,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* C20 : PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* - * C21 : H1_PCH_INT_ODL - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, NONE), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), /* C22 : EC_IN_RW_OD */ PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ @@ -451,12 +441,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* - * C21 : H1_PCH_INT_ODL - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, NONE), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* F2 : MEM_CH_SEL */ diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 7e73724387..f95e0220f1 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -19,11 +19,8 @@ #include static const struct pad_config gpio_table[] = { - /* C13 : EC_PCH_INT_L - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, NONE)}; + /* C13 : EC_PCH_INT_L */ + PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; const struct pad_config *override_gpio_table(size_t *num) { From 328b77a5e9df9bbca38dd41ef2d385868d0bbf50 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Wed, 26 Jun 2019 14:56:18 -0700 Subject: [PATCH 021/231] mb/google/hatch: Set trackpad irq and wake to GPP_A21 Previously, We had to use GPP_A21 for trackpad wake and GPP_D21 for trackpad interrupts due to ITSS not honoring the INVERT config. Now that's fixed, we can configure trackpad wake and interrupts on GPP_A21 only. BUG=b:130436471 BRANCH=None TEST=1. boot a hatch device and make sure we can move the cursor with the trackpad 2. Run powerd_dbus_suspend and wake by clicking on the trackpad and ensure through "mosys eventlog list" that the wake source is the trackpad.\ 3. Run "echo mem > /sys/power/state", wait until device goes into S3, click trackpad to ensure device wakes. Change-Id: I26a99206c42ba442f91ae577b98366fc2fd6c0ca Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/33820 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Fagerburg --- .../google/hatch/variants/baseboard/gpio.c | 16 ++++------------ .../google/hatch/variants/hatch/overridetree.cb | 2 +- 2 files changed, 5 insertions(+), 13 deletions(-) diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index a4fb4c9711..56ae601df0 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -54,12 +54,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_A19, 1, DEEP), /* A20 : WLAN_INT_L */ PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, INVERT), - /* - * A21 : TRACKPAD_INT_ODL (wake) - * TODO Combine into single gpio, when ITSS IPCx configuration - * is fixed in FSP. - */ - PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), + /* A21 : TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_A21, NONE, DEEP, LEVEL, INVERT), /* A22 : FPMCU_PCH_BOOT0 */ PAD_CFG_GPO(GPP_A22, 0, DEEP), /* A23 : FPMCU_PCH_INT_ODL */ @@ -209,12 +205,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : DMIC_DATA_0_SNDW4_DATA */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), - /* - * D21 : TRACKPAD_INT_ODL - * TODO Combine into single gpio with invert mode, when ITSS - * IPCx configuration is fixed in FSP. - */ - PAD_CFG_GPI_APIC(GPP_D21, NONE, PLTRST, LEVEL, NONE), + /* D21 : GPP_D21 ==> NC */ + PAD_NC(GPP_D21, NONE), /* D22 : GPP_D22 ==> NC */ PAD_NC(GPP_D22, NONE), /* D23 : SPP_MCLK */ diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index d676843720..2582940a1a 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -63,7 +63,7 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" device i2c 15 on end end From 3b34ef29b36401c40ecebaa9079ba1565fdffe17 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sun, 30 Jun 2019 11:41:51 +0200 Subject: [PATCH 022/231] util/release: add more categories Change-Id: I73cd50da7b2f1aaf1ab05daad4997c5e48172f25 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/33929 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Martin Roth --- util/release/genrelnotes | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/util/release/genrelnotes b/util/release/genrelnotes index 9a88b49c6c..e4f304b727 100755 --- a/util/release/genrelnotes +++ b/util/release/genrelnotes @@ -291,7 +291,7 @@ log_versions "$(git log --pretty=%H \ echo "" >> "$LOGFILE" ### SPECIFIC AREAS FOR RELEASE ### -get_log_dedupe "cleanup" "" "spelling\|Use tabs\|transition away from device_t\|space [around\|before]\|code formatting\|commented code\|code cleanup\|capitalize\|unnecessary whitespace\|checkpatch" +get_log_dedupe "cleanup" "" "spelling\|Use tabs\|transition away from device_t\|space [around\|before]\|code formatting\|commented code\|code cleanup\|capitalize\|unnecessary whitespace\|checkpatch\|remove unused\|remove.*not used" get_log_dedupe "Google Kahlee / AMD Gardenia" "src/mainboard/google/kahlee src/mainboard/amd/gardenia" "kahlee\|gardenia" get_log_dedupe "AMD Stoney Ridge" "src/soc/amd/stoneyridge" "stoney" @@ -329,11 +329,16 @@ get_log_dedupe "Intel Sandybridge / Ivybridge" "src/southbridge/intel/bd82x6x sr get_log_dedupe "Intel Common" "src/soc/intel/common src/southbridge/intel/common src/northbridge/intel/common" "" get_log_dedupe "Amd Common" "src/soc/amd/common src/southbridge/amd/common" "" +get_log_dedupe "Nvidia" "src/southbridge/nvidia" "" +get_log_dedupe "Via" "src/northbridge/via src/southbridge/via" "" +get_log_dedupe "Broadcom" "src/southbridge/broadcom" "" +get_log_dedupe "Qualcomm" "src/soc/qualcomm" "" + get_log_dedupe "Intel vendorcode / FSP" "src/drivers/intel/fsp* src/vendorcode/intel" "" get_log_dedupe "AMD vendorcode / AGESA / PI" "src/vendorcode/amd" "" get_log_dedupe "Google vendorcode" "src/vendorcode/google" -get_log_dedupe "TPM" "src/drivers/i2c/tpm" "tpm" +get_log_dedupe "TPM" "src/drivers/i2c/tpm src/security/tpm" "tpm" get_log_dedupe "Vboot" "src/vboot" "vboot" @@ -394,6 +399,9 @@ get_log_dedupe "Build system" \ "Makefile Makefile.inc toolchain.inc src/Kconfig src/cpu/Makefile.inc" get_log_dedupe "Submodules" "3rdparty util/nvidia/cbootimage" + +get_log_dedupe "Maintainers" "MAINTAINERS" "" + # Finally, get anything that was missed above get_log_dedupe "MISC" "." From 328d2e2a7db357e6b7b8aad75cd1a9aea3c11be5 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sun, 30 Jun 2019 23:45:22 +0200 Subject: [PATCH 023/231] util/docker/coreboot.org-status: Add more "nice" names for CPUs It's not perfect and we'll need to find a better place for that, but I'll look into that as part of the big board-status rework. Change-Id: I2ae50c58e3796563e0b2370105abc82b7e2e042a Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/33930 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Martin Roth --- .../board-status.html/tohtml.sh | 73 ++++++++++++++++++- 1 file changed, 72 insertions(+), 1 deletion(-) diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index 1992826667..41de9ff238 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -248,7 +248,12 @@ EOF southbridge_nice="$(echo "$southbridge"|sed 's,_, ,g;s,INTEL,Intel®,g')" superio="$(sed -n "/[[:space:]]*select SUPERIO_/ s,[[:space:]]*select SUPERIO_,,p" "$vendor_board_dir/Kconfig"|grep -v OVERRIDE_FANCTL)" superio_nice="$(echo "$superio"|sed 's,_, ,g;s,WINBOND,Winbond™,g;s,ITE,ITE™,g;s,SMSC,SMSC®,g;s,NUVOTON,Nuvoton ,g')" - cpu="$(sed -n "/ select CPU_/ s, select CPU_,,p" "$vendor_board_dir/Kconfig"|grep -v "AMD_AGESA_FAMILY"|grep -v CPU_MICROCODE_CBFS_NONE)" + cpu="$(sed -n \ + -e "/ select CPU_/ s, select CPU_,,p" \ + -e "/ select SOC_/ s, select SOC_,,p" \ + "$vendor_board_dir/Kconfig" | \ + grep -v "AMD_AGESA_FAMILY" | \ + grep -v CPU_MICROCODE_CBFS_NONE)" case "$cpu" in ALLWINNER_A10) cpu_nice="Allwinner A10" @@ -302,12 +307,24 @@ EOF AMD_SC520) cpu_nice="AMD Élan™SC520"; socket_nice="—";; + AMD_STONEYRIDGE_FP4) + cpu_nice="AMD Stoney Ridge"; + socket_nice="FP4 BGA";; ARMLTD_CORTEX_A9) cpu_nice="ARM Cortex A9"; socket_nice="?";; DMP_VORTEX86EX) cpu_nice="DMP VORTEX86EX"; socket_nice="?";; + MEDIATEK_MT8173) + cpu_nice="MediaTek MT8173"; + socket_nice="—";; + NVIDIA_TEGRA124) + cpu_nice="NVIDIA Tegra 124"; + socket_nice="—";; + NVIDIA_TEGRA210) + cpu_nice="NVIDIA Tegra 210"; + socket_nice="—";; SAMSUNG_EXYNOS5420) cpu_nice="Samsung Exynos 5420"; socket_nice="?";; @@ -317,6 +334,42 @@ EOF TI_AM335X) cpu_nice="TI AM335X"; socket_nice="?";; + IMGTEC_PISTACHIO) + cpu_nice="Imagination Technologies Pistachio"; + socket_nice="—";; + INTEL_APOLLOLAKE) + cpu_nice="Intel® Apollo Lake"; + socket_nice="—";; + INTEL_BAYTRAIL) + cpu_nice="Intel® Bay Trail"; + socket_nice="—";; + INTEL_BRASWELL) + cpu_nice="Intel® Braswell"; + socket_nice="—";; + INTEL_BROADWELL) + cpu_nice="Intel® Broadwell"; + socket_nice="—";; + INTEL_DENVERTON_NS) + cpu_nice="Intel® Denverton-NS"; + socket_nice="—";; + INTEL_FSP_BROADWELL_DE) + cpu_nice="Intel® Broadwell-DE"; + socket_nice="—";; + INTEL_GLK) + cpu_nice="Intel® Gemini Lake"; + socket_nice="—";; + INTEL_ICELAKE) + cpu_nice="Intel® Ice Lake"; + socket_nice="—";; + INTEL_KABYLAKE) + cpu_nice="Intel® Kaby Lake"; + socket_nice="—";; + INTEL_SANDYBRIDGE) + cpu_nice="Intel® Sandy Bridge"; + socket_nice="—";; + INTEL_SKYLAKE) + cpu_nice="Intel® Skylake"; + socket_nice="—";; INTEL_SLOT_1) cpu_nice="Intel® Pentium® II/III, Celeron®"; socket_nice="Slot 1";; @@ -384,6 +437,24 @@ EOF INTEL_SOCKET_MFCBGA479) cpu_nice="Intel® Mobile Celeron" socket_nice="Socket 479";; + INTEL_WHISKEYLAKE) + cpu_nice="Intel® Whiskey Lake"; + socket_nice="—";; + QC_IPQ806X) + cpu_nice="Qualcomm IPQ806x"; + socket_nice="—";; + QUALCOMM_QCS405) + cpu_nice="Qualcomm QCS405"; + socket_nice="—";; + QUALCOMM_SDM845) + cpu_nice="Qualcomm SDM845"; + socket_nice="—";; + ROCKCHIP_RK3288) + cpu_nice="Rockchip RK3288"; + socket_nice="—";; + ROCKCHIP_RK3399) + cpu_nice="Rockchip RK3399"; + socket_nice="—";; VIA_C3) cpu_nice="VIA C3™"; socket_nice="?" From 1c9bd9ce61391d990839cca12380f2ce11c44bc7 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 26 Jun 2019 17:49:31 +0200 Subject: [PATCH 024/231] arch/x86: Fix cpu_cpuid_extended_level() return type `cpuid_eax()` returns an unsigned integer. Change-Id: Iebb6501130bc9ae333d45ae9d2e10c918245a6d1 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33814 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Nico Huber --- src/arch/x86/cpu_common.c | 2 +- src/arch/x86/include/arch/cpu.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index 119122786d..0fd0af016f 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -49,7 +49,7 @@ int cpu_have_cpuid(void) } #endif -int cpu_cpuid_extended_level(void) +unsigned int cpu_cpuid_extended_level(void) { return cpuid_eax(0x80000000); } diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index ff1a33b9ea..75f1f439b8 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -200,7 +200,7 @@ static inline unsigned int cpuid_edx(unsigned int op) #define CPUID_CACHE_NO_OF_SETS_MASK 0xffffffff #define CPUID_CACHE_NO_OF_SETS(res) CPUID_CACHE(NO_OF_SETS, (res).ecx) -int cpu_cpuid_extended_level(void); +unsigned int cpu_cpuid_extended_level(void); int cpu_have_cpuid(void); void smm_init(void); From a88921e2b0123226d2258850a229f434007e9807 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Thu, 20 Jun 2019 11:45:43 -0700 Subject: [PATCH 025/231] 3rdparty/fsp: Update submodule pointer Update fsp submodule pointer to Coffee Lake FSP 7.0.64.40 github commit: https://github.com/IntelFsp/FSP/commit/59964173e18950debcc6b8856c5c928935ce0b4f Change-Id: I864404a03be63aa60e81db21af16d69cda2d4e12 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/33642 Reviewed-by: Lijian Zhao Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- 3rdparty/fsp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/fsp b/3rdparty/fsp index 1d2b7e1a94..59964173e1 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 1d2b7e1a94c6a7c25a6fed1ac37caebf500f5f1a +Subproject commit 59964173e18950debcc6b8856c5c928935ce0b4f From 414d5d8698c2acc1655ba59ff794524cd45e7fb6 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Thu, 27 Jun 2019 16:02:32 -0600 Subject: [PATCH 026/231] util/cbmem: Use correct integer types for loop indices Make sure that the type of the loop index matches the type of the upper bound. This fixes several -Wsign-compare warnings. Change-Id: Iaa94ce93bc35d523bc782ad914bfd283606becac Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Martin Roth --- util/cbmem/cbmem.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 9d2a64349c..563bcbe9c2 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -543,9 +543,7 @@ static void print_norm(u64 v) static const char *timestamp_name(uint32_t id) { - int i; - - for (i = 0; i < ARRAY_SIZE(timestamp_ids); i++) { + for (size_t i = 0; i < ARRAY_SIZE(timestamp_ids); i++) { if (timestamp_ids[i].id == id) return timestamp_ids[i].name; } @@ -608,7 +606,6 @@ static int compare_timestamp_entries(const void *a, const void *b) /* dump the timestamp table */ static void dump_timestamps(int mach_readable) { - int i; const struct timestamp_table *tst_p; struct timestamp_table *sorted_tst_p; size_t size; @@ -656,7 +653,7 @@ static void dump_timestamps(int mach_readable) sizeof(struct timestamp_entry), compare_timestamp_entries); total_time = 0; - for (i = 0; i < sorted_tst_p->num_entries; i++) { + for (uint32_t i = 0; i < sorted_tst_p->num_entries; i++) { uint64_t stamp; const struct timestamp_entry *tse = &sorted_tst_p->entries[i]; @@ -685,7 +682,6 @@ static void dump_timestamps(int mach_readable) /* dump the tcpa log table */ static void dump_tcpa_log(void) { - int i, j; const struct tcpa_table *tclt_p; size_t size; struct mapping tcpa_mapping; @@ -710,12 +706,12 @@ static void dump_tcpa_log(void) printf("coreboot TCPA log:\n\n"); - for (i = 0; i < tclt_p->num_entries; i++) { + for (uint16_t i = 0; i < tclt_p->num_entries; i++) { const struct tcpa_entry *tce = &tclt_p->entries[i]; printf(" PCR-%u ", tce->pcr); - for (j = 0; j < tce->digest_length; j++) + for (uint32_t j = 0; j < tce->digest_length; j++) printf("%02x", tce->digest[j]); printf(" %s [%s]\n", tce->digest_type, tce->name); @@ -806,9 +802,8 @@ static void dump_console(int one_boot_only) BANNER_REGEX("romstage"), OVERFLOW_REGEX("ramstage"), BANNER_REGEX("ramstage") }; - int i; - for (i = 0; !cursor && i < ARRAY_SIZE(regex); i++) { + for (size_t i = 0; !cursor && i < ARRAY_SIZE(regex); i++) { regex_t re; regmatch_t match; assert(!regcomp(&re, regex[i], 0)); @@ -875,7 +870,6 @@ static void dump_cbmem_hex(void) void rawdump(uint64_t base, uint64_t size) { - int i; const uint8_t *m; struct mapping dump_mapping; @@ -883,7 +877,7 @@ void rawdump(uint64_t base, uint64_t size) if (!m) die("Unable to map rawdump memory\n"); - for (i = 0 ; i < size; i++) + for (uint64_t i = 0 ; i < size; i++) printf("%c", m[i]); unmap_memory(&dump_mapping); @@ -937,12 +931,11 @@ static const struct cbmem_id_to_name cbmem_ids[] = { CBMEM_ID_TO_NAME_TABLE }; #define MAX_STAGEx 10 void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size) { - int i; const char *name; char stage_x[20]; name = NULL; - for (i = 0; i < ARRAY_SIZE(cbmem_ids); i++) { + for (size_t i = 0; i < ARRAY_SIZE(cbmem_ids); i++) { if (cbmem_ids[i].id == id) { name = cbmem_ids[i].name; break; @@ -1390,11 +1383,10 @@ int main(int argc, char** argv) parse_cbtable(baseaddr, cb_table_size); #else - int j; unsigned long long possible_base_addresses[] = { 0, 0xf0000 }; /* Find and parse coreboot table */ - for (j = 0; j < ARRAY_SIZE(possible_base_addresses); j++) { + for (size_t j = 0; j < ARRAY_SIZE(possible_base_addresses); j++) { if (!parse_cbtable(possible_base_addresses[j], 0)) break; } From 4d543b5aa61558bfd6ad99c7b525e123fc6c3620 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Thu, 27 Jun 2019 16:08:38 -0600 Subject: [PATCH 027/231] util/cbmem: Enable -Wextra This enables extra useful warnings. Change-Id: I4afbbb0fefb32a7d954aafd87df17075b0abe6f7 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33851 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Martin Roth --- util/cbmem/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile index eed08a4cb3..e7318a17d4 100644 --- a/util/cbmem/Makefile +++ b/util/cbmem/Makefile @@ -19,7 +19,7 @@ CC ?= $(CROSS_COMPILE)gcc INSTALL ?= /usr/bin/env install PREFIX ?= /usr/local CFLAGS ?= -O2 -CFLAGS += -Wall -Werror +CFLAGS += -Wall -Wextra -Werror CPPFLAGS += -I . -I $(ROOT)/commonlib/include CPPFLAGS += -include ../../src/commonlib/include/commonlib/compiler.h From 79a2f4767d2c5f200231568c01cc763fdc860df7 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Thu, 27 Jun 2019 17:23:25 -0600 Subject: [PATCH 028/231] util/cbmem: Make internal functions static These functions are only used in cbmem, so they can be made static. Change-Id: I21f7d7c21064a8ae951e6d96b28c2ddcf52c0006 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33852 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Martin Roth --- util/cbmem/cbmem.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 563bcbe9c2..ca6a2f4a48 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -521,7 +521,7 @@ static void timestamp_set_tick_freq(unsigned long table_tick_freq_mhz) debug("Timestamp tick frequency: %ld MHz\n", tick_freq_mhz); } -u64 arch_convert_raw_ts_entry(u64 ts) +static u64 arch_convert_raw_ts_entry(u64 ts) { return ts / tick_freq_mhz; } @@ -569,7 +569,7 @@ static uint64_t timestamp_print_parseable_entry(uint32_t id, uint64_t stamp, return step_time; } -uint64_t timestamp_print_entry(uint32_t id, uint64_t stamp, uint64_t prev_stamp) +static uint64_t timestamp_print_entry(uint32_t id, uint64_t stamp, uint64_t prev_stamp) { const char *name; uint64_t step_time; @@ -868,7 +868,7 @@ static void dump_cbmem_hex(void) hexdump(unpack_lb64(cbmem.start), unpack_lb64(cbmem.size)); } -void rawdump(uint64_t base, uint64_t size) +static void rawdump(uint64_t base, uint64_t size) { const uint8_t *m; struct mapping dump_mapping; @@ -929,7 +929,7 @@ struct cbmem_id_to_name { static const struct cbmem_id_to_name cbmem_ids[] = { CBMEM_ID_TO_NAME_TABLE }; #define MAX_STAGEx 10 -void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size) +static void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size) { const char *name; char stage_x[20]; From 0476332161920187ae03459a124055035d32af6d Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Thu, 27 Jun 2019 17:24:37 -0600 Subject: [PATCH 029/231] util/cbmem: Enable -Wmissing-prototypes Change-Id: Ia8482dc9b6ad800826152c2d3e9813190b0b574e Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33853 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Martin Roth --- util/cbmem/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile index e7318a17d4..485955b68a 100644 --- a/util/cbmem/Makefile +++ b/util/cbmem/Makefile @@ -19,7 +19,7 @@ CC ?= $(CROSS_COMPILE)gcc INSTALL ?= /usr/bin/env install PREFIX ?= /usr/local CFLAGS ?= -O2 -CFLAGS += -Wall -Wextra -Werror +CFLAGS += -Wall -Wextra -Wmissing-prototypes -Werror CPPFLAGS += -I . -I $(ROOT)/commonlib/include CPPFLAGS += -include ../../src/commonlib/include/commonlib/compiler.h From 7803e487bdd64ec0f1a8a17a483a4298d38bb77a Mon Sep 17 00:00:00 2001 From: Paul Fagerburg Date: Thu, 27 Jun 2019 10:44:51 -0600 Subject: [PATCH 030/231] soc/intel/cannonlake: Add support to log XHCI wake events Enhance elog wake source information with more details about which USB port resulted in a wake from S3 or S0ix. BUG=b:123429132 BRANCH=none TEST=``FW_NAME=hatch emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`` Ensure /build/hatch/firmware/image-hatch.serial.bin has been built. Plug a keyboard into a USB port on the DUT. Switch the DUT to the console (Ctrl-Alt-F2, or use the AP console via servo). On the console, run ``powerd_dbus_suspend``. Wait for the DUT to enter low power mode. Verify low power mode by issuing the ``powerinfo`` command on the EC console (via servo). Expect to see ``power state 4 = S0ix``. Press a key on the USB keyboard. The DUT wakes up. On the console, run ``mosys eventlog list`` and look for the wake source. 156 | 2019-06-26 09:46:07 | S0ix Enter 157 | 2019-06-26 12:14:05 | S0ix Exit 158 | 2019-06-26 12:14:05 | Wake Source | Internal PME | 0 159 | 2019-06-26 12:14:05 | Wake Source | GPE # | 109 Program image-hatch.serial.bin into the DUT using flashrom. Repeat the ``powerd_dbus_suspend``, ``powerinfo``, ``mosys eventlog list`` sequence. 12 | 2019-06-26 14:52:23 | S0ix Enter 13 | 2019-06-26 14:53:07 | S0ix Exit 14 | 2019-06-26 14:53:07 | Wake Source | PME - XHCI (USB 2.0 port) | 3 15 | 2019-06-26 14:53:07 | Wake Source | GPE # | 109 Change-Id: Ie9ef870e219733dea9806c766f5351db25689b32 Signed-off-by: Paul Fagerburg Reviewed-on: https://review.coreboot.org/c/coreboot/+/33843 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/cannonlake/Kconfig | 2 ++ src/soc/intel/cannonlake/elog.c | 17 +++++++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 37e42f30e2..d697620725 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -95,6 +95,8 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_PCH_BASE diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 2ec6b410df..141aa45b02 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -20,9 +20,22 @@ #include #include #include +#include #include #include +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x580 +#define XHCI_USB2_PORT_NUM 14 +#define XHCI_USB3_PORT_NUM 10 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -53,9 +66,9 @@ static void pch_log_wake_source(struct chipset_power_state *ps) if (ps->gpe0_sts[GPE_STD] & PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); - /* Internal PME (TODO: determine wake device) */ + /* XHCI - "Power Management Event Bus 0" events include XHCI */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + pch_xhci_update_wake_event(&usb_info); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) From 63f98f23045e072b0d07ecdd4cd50d01ad844df7 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 26 Jun 2019 20:17:50 +0200 Subject: [PATCH 031/231] src: Use CRx_TYPE type for CRx Change-Id: If50d9218119d5446d0ce98b8a9297b23bae65c72 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33816 Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/cpu/x86/lapic/lapic_cpu_init.c | 2 +- src/include/cpu/x86/cache.h | 4 ++-- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctsrc.c | 2 +- src/northbridge/amd/amdmct/mct/mcttmrl.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 5 +++-- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 7 ++++--- src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 4 ++-- src/soc/intel/quark/reg_access.c | 1 + 9 files changed, 16 insertions(+), 13 deletions(-) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 0f73e71331..cbbc10df31 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -417,7 +417,7 @@ asmlinkage void secondary_cpu_init(unsigned int index) * Seems that CR4 was cleared when AP start via lapic_start_cpu() * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled */ - u32 cr4_val; + CRx_TYPE cr4_val; cr4_val = read_cr4(); cr4_val |= (CR4_OSFXSR | CR4_OSXMMEXCPT); write_cr4(cr4_val); diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index c8d26abad4..7f135e5390 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -67,7 +67,7 @@ static inline void clflush(void *addr) */ static __always_inline void enable_cache(void) { - unsigned long cr0; + CRx_TYPE cr0; cr0 = read_cr0(); cr0 &= ~(CR0_CD | CR0_NW); write_cr0(cr0); @@ -76,7 +76,7 @@ static __always_inline void enable_cache(void) static __always_inline void disable_cache(void) { /* Disable and write back the cache */ - unsigned long cr0; + CRx_TYPE cr0; cr0 = read_cr0(); cr0 |= CR0_CD; wbinvd(); diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 36ee3ab332..2e52a39619 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -278,7 +278,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, u8 dqsWrDelay_end; u32 addr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; print_debug_dqs("\nTrainDQSRdWrPos: Node_ID ", pDCTstat->Node_ID, 0); diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 649c1c85c2..406547e0f8 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -129,7 +129,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, u32 index_reg; u32 ch_start, ch_end, ch; u32 msr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; u8 valid; diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index a78d42df85..6ec4d648d8 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -122,7 +122,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, u32 PatternBuffer[60]; // FIXME: why not 48 + 4 u32 Margin; u32 addr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; u8 valid; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 34b13ea306..6b31294586 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -405,7 +406,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, u32 dev; u32 addr; u8 valid; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; u32 index_reg; uint32_t TestAddr; @@ -1617,7 +1618,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, u8 _Wrap32Dis = 0, _SSE2 = 0; u32 addr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; uint8_t dct; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index a6faf90e0c..032152c39d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -612,7 +613,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, u32 index_reg; u32 ch_start, ch_end, ch; msr_t msr; - u32 cr4; + CRx_TYPE cr4; uint32_t dword; uint8_t dimm; @@ -1186,7 +1187,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, u32 index_reg; u32 ch_start, ch_end, ch; u32 msr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; uint32_t dword; @@ -1583,7 +1584,7 @@ void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, u32 index_reg; u32 ch_start, ch_end; u32 msr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; uint32_t dword; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index e7b7883f13..ec9b8e4327 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -21,7 +21,7 @@ #include #include #include - +#include #include "mct_d.h" #include "mct_d_gcc.h" @@ -119,7 +119,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, u32 PatternBuffer[60]; /* FIXME: why not 48 + 4 */ u32 Margin; u32 addr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; u8 valid; diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 1063525e03..5e5acd8266 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include From 4d4a13f7970c299bed278f2f098211cefaf17684 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 26 Jun 2019 12:26:29 +0200 Subject: [PATCH 032/231] drivers/pc80/rtc/mc146818rtc_boot: Use size_t for length Change-Id: I877e19c014759e33b9cc48ff9ee27e898737aece Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33805 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/drivers/pc80/rtc/mc146818rtc_boot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index 26bcac5acf..0ac06b3152 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -67,7 +67,7 @@ void sanitize_cmos(void) CBFS_COMPONENT_CMOS_DEFAULT, &length); #endif if (cmos_default) { - int i; + size_t i; cmos_disable_rtc(); for (i = 14; i < MIN(128, length); i++) cmos_write_inner(cmos_default[i], i); From 9d0b7b902106e898d44f2bfc9b944a2e0c9a4f27 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 10 Feb 2019 15:42:25 +0100 Subject: [PATCH 033/231] arch/riscv: Make RISCV specific options depend on ARCH_RISCV Also don't define the default as this results in spurious lines in the .config. The only difference in the generated config.h is that for most board ARCH_RISCV_M goes from 1 to 0. This should not matter. Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/31311 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/arch/riscv/Kconfig | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 25a398068a..a4f1788497 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -1,6 +1,15 @@ +config ARCH_RISCV_RV64 + bool + select ARCH_RISCV + +config ARCH_RISCV_RV32 + bool + select ARCH_RISCV + config ARCH_RISCV bool - default n + +if ARCH_RISCV config RISCV_ARCH string @@ -37,16 +46,6 @@ config ARCH_RISCV_U bool default n -config ARCH_RISCV_RV64 - bool - default n - select ARCH_RISCV - -config ARCH_RISCV_RV32 - bool - default n - select ARCH_RISCV - config ARCH_RISCV_PMP bool default n @@ -74,3 +73,5 @@ config RISCV_USE_ARCH_TIMER config RISCV_WORKING_HARTID int + +endif # if ARCH_RISCV From bf2c693f893ab6f9458f1a4840c2a9cbbd4bb9f2 Mon Sep 17 00:00:00 2001 From: Keith Short Date: Fri, 21 Jun 2019 16:39:59 -0600 Subject: [PATCH 034/231] libpayload/usb: Increase USB request timeout to 5 s Increase the timeout for USB requests to 5 seconds for all USB host controllers. Prior to this fix, the xCHI driver was detecting false timeouts during SET ADDRESS requests when nested downstream hubs were connected to the xHCI root hub. BUG=b:124730179 BRANCH=sarien TEST=Build libpayload and depthcharge on sarien/arcada. TEST=Without change replicate USB set address timeouts in depthcharge when dock and 4K monitor connected (which includes a total of 4 USB hubs). With timeout fix, depthcharge boots OS with no USB errors and the same USB topology. Note that this tests xHCI operation only. Change-Id: I53e3e67d893420e7c9e8b52c47dd0edb979e5468 Signed-off-by: Keith Short Reviewed-on: https://review.coreboot.org/c/coreboot/+/33671 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- payloads/libpayload/drivers/usb/dwc2.c | 17 +++++++++++------ payloads/libpayload/drivers/usb/ehci.c | 14 ++++---------- payloads/libpayload/drivers/usb/ohci.c | 11 +++++------ payloads/libpayload/drivers/usb/uhci.c | 8 +++++--- payloads/libpayload/drivers/usb/xhci_events.c | 14 ++++---------- payloads/libpayload/include/usb/usb.h | 18 ++++++++++++++++++ 6 files changed, 47 insertions(+), 35 deletions(-) diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c index 34de3bc42b..06c54e1030 100644 --- a/payloads/libpayload/drivers/usb/dwc2.c +++ b/payloads/libpayload/drivers/usb/dwc2.c @@ -146,6 +146,8 @@ static int dwc2_disconnected(hci_t *controller) return !(hprt.prtena && hprt.prtconnsts); } +#define DWC2_SLEEP_TIME_US 5 + /* * This function returns the actual transfer length when the transfer succeeded * or an error code if the transfer failed @@ -157,14 +159,14 @@ wait_for_complete(endpoint_t *ep, uint32_t ch_num) hcchar_t hcchar; hctsiz_t hctsiz; dwc2_reg_t *reg = DWC2_REG(ep->dev->controller); - int timeout = 600000; /* time out after 600000 * 5us == 3s */ + int timeout = USB_MAX_PROCESSING_TIME_US / DWC_SLEEP_TIME_US; /* * TODO: We should take care of up to three times of transfer error * retry here, according to the USB 2.0 spec 4.5.2 */ do { - udelay(5); + udelay(DWC_SLEEP_TIME_US); hcint.d32 = readl(®->host.hchn[ch_num].hcintn); hctsiz.d32 = readl(®->host.hchn[ch_num].hctsizn); @@ -374,12 +376,15 @@ static int dwc2_need_split(usbdev_t *dev, split_info_t *split) return 1; } +#define USB_FULL_LOW_SPEED_FRAME_US 1000 + static int dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, uint32_t ch_num, u8 *src, uint8_t skip_nak) { split_info_t split; - int ret, short_pkt, transferred = 0, timeout = 3000; + int ret, short_pkt, transferred = 0; + int timeout = USB_MAX_PROCESSING_TIME_US / USB_FULL_LOW_SPEED_FRAME_US; ep->toggle = pid; @@ -393,11 +398,11 @@ nak_retry: /* * dwc2_split_transfer() waits for the next FullSpeed - * frame boundary, so we have one try per millisecond. - * It's 3s timeout for each split transfer. + * frame boundary, so we only need to delay 500 us + * here to have one try per millisecond. */ if (ret == -HCSTAT_NAK && !skip_nak && --timeout) { - udelay(500); + udelay(USB_FULL_LOW_SPEED_FRAME_US / 2); goto nak_retry; } } else { diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 3d6c077b31..68763402af 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -247,6 +247,8 @@ static void free_qh_and_tds(ehci_qh_t *qh, qtd_t *cur) free((void *)qh); } +#define EHCI_SLEEP_TIME_US 50 + static int wait_for_tds(qtd_t *head) { /* returns the amount of bytes *not* transmitted, or -1 for error */ @@ -256,18 +258,10 @@ static int wait_for_tds(qtd_t *head) if (0) dump_td(virt_to_phys(cur)); /* wait for results */ - /* how long to wait? - * tested with some USB2.0 flash sticks: - * TUR turn around took - * about 2.2s for the slowest (13fe:3800) - * max. 250ms for the others - * slowest non-TUR turn around took about 1.3s - * set to 3s to be safe as a failed TUR can be fatal - */ - int timeout = 60000; /* time out after 60000 * 50us == 3s */ + int timeout = USB_MAX_PROCESSING_TIME_US / EHCI_SLEEP_TIME_US; while ((cur->token & QTD_ACTIVE) && !(cur->token & QTD_HALTED) && timeout--) - udelay(50); + udelay(EHCI_SLEEP_TIME_US); if (timeout < 0) { usb_debug("Error: ehci: queue transfer " "processing timed out.\n"); diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index ecd1084005..f1dc081656 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -292,14 +292,13 @@ ohci_stop (hci_t *controller) OHCI_INST (controller)->opreg->HcControl &= ~PeriodicListEnable; } +#define OHCI_SLEEP_TIME_US 1000 + static int wait_for_ed(usbdev_t *dev, ed_t *head, int pages) { /* wait for results */ - /* TOTEST: how long to wait? - * give 2s per TD (2 pages) plus another 2s for now - */ - int timeout = pages*1000 + 2000; + int timeout = USB_MAX_PROCESSING_TIME_US / OHCI_SLEEP_TIME_US; while (((head->head_pointer & ~3) != head->tail_pointer) && !(head->head_pointer & 1) && ((((td_t*)phys_to_virt(head->head_pointer & ~3))->config @@ -315,9 +314,9 @@ wait_for_ed(usbdev_t *dev, ed_t *head, int pages) ((td_t*)phys_to_virt(head->head_pointer & ~3))->next_td, head->tail_pointer, (((td_t*)phys_to_virt(head->head_pointer & ~3))->config & TD_CC_MASK) >> TD_CC_SHIFT); - mdelay(1); + udelay(OHCI_SLEEP_TIME_US); } - if (timeout < 0) + if (timeout <= 0) usb_debug("Error: ohci: endpoint " "descriptor processing timed out.\n"); /* Clear the done queue. */ diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index e62fd25a2d..32d40901a0 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -272,21 +272,23 @@ uhci_stop (hci_t *controller) uhci_reg_read16(controller, USBCMD) & ~1); // stop work on schedule } +#define UHCI_SLEEP_TIME_US 30 +#define UHCI_TIMEOUT (USB_MAX_PROCESSING_TIME_US / UHCI_SLEEP_TIME_US) #define GET_TD(x) ((void*)(((unsigned int)(x))&~0xf)) static td_t * wait_for_completed_qh (hci_t *controller, qh_t *qh) { - int timeout = 1000; /* max 30 ms. */ + int timeout = UHCI_TIMEOUT; void *current = GET_TD (qh->elementlinkptr); while (((qh->elementlinkptr & FLISTP_TERMINATE) == 0) && (timeout-- > 0)) { if (current != GET_TD (qh->elementlinkptr)) { current = GET_TD (qh->elementlinkptr); - timeout = 1000; + timeout = UHCI_TIMEOUT; } uhci_reg_write16(controller, USBSTS, uhci_reg_read16(controller, USBSTS) | 0); // clear resettable registers - udelay (30); + udelay(UHCI_SLEEP_TIME_US); } return (GET_TD (qh->elementlinkptr) == 0) ? 0 : GET_TD (phys_to_virt (qh->elementlinkptr)); diff --git a/payloads/libpayload/drivers/usb/xhci_events.c b/payloads/libpayload/drivers/usb/xhci_events.c index dacb5d8618..c21797de93 100644 --- a/payloads/libpayload/drivers/usb/xhci_events.c +++ b/payloads/libpayload/drivers/usb/xhci_events.c @@ -236,7 +236,7 @@ xhci_wait_for_command_aborted(xhci_t *const xhci, const trb_t *const address) * we don't get a response after 5s. Still, let the caller decide, * what to do then. */ - unsigned long timeout_us = 5 * 1000 * 1000; /* 5s */ + unsigned long timeout_us = USB_MAX_PROCESSING_TIME_US; /* 5s */ int cc = TIMEOUT; /* * Expects two command completion events: @@ -280,13 +280,7 @@ xhci_wait_for_command_done(xhci_t *const xhci, const trb_t *const address, const int clear_event) { - /* - * The Address Device Command should take most time, as it has to - * communicate with the USB device. Set address processing shouldn't - * take longer than 50ms (at the slave). Let's take a timeout of - * 100ms. - */ - unsigned long timeout_us = 100 * 1000; /* 100ms */ + unsigned long timeout_us = USB_MAX_PROCESSING_TIME_US; /* 5s */ int cc = TIMEOUT; while (xhci_wait_for_event_type(xhci, TRB_EV_CMD_CMPL, &timeout_us)) { if ((xhci->er.cur->ptr_low == virt_to_phys(address)) && @@ -311,8 +305,8 @@ int xhci_wait_for_transfer(xhci_t *const xhci, const int slot_id, const int ep_id) { xhci_spew("Waiting for transfer on ID %d EP %d\n", slot_id, ep_id); - /* 3s for all types of transfers */ /* TODO: test, wait longer? */ - unsigned long timeout_us = 3 * 1000 * 1000; + /* 5s for all types of transfers */ + unsigned long timeout_us = USB_MAX_PROCESSING_TIME_US; int ret = TIMEOUT; while (xhci_wait_for_event_type(xhci, TRB_EV_TRANSFER, &timeout_us)) { if (TRB_GET(ID, xhci->er.cur) == slot_id && diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index 79c4586c4a..db7ec57d57 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -71,6 +71,24 @@ typedef enum { /* SetAddress() recovery interval (USB 2.0 specification 9.2.6.3 */ #define SET_ADDRESS_MDELAY 2 +/* + * USB sets an upper limit of 5 seconds for any transfer to be completed. + * + * Data originally from EHCI driver: + * Tested with some USB2.0 flash sticks: + * TUR turn around took about 2.2s for the slowest (13fe:3800), maximum + * of 250ms for the others. + * + * SET ADDRESS on xHCI controllers. + * The USB specification indicates that devices must complete processing + * of a SET ADDRESS request within 50 ms. However, some hubs were found + * to take more than 100 ms to complete a SET ADDRESS request on a + * downstream port. + */ +#define USB_MAX_PROCESSING_TIME_US (5 * 1000 * 1000) + +#define USB_FULL_LOW_SPEED_FRAME_US 1000 + typedef struct { unsigned char bDescLength; unsigned char bDescriptorType; From 914e6b44bb189123cbc5555368d384c7ebf0e00c Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 1 Jul 2019 09:56:12 -0500 Subject: [PATCH 035/231] cpu/amd/msr: Clarify MMIO_CONF shift value MMIO_BUS_RANGE_SHIFT is a numerical value and not a bit field. Change it to simply 2. Otherwise its usage winds up evaluating to BusRange << (1 << 1). Signed-off-by: Marshall Dawson Change-Id: I2a6ecfc9fbfd45f69194b8daef43ff84a1dfd5fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/33942 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Richard Spiegel Reviewed-by: HAOUAS Elyes --- src/include/cpu/amd/msr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 5d7b5e4fda..0f88e516d1 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -39,7 +39,7 @@ #define MSR_INTPEND 0xC0010055 #define MMIO_CONF_BASE 0xC0010058 #define MMIO_RANGE_EN (1 << 0) -#define MMIO_BUS_RANGE_SHIFT (1 << 1) +#define MMIO_BUS_RANGE_SHIFT 2 /* P-state Current Limit Register */ #define PS_LIM_REG 0xC0010061 /* P-state Maximum Value shift position */ From 848e30daa1a82f401dad17c9bc93e7d0bb871833 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 18 Jun 2019 22:02:13 +0200 Subject: [PATCH 036/231] cbfstool: show "preserved" flag in cbfstool layout output The flag is useful for updaters to determine which areas to leave alone, such as VPD (vital product data) regions that are set in factory and might contain unique (MAC addresses) or hard to obtain (calibration output) data. It's also useful to see which regions are marked as such. Change-Id: Ic0a229d474b32ac156cfabc917714ce9d339bac6 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/33604 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Martin Roth --- util/cbfstool/cbfstool.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index cf89b473fa..54b5f6549c 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -1045,6 +1045,8 @@ static int cbfs_layout(void) qualifier = "read-only, "; else if (region_is_modern_cbfs((const char *)current->name)) qualifier = "CBFS, "; + else if (current->flags & FMAP_AREA_PRESERVE) + qualifier = "preserve, "; printf(" (%ssize %u, offset %u)\n", qualifier, current->size, current->offset); From d19fa78ae73b3b76986ce65c71e254d7b7717cb5 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 2 Jul 2019 13:35:22 -0500 Subject: [PATCH 037/231] arch/x86: Fix spelling error in BERT comment Signed-off-by: Marshall Dawson Change-Id: I57c0bcfbe0d96aac106f771e8efb3bd471302c25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33965 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/arch/x86/include/arch/bert_storage.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index c96918c990..5c87aed8b0 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -67,7 +67,7 @@ size_t bert_storage_remaining(void); /* Find if errors were added, a BERT region is present, and ACPI table needed */ int bert_errors_present(void); -/* Get the number of entries accociated with status */ +/* Get the number of entries associated with status */ static inline size_t bert_entry_count(acpi_generic_error_status_t *status) { return (status->block_status & GENERIC_ERR_STS_ENTRY_COUNT_MASK) From 275f7ba5ac9b11a9dc044e5d344f27e6948008d2 Mon Sep 17 00:00:00 2001 From: Akash Asthana Date: Mon, 24 Jun 2019 11:28:34 +0530 Subject: [PATCH 038/231] sdm845: Update macro definition in CB clock driver Use literals KHz & MHz for kilohertz and megahertz frequency usages in macro definition. Change-Id: If1ca6e5e7b0603f93f3c980cc85af470fdcd54ba Signed-off-by: Akash Asthana Reviewed-on: https://review.coreboot.org/c/coreboot/+/33811 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Paul Menzel --- src/soc/qualcomm/sdm845/include/soc/clock.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/qualcomm/sdm845/include/soc/clock.h b/src/soc/qualcomm/sdm845/include/soc/clock.h index 6aee9c14f3..ea4d87d812 100644 --- a/src/soc/qualcomm/sdm845/include/soc/clock.h +++ b/src/soc/qualcomm/sdm845/include/soc/clock.h @@ -30,9 +30,9 @@ #define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx) #define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx) -#define GPLL0_EVEN_HZ (300*Mhz) -#define GPLL0_MAIN_HZ (600*Mhz) -#define QUP_WRAP_CORE_2X_19_2MHZ (19200*Khz) +#define GPLL0_EVEN_HZ (300*MHz) +#define GPLL0_MAIN_HZ (600*MHz) +#define QUP_WRAP_CORE_2X_19_2MHZ (19200*KHz) #define SRC_XO_19_2MHZ 0 #define SRC_GPLL0_MAIN_600MHZ 1 From eda20b677f55707eb84c98bf04a15ec5b9eb3c33 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 1 Jul 2019 16:44:01 -0700 Subject: [PATCH 039/231] vboot: Use CONFIG_VBOOT_MIGRATE_WORKING_DATA on all platforms When we added CONFIG_VBOOT_MIGRATE_WORKING_DATA, the idea was that on some Arm platforms the original working data buffer was in SRAM, which stays accessbile for the whole runtime of the system. There is no reason to migrate it into CBMEM on those platforms because ramstage and the payload could continue to access it in SRAM. Now that we've had a couple of months of experience with this option, we found that most of our Arm platforms have some issue that requires migrating anyway, because BL31 often claims SRAM for itself and makes it inaccessible to the payload. On the remaining platforms, accessing SRAM from the payload is possible but still an issue, because libpayload doesn't have enough memory layout information to set up proper page tables for it, so we're accessing it uncached and at risk of alignment errors. Rather than having to figure out how to map the right SRAM range for every platform in the payload, let's just get rid of the option. memcpy()ing 12KB isn't worth this much hassle. Change-Id: I1b94e01c998f723c8950be4d12cc8f02b363a1bf Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/33952 Tested-by: build bot (Jenkins) Reviewed-by: Joel Kitching Reviewed-by: Paul Menzel Reviewed-by: Hung-Te Lin --- src/security/vboot/Kconfig | 15 --------------- src/security/vboot/common.c | 7 +++---- src/security/vboot/vboot_loader.c | 3 --- src/soc/qualcomm/qcs405/Kconfig | 1 - src/soc/qualcomm/sdm845/Kconfig | 1 - src/soc/rockchip/rk3399/Kconfig | 1 - 6 files changed, 3 insertions(+), 25 deletions(-) diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 66bcc1ed6f..ea1f73889a 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -107,21 +107,6 @@ config VBOOT_STARTS_IN_ROMSTAGE memory initialization). This implies that vboot working data is allocated in CBMEM. -config VBOOT_MIGRATE_WORKING_DATA - bool - default y if CACHE_AS_RAM - depends on !VBOOT_STARTS_IN_ROMSTAGE - help - In order to make vboot data structures available downstream, - migrate verified boot working data to CBMEM after CBMEM comes - online, when VBOOT_STARTS_IN_BOOTBLOCK is employed. This should - always be enabled on x86 architectures to migrate data from CAR - before losing access in ramstage, and should almost always be - disabled in SRAM architectures, where access to SRAM is usually - retained. Any SRAM platform where the original location of the - VBOOT_WORKBUF region becomes inaccessible in later stages should - manually select this option. - config VBOOT_MOCK_SECDATA bool "Mock secdata for firmware verification" default n diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index bd72683e00..626fbc52a4 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -117,13 +117,12 @@ int vboot_is_slot_selected(void) return reg->size > 0; } -#if CONFIG(VBOOT_MIGRATE_WORKING_DATA) +#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) /* * For platforms that do not employ VBOOT_STARTS_IN_ROMSTAGE, vboot * verification occurs before CBMEM is brought online, using pre-RAM. * In order to make vboot data structures available downstream, copy - * vboot_working_data from SRAM/CAR into CBMEM on platforms where this - * memory later becomes unavailable. + * vboot_working_data from SRAM/CAR into CBMEM. */ static void vboot_migrate_cbmem(int unused) { @@ -140,7 +139,7 @@ static void vboot_migrate_cbmem(int unused) memcpy(wd_cbmem, wd_preram, cbmem_size); } ROMSTAGE_CBMEM_INIT_HOOK(vboot_migrate_cbmem) -#elif CONFIG(VBOOT_STARTS_IN_ROMSTAGE) +#else static void vboot_setup_cbmem(int unused) { struct vboot_working_data *wd_cbmem = diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 9e2cd00404..af4a3fd880 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -26,9 +26,6 @@ _Static_assert(CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) + CONFIG(VBOOT_STARTS_IN_ROMSTAGE) == 1, "vboot must either start in bootblock or romstage (not both!)"); -_Static_assert(CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) || - !CONFIG(VBOOT_MIGRATE_WORKING_DATA), - "no need to migrate working data after CBMEM is already up!"); _Static_assert(!CONFIG(VBOOT_SEPARATE_VERSTAGE) || CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), "stand-alone verstage must start in (i.e. after) bootblock"); diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index e24993a2f0..aa867c2f25 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -19,7 +19,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_MIGRATE_WORKING_DATA config QCS405_BLSP_SPI bool diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig index f6268c95ba..459a4411b2 100644 --- a/src/soc/qualcomm/sdm845/Kconfig +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -19,7 +19,6 @@ config VBOOT select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_MIGRATE_WORKING_DATA config SDM845_QSPI bool diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig index 897a5979d4..83fc437073 100644 --- a/src/soc/rockchip/rk3399/Kconfig +++ b/src/soc/rockchip/rk3399/Kconfig @@ -17,7 +17,6 @@ config SOC_ROCKCHIP_RK3399 if SOC_ROCKCHIP_RK3399 config VBOOT - select VBOOT_MIGRATE_WORKING_DATA select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY From 593d1cf81725506315b5e647342318228fc1889e Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Mon, 1 Jul 2019 16:11:29 +0800 Subject: [PATCH 040/231] mb/google/octopus: Add custom SAR values for Blooguard Google project name is Bloog. Bloog is 12-inch LCD. Blooguard is 14-inch LCD so would prefer to use a different SAR values instead. Use sku-id to load the SAR values. BUG=b:135078377 BRANCH=octopus TEST=build and verify SAR load by sku-id Change-Id: Id80df28a961eb1f62714558df2b219aa552ecb97 Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/33935 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Karthik Ramasubramanian --- .../octopus/variants/bloog/Makefile.inc | 1 + .../google/octopus/variants/bloog/variant.c | 36 +++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 src/mainboard/google/octopus/variants/bloog/variant.c diff --git a/src/mainboard/google/octopus/variants/bloog/Makefile.inc b/src/mainboard/google/octopus/variants/bloog/Makefile.inc index 9fb63f5f43..ba865e9f82 100644 --- a/src/mainboard/google/octopus/variants/bloog/Makefile.inc +++ b/src/mainboard/google/octopus/variants/bloog/Makefile.inc @@ -1,3 +1,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/octopus/variants/bloog/variant.c b/src/mainboard/google/octopus/variants/bloog/variant.c new file mode 100644 index 0000000000..58b3bc4cd2 --- /dev/null +++ b/src/mainboard/google/octopus/variants/bloog/variant.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#define SKU_UNKNOWN 0xFFFFFFFF + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + uint32_t sku_id; + sku_id = get_board_sku(); + + if (sku_id == SKU_UNKNOWN) + return NULL; + + if (sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52) + filename = "wifi_sar-blooguard.hex"; + + return filename; +} From 84133b161c8be7cbb41fdbdb0196fd42375e141a Mon Sep 17 00:00:00 2001 From: Chris Zhou Date: Wed, 26 Jun 2019 16:54:19 +0800 Subject: [PATCH 041/231] mb/google/octopus/variants/fleex: Enable EMR function for Grob360S Enable EMR Pen Stylus function for Grob360S BUG=b:135968368 BRANCH=octopus TEST=EMR function working normally with HW reworked Fleex. Change-Id: Ia220dc0d3051b79b110b4df66df108f701776478 Signed-off-by: Chris Zhou Reviewed-on: https://review.coreboot.org/c/coreboot/+/33802 Reviewed-by: EricR Lai Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- .../google/octopus/variants/fleex/gpio.c | 3 ++- .../octopus/variants/fleex/overridetree.cb | 18 +++++++++++++++++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 89adfb8cb6..d2d0d641dc 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -30,7 +30,8 @@ static const struct pad_config default_override_table[] = { PAD_NC(GPIO_138, UP_20K), PAD_NC(GPIO_139, UP_20K), - PAD_NC(GPIO_140, UP_20K), + /* GPIO_140 -- PEN_RESET */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), PAD_NC(GPIO_143, UP_20K), PAD_NC(GPIO_144, UP_20K), PAD_NC(GPIO_145, UP_20K), diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 19246e0a51..da4e701641 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -61,6 +61,9 @@ chip soc/intel/apollolake .speed_mhz = 1, .early_init = 1, }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, .i2c[5] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 104, @@ -80,7 +83,20 @@ chip soc/intel/apollolake }" device domain 0 on - device pci 16.0 off end # - I2C 0 + device pci 16.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 0 device pci 16.1 off end # - I2C 1 device pci 17.1 on chip drivers/i2c/da7219 From 19476c34b0ce20c966d0461ec4d4bb689fce8f35 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Mon, 17 Jun 2019 16:18:27 +0800 Subject: [PATCH 042/231] mb/google/octopus: Override DDI1 DDC SDA/SCL for Garg HDMI garg 2A2C DB: SKU ID - 1 garg HDMI DB: SKU ID - 9 garg LTE DB: SKU ID - 17 For HDMI SKU9, GPIO needs to be overriden to enable DDI1 DDC SDA/SCL. BUG=b:134912735 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: I6ad8e5aa52f503121b10fe353e4bf4021aee2061 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/33552 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian Reviewed-by: Justin TerAvest --- .../google/octopus/variants/garg/gpio.c | 35 +++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index a4362409b5..90601ce850 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -19,6 +19,12 @@ #include #include +enum { + SKU_1_2A2C = 1, + SKU_9_HDMI = 9, + SKU_17_LTE = 17, +}; + static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), @@ -29,9 +35,34 @@ static const struct pad_config default_override_table[] = { PAD_NC(GPIO_213, DN_20K), }; +static const struct pad_config hdmi_override_table[] = { + PAD_NC(GPIO_104, UP_20K), + + /* HV_DDI1_DDC_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, NONE, DEEP, NF1, HIZCRx1, + DISPUPD), + /* HV_DDI1_DDC_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, NONE, DEEP, NF1, HIZCRx1, + DISPUPD), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_213, DN_20K), +}; + const struct pad_config *variant_override_gpio_table(size_t *num) { - *num = ARRAY_SIZE(default_override_table); + uint32_t sku_id; + sku_id = get_board_sku(); - return default_override_table; + switch (sku_id) { + case SKU_9_HDMI: + *num = ARRAY_SIZE(hdmi_override_table); + return hdmi_override_table; + default: + *num = ARRAY_SIZE(default_override_table); + return default_override_table; + } } From 2020cbb6ed45a282d1236dca91dce86d03360132 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 3 Jul 2019 10:20:40 +0200 Subject: [PATCH 043/231] soc/intel/skylake: Add Kabylake-R microcode update files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This also corrects some CPU naming in comments. Change-Id: I8b9fc3ba0d6dc6e0001b40518aae2d26c1184dc8 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/34000 Reviewed-by: Nico Huber Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/Makefile.inc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 25dce05226..20fba29116 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -84,13 +84,15 @@ postcar-y += uart.c ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y) # Skylake H Q0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5e-03 -# Kabylake HB0 +# Kabylake H B0 S0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-09 else # Skylake D0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-4e-03 -# Kabylake H0, Y0 +# Kabylake H0, J0, J1 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-09 +# Kabylake Y0 +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0a endif # Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8) # since those are probably pre-release samples. From a8dc3f58a9d47f644818551123fc16948d203131 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 2 Jul 2019 15:19:26 +0300 Subject: [PATCH 044/231] intel/e7505: Drop debug code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only (conditionally) used part was dump_pci_device() and that was never particularly useful either. Change-Id: Iaacfa511de1ce1e0bdbd2e8a74e41d336e505670 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/33958 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/e7505/Makefile.inc | 1 - src/northbridge/intel/e7505/debug.c | 186 ----------------------- src/northbridge/intel/e7505/debug.h | 26 ---- src/northbridge/intel/e7505/raminit.c | 9 -- 4 files changed, 222 deletions(-) delete mode 100644 src/northbridge/intel/e7505/debug.c delete mode 100644 src/northbridge/intel/e7505/debug.h diff --git a/src/northbridge/intel/e7505/Makefile.inc b/src/northbridge/intel/e7505/Makefile.inc index 7f7c5e40aa..4eda3d1049 100644 --- a/src/northbridge/intel/e7505/Makefile.inc +++ b/src/northbridge/intel/e7505/Makefile.inc @@ -4,7 +4,6 @@ ramstage-y += northbridge.c ramstage-y += memmap.c romstage-y += raminit.c -romstage-y += debug.c romstage-y += memmap.c postcar-y += memmap.c diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c deleted file mode 100644 index 357a9633b6..0000000000 --- a/src/northbridge/intel/e7505/debug.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include "raminit.h" -#include "debug.h" - -/* - * generic debug code, used by mainboard specific romstage.c - * - */ - -void print_debug_pci_dev(unsigned dev) -{ - printk(BIOS_DEBUG, "PCI: %02x:%02x.%x", - (dev >> 16) & 0xff, (dev >> 11) & 0x1f, (dev >> 8) & 7); -} - -void print_pci_devices(void) -{ - pci_devfn_t dev; - for (dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - printk(BIOS_DEBUG, "\n"); - } -} - -void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - - for (i = 0; i < 256; i++) { - unsigned char val; - if ((i & 0x0f) == 0) - printk(BIOS_DEBUG, "\n%02x:",i); - val = pci_read_config8(dev, i); - printk(BIOS_DEBUG, " %02x", val); - } - printk(BIOS_DEBUG, "\n"); -} - -void dump_pci_devices(void) -{ - pci_devfn_t dev; - for (dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - -void dump_pci_devices_on_bus(unsigned busn) -{ - pci_devfn_t dev; - for (dev = PCI_DEV(busn, 0, 0); - dev <= PCI_DEV(busn, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - -void dump_spd_registers(const struct mem_controller *ctrl) -{ - int i; - printk(BIOS_DEBUG, "\n"); - for (i = 0; i < 4; i++) { - unsigned device; - device = ctrl->channel0[i]; - if (device) { - int j; - printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device); - for (j = 0; j < 128; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) - printk(BIOS_DEBUG, "\n%02x: ", j); - status = spd_read_byte(device, j); - if (status < 0) { - break; - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } - device = ctrl->channel1[i]; - if (device) { - int j; - printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); - for (j = 0; j < 128; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) - printk(BIOS_DEBUG, "\n%02x: ", j); - status = spd_read_byte(device, j); - if (status < 0) { - break; - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } - } -} -void dump_smbus_registers(void) -{ - unsigned device; - printk(BIOS_DEBUG, "\n"); - for (device = 1; device < 0x80; device++) { - int j; - if (spd_read_byte(device, 0) < 0) - continue; - printk(BIOS_DEBUG, "smbus: %02x", device); - for (j = 0; j < 256; j++) { - int status; - unsigned char byte; - status = spd_read_byte(device, j); - if (status < 0) { - break; - } - if ((j & 0xf) == 0) - printk(BIOS_DEBUG, "\n%02x: ",j); - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } -} - -void dump_io_resources(unsigned port) -{ - int i; - printk(BIOS_DEBUG, "%04x:\n", port); - for (i = 0; i < 256; i++) { - uint8_t val; - if ((i & 0x0f) == 0) - printk(BIOS_DEBUG, "%02x:", i); - val = inb(port); - printk(BIOS_DEBUG, " %02x",val); - if ((i & 0x0f) == 0x0f) { - printk(BIOS_DEBUG, "\n"); - } - port++; - } -} diff --git a/src/northbridge/intel/e7505/debug.h b/src/northbridge/intel/e7505/debug.h deleted file mode 100644 index 98ca848ea0..0000000000 --- a/src/northbridge/intel/e7505/debug.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef E7505_DEBUG_H -#define E7505_DEBUG_H - -void print_debug_pci_dev(unsigned dev); -void print_pci_devices(void); -void dump_pci_device(unsigned dev); -void dump_pci_devices(void); -void dump_pci_devices_on_bus(unsigned busn); -void dump_spd_registers(const struct mem_controller *ctrl); -void dump_smbus_registers(void); -void dump_io_resources(unsigned port); - -#endif diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 3bb1f67b59..8a336e6f0a 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -43,7 +43,6 @@ #include "raminit.h" #include "e7505.h" -#include "debug.h" /*----------------------------------------------------------------------------- Definitions: @@ -58,12 +57,10 @@ Definitions: #define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x) #define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x) #define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x) -#define DUMPNORTH() dump_pci_device(MCHDEV) #else #define RAM_DEBUG_MESSAGE(x) #define RAM_DEBUG_HEX32(x) #define RAM_DEBUG_HEX8(x) -#define DUMPNORTH() #endif #define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4) @@ -1768,9 +1765,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl) */ void e7505_mch_init(const struct mem_controller *memctrl) { - RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); - DUMPNORTH(); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_set_registers(memctrl); @@ -1783,9 +1777,6 @@ void e7505_mch_done(const struct mem_controller *memctrl) sdram_post_ecc(memctrl); timestamp_add_now(TS_AFTER_INITRAM); - - RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n"); - DUMPNORTH(); } int e7505_mch_is_ready(void) From 810e566c8019f5da2f215bf5a257525ac216dfe5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 3 Jul 2019 09:12:39 +0300 Subject: [PATCH 045/231] aopen/dxplplusu: Remove PIRQ table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It was never tested or injected. Change-Id: I3fd82aaa11afc5adab212ec6709580b4bcc67ca3 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34001 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/aopen/dxplplusu/Kconfig | 2 - src/mainboard/aopen/dxplplusu/irq_tables.c | 72 ---------------------- 2 files changed, 74 deletions(-) delete mode 100644 src/mainboard/aopen/dxplplusu/irq_tables.c diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index 905ddd5800..7dc0eab674 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -7,8 +7,6 @@ config BOARD_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_I82870 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_LPC47M10X -# select HAVE_PIRQ_TABLE -# select PIRQ_ROUTE select UDELAY_TSC select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 diff --git a/src/mainboard/aopen/dxplplusu/irq_tables.c b/src/mainboard/aopen/dxplplusu/irq_tables.c deleted file mode 100644 index b7e1187162..0000000000 --- a/src/mainboard/aopen/dxplplusu/irq_tables.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Kyösti Mälkki - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "bus.h" - -#define UNUSED_INTERRUPT {0, 0} -#define PIRQ_A 0x60 -#define PIRQ_B 0x61 -#define PIRQ_C 0x62 -#define PIRQ_D 0x63 -#define PIRQ_E 0x68 -#define PIRQ_F 0x69 -#define PIRQ_G 0x6A -#define PIRQ_H 0x6B - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Size of this struct in bytes */ - 0, /* PCI bus number on which the interrupt router resides */ - PCI_DEVFN(31, 0), /* PCI device/function number of the interrupt router */ - 0, /* PCI-exclusive IRQ bitmap */ - PCI_VENDOR_ID_INTEL, /* Vendor ID of compatible PCI interrupt router */ - PCI_DEVICE_ID_INTEL_82801DB_LPC, /* Device ID of compatible PCI interrupt router */ - 0, /* Additional miniport information */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* Reserved, must be zero */ - 0xB1, /* Checksum of the entire structure (causes 8-bit sum == 0) */ - { - /* NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space */ - /* This was determined from linux-2.6.11/arch/i386/pci/irq.c */ - /* bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15 */ - /* ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13 */ - /* Not sure why IRQ9 isn't routable (inherited from Tyan S2735) */ - - /* INTA# INTB# INTC# INTD# */ - /* bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu */ - - {PCI_BUS_ROOT, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, /* IDE / SMBus */ - {PCI_BUS_ROOT, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, /* USB 1.1 */ - - {PCI_BUS_P64H2_B, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, - {PCI_BUS_P64H2_B, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, - {PCI_BUS_P64H2_B, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, /* GbE */ - - {PCI_BUS_P64H2_A, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, - {PCI_BUS_P64H2_A, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, - {PCI_BUS_P64H2_A, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, /* SCSI */ - - {PCI_BUS_ICH4, PCI_DEVFN(3, 0), {{PIRQ_E, 0xdcf8}, {PIRQ_F, 0xdcf8}, {PIRQ_G, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, /* 32-bit slot */ - - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} From 5e4a26a76e5ec342e10a5c8ce2ff26eb03bb5bc2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 3 Jul 2019 07:50:45 +0300 Subject: [PATCH 046/231] aopen/dxplplusu: Replace use of dev_find_slot() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To use fixed PCI bus numbers is always invalid. Change-Id: Ia2ffdb1f5e0ff398674a016ad4cb94f622c057ff Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34002 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/aopen/dxplplusu/acpi_tables.c | 43 +++++++++++++-------- src/mainboard/aopen/dxplplusu/bus.h | 39 ------------------- 2 files changed, 26 insertions(+), 56 deletions(-) delete mode 100644 src/mainboard/aopen/dxplplusu/bus.h diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index 039e4ecc6a..cc6835b939 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -20,13 +20,17 @@ #include #include -#include -#include "bus.h" + +#define IOAPIC_ICH4 2 +#define IOAPIC_P64H2_BUS_B 3 /* IOAPIC 3 at 02:1c.0 */ +#define IOAPIC_P64H2_BUS_A 4 /* IOAPIC 4 at 02:1e.0 */ + +#define INTEL_IOAPIC_NUM_INTERRUPTS 24 /* Both ICH-4 and P64-H2 */ unsigned long acpi_fill_madt(unsigned long current) { unsigned int irq_start = 0; - struct device *dev = NULL; + struct device *bdev, *dev = NULL; struct resource* res = NULL; /* SJM: Hard-code CPU LAPIC entries for now */ @@ -36,25 +40,30 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7); /* Southbridge IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4, 0xfec00000, irq_start); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4, + 0xfec00000, irq_start); irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + bdev = pcidev_on_root(2, 0); /* P64H2 Bus B IOAPIC */ - dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); - if (!dev) - BUG(); /* Config.lb error? */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_B, res->base, irq_start); - irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + if (bdev) + dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(28, 0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + IOAPIC_P64H2_BUS_B, res->base, irq_start); + irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + } /* P64H2 Bus A IOAPIC */ - dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); - if (!dev) - BUG(); /* Config.lb error? */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_A, res->base, irq_start); - irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; - + if (bdev) + dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(28, 0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + IOAPIC_P64H2_BUS_A, res->base, irq_start); + irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + } /* Map ISA IRQ 0 to IRQ 2 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0); diff --git a/src/mainboard/aopen/dxplplusu/bus.h b/src/mainboard/aopen/dxplplusu/bus.h deleted file mode 100644 index 12eef12381..0000000000 --- a/src/mainboard/aopen/dxplplusu/bus.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Kyösti Mälkki - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef DXPLPLUSU_BUS_H_INCLUDED -#define DXPLPLUSU_BUS_H_INCLUDED - -/* These were determined by seeing how coreboot enumerates the various - * PCI (and PCI-like) buses on the board. - */ - -#define PCI_BUS_ROOT 0 -#define PCI_BUS_AGP 1 /* AGP */ -#define PCI_BUS_E7501_HI_B 2 /* P64H2#1 */ -#define PCI_BUS_P64H2_B 3 /* P64H2#1 bus B */ -#define PCI_BUS_P64H2_A 4 /* P64H2#1 bus A */ -#define PCI_BUS_ICH4 5 /* ICH4 */ - -/* IOAPIC addresses determined by coreboot enumeration. */ -/* Someday add functions to get APIC IDs and versions from the chips themselves. */ - -#define IOAPIC_ICH4 2 -#define IOAPIC_P64H2_BUS_B 3 /* IOAPIC 3 at 02:1c.0 MBAR = fe300000 DataAddr = fe300010 */ -#define IOAPIC_P64H2_BUS_A 4 /* IOAPIC 4 at 02:1e.0 MBAR = fe301000 DataAddr = fe301010 */ - -#define INTEL_IOAPIC_NUM_INTERRUPTS 24 /* Both ICH-4 and P64-H2 */ - -#endif From 30cf1551683810504f7823e42d4cb6515459cff8 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 19 Mar 2019 14:48:33 -0600 Subject: [PATCH 047/231] util/cbfstool: Add AMD BIOS compression tool for PSP Add a utility to generate a compressed BIOS image for AMD Family 17h. If the input is an elf file, the utility extracts the program portion for compression. Otherwise the file is compressed as-is. In modern AMD systems, the PSP brings up DRAM then uncompresses the BIOS image into memory prior to x86 beginning execution. The PSP supports a zlib engine, and interprets the first 256 bytes as a header, where offset 0x14 containing the uncompressed size. For further details, see AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:127766506 TEST=Use with WIP Picasso Change-Id: Id1c54e0a6dae9e4a0362c6635fe8b8aa48a369d8 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/33401 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Edward O'Callaghan --- Makefile.inc | 6 +- util/cbfstool/Makefile.inc | 10 + util/cbfstool/amdcompress.c | 364 ++++++++++++++++++++++++++++++++++++ 3 files changed, 379 insertions(+), 1 deletion(-) create mode 100644 util/cbfstool/amdcompress.c diff --git a/Makefile.inc b/Makefile.inc index 362243eb6a..28f1363131 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -514,6 +514,7 @@ FMAPTOOL:=$(objutil)/cbfstool/fmaptool RMODTOOL:=$(objutil)/cbfstool/rmodtool IFWITOOL:=$(objutil)/cbfstool/ifwitool IFITTOOL:=$(objutil)/cbfstool/ifittool +AMDCOMPRESS:=$(objutil)/cbfstool/amdcompress $(obj)/cbfstool: $(CBFSTOOL) cp $< $@ @@ -530,6 +531,9 @@ $(obj)/ifwitool: $(IFWITOOL) $(obj)/ifittool: $(IFITTOOL) cp $< $@ +$(obj)/amdcompress: $(AMDCOMPRESS) + cp $< $@ + _WINCHECK=$(shell uname -o 2> /dev/null) STACK= ifeq ($(_WINCHECK),Msys) @@ -642,7 +646,7 @@ install-git-commit-clangfmt: include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) $(BINCFG) $(IFITTOOL) +tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) ########################################################################### # Common recipes for all stages diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index efc3dca6f5..95372c2988 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -98,6 +98,12 @@ cbfscompobj := cbfscompobj += $(compressionobj) cbfscompobj += cbfscomptool.o +amdcompobj := +amdcompobj += amdcompress.o +amdcompobj += elfheaders.o +amdcompobj += common.o +amdcompobj += xdr.o + TOOLCFLAGS ?= -Werror -Wall -Wextra TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings @@ -185,6 +191,10 @@ $(objutil)/cbfstool/cbfs-compression-tool: $(addprefix $(objutil)/cbfstool/,$(cb printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(cbfscompobj)) +$(objutil)/cbfstool/amdcompress: $(addprefix $(objutil)/cbfstool/,$(amdcompobj)) + printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" + $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(amdcompobj)) -lz + # Yacc source is superset of header $(objutil)/cbfstool/fmd.o: TOOLCFLAGS += -Wno-redundant-decls $(objutil)/cbfstool/fmd_parser.o: TOOLCFLAGS += -Wno-redundant-decls diff --git a/util/cbfstool/amdcompress.c b/util/cbfstool/amdcompress.c new file mode 100644 index 0000000000..641e1ea6c0 --- /dev/null +++ b/util/cbfstool/amdcompress.c @@ -0,0 +1,364 @@ +/* + * AMD Family 17h and later BIOS compressor + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include "zlib.h" + +#define DEBUG_FILE 0 + +#define HDR_SIZE 256 +#define UNCOMP_MAX 0x300000 + +#define DIR_UNDEF 0 +#define DIR_COMP 1 +#define DIR_UNCOMP 2 + +typedef struct _header { + uint32_t rsvd1[5]; + uint32_t size; + uint32_t rsvd2[58]; +} __attribute__((packed)) header; + +static const char *optstring = "i:o:cm:uh"; + +static struct option long_options[] = { + {"infile", required_argument, 0, 'i' }, + {"outfile", required_argument, 0, 'o' }, + {"compress", required_argument, 0, 'c' }, + {"maxsize", required_argument, 0, 'h' }, + {"uncompress", required_argument, 0, 'u' }, + {"help", no_argument, 0, 'h' }, +}; + +static void usage(void) +{ + printf(": Extract or create a zlib compressed BIOS binary\n"); + printf(" image. A compressed image contains a 256 byte\n"); + printf(" header with a 32-bit size at 0x14.\n"); + printf("Usage: -i in_file -o out_file -[c|u]\n"); + printf("-i | --infile Input file\n"); + printf("-o | --outfile Output file\n"); + printf("-c | --compress Compress\n"); + printf("-m | --maxsize Maximum uncompressed size (optional)\n"); + printf(" * On compress: verify uncompressed size\n"); + printf(" will be less than or equal maxsize\n"); + printf(" * On uncompress: override default buffer size\n"); + printf(" allocation of 0x%x bytes\n", UNCOMP_MAX); + printf("-u | --uncompress Uncompress\n"); + printf("-h | --help Display this message\n"); + + exit(1); +} + +static int do_file(char *name, size_t *size, int oflag) +{ + struct stat fd_stat; + int fd; + + fd = open(name, oflag, 0666); + if (fd < 0) + return -1; + + if (fstat(fd, &fd_stat)) { + close(fd); + return -1; + } + + if (size) + *size = fd_stat.st_size; + return fd; +} + +static int parse_elf_to_xip_ram(const struct buffer *input, + struct buffer *output) +{ + struct parsed_elf pelf; + + if (parse_elf(input, &pelf, ELF_PARSE_ALL)) + return 1; + if (buffer_create(output, pelf.phdr->p_filesz, "") != 0) + return 1; + + memcpy(output->data, input->data + pelf.phdr->p_offset, output->size); + + return 0; +} + +static int convert_elf(struct buffer *buf) +{ + struct buffer out; + + if (parse_elf_to_xip_ram(buf, &out)) { + printf("\tError parsing ELF file\n"); + return -1; + } + + /* Discard the elf file in buf and replace with the progbits */ + free(buf->data); + buf->data = out.data; + buf->size = out.size; + + return 0; +} + +static int iself(const void *input) +{ + const Elf32_Ehdr *ehdr = input; + return !memcmp(ehdr->e_ident, ELFMAG, 4); +} + +/* todo: Consider using deflate() and inflate() instead of compress() and + * decompress(), especially if memory allocation somehow becomes a problem. + * Those two functions can operate on streams and process chunks of data. + */ + +/* Build the required header and follow it with the compressed image. Detect + * whether the input is an elf image, and if so, compress only the progbits. + * + * header + * 0 +------+-------+-------+-------+ + * | | | | | + * +----------------------+-------+ + * | | size | | | + * +----------------------+-------+ + * | | | | | + * | | | ... | + * 256 +------------------------------+ + * |compressed image | + * | ... | + * | ... | + * | ... | + * n +------------------------------+ + */ +static void do_compress(char *outf, char *inf, size_t max_size) +{ + int out_fd, in_fd; + struct buffer inbf, outbf; + int err; + + in_fd = do_file(inf, &inbf.size, O_RDONLY); + if (in_fd < 0) { + printf("\tError opening input file %s\n", inf); + err = 1; + goto out; + } + + out_fd = do_file(outf, 0, O_CREAT | O_WRONLY); + if (out_fd < 0) { + printf("\tError opening output file %s\n", outf); + err = 1; + goto out_close_in; + } + + inbf.data = calloc(inbf.size, 1); + if (!inbf.data) { + printf("\tError allocating 0x%zx bytes for input buffer\n", inbf.size); + err = 1; + goto out_close_out; + } + + if (read(in_fd, inbf.data, inbf.size) != (ssize_t)inbf.size) { + printf("\tError reading input file %s\n", inf); + err = 1; + goto out_free_in; + } + + if (iself(inbf.data)) { + if (convert_elf(&inbf)) { + err = 1; + goto out_free_in; + } + } + + if (max_size && inbf.size > max_size) { + printf("\tError - size (%zx) exceeds specified max_size (%zx)\n", + inbf.size, max_size); + err = 1; + goto out_free_in; + } + + outbf.size = inbf.size; /* todo: tbd worst case? */ + outbf.size += sizeof(header); + outbf.data = calloc(outbf.size, 1); + if (!outbf.size) { + printf("\tError allocating 0x%zx bytes for output buffer\n", outbf.size); + err = 1; + goto out_free_in; + } + + err = compress((Bytef *)(outbf.data + sizeof(header)), &outbf.size, + (Bytef *)inbf.data, inbf.size); + if (err != Z_OK) { + printf("\tzlib compression error %d\n", err); + err = 1; + goto out_free_out; + } + + if (DEBUG_FILE) + printf("\tCompressed 0x%zx bytes into 0x%zx\n", inbf.size, + outbf.size - sizeof(header)); + + ((header *)outbf.data)->size = outbf.size; + + if (write(out_fd, outbf.data, outbf.size + sizeof(header)) + != (ssize_t)(outbf.size + sizeof(header))) { + printf("\tError writing to %s\n", outf); + err = 1; + /* fall through to out_free_out */ + } + +out_free_out: + free(outbf.data); +out_free_in: + free(inbf.data); +out_close_out: + close(out_fd); +out_close_in: + close(in_fd); +out: + if (err) + exit(err); +} + +static void do_uncompress(char *outf, char *inf, size_t max_size) +{ + int out_fd, in_fd; + char *in_buf, *out_buf; + size_t size_unc, size_comp; + size_t bytes; + int err; + + in_fd = do_file(inf, &size_comp, O_RDONLY); + if (in_fd < 0) { + printf("\tError opening input file %s\n", inf); + err = 1; + goto out; + } + + out_fd = do_file(outf, 0, O_CREAT | O_WRONLY); + if (out_fd < 0) { + printf("\tError opening output file %s\n", outf); + err = 1; + goto out_close_in; + } + + in_buf = calloc(size_comp, 1); + if (!in_buf) { + printf("\tError allocating 0x%zx bytes for input buffer\n", size_comp); + err = 1; + goto out_close_out; + } + + bytes = read(in_fd, in_buf, size_comp); + if (bytes != size_comp) { + printf("\tError reading input file %s\n", inf); + err = 1; + goto out_free_in; + } + + size_comp = ((header *)in_buf)->size; + + size_unc = max_size ? max_size : UNCOMP_MAX; + out_buf = calloc(size_unc, 1); + if (!out_buf) { + printf("\tError allocating 0x%zx bytes for output buffer\n", size_unc); + err = 1; + goto out_free_in; + } + + err = uncompress((Bytef *)out_buf, &size_unc, + (Bytef *)in_buf + sizeof(header), size_comp); + if (err != Z_OK) { + printf("\tzlib uncompression error %d\n", err); + err = 1; + goto out_free_out; + } + + if (DEBUG_FILE) + printf("Uncompressed 0x%zx bytes into 0x%zx\n", size_comp, size_unc); + + bytes = write(out_fd, out_buf, size_unc); + if (bytes != size_unc) { + printf("\tError writing to %s\n", outf); + err = 1; + /* fall through to out_free_out */ + } + +out_free_out: + free(out_buf); +out_free_in: + free(in_buf); +out_close_out: + close(out_fd); +out_close_in: + close(in_fd); +out: + if (err) + exit(err); +} + +int main(int argc, char *argv[]) +{ + int c; + char *inf = 0, *outf = 0, *scratch; + int direction = DIR_UNDEF; + size_t max_size = 0; + + while (1) { + int optindex = 0; + + c = getopt_long(argc, argv, optstring, long_options, &optindex); + if (c == -1) + break; + + switch (c) { + case 'i': + inf = optarg; + break; + case 'o': + outf = optarg; + break; + case 'c': + if (direction != DIR_UNDEF) + usage(); + direction = DIR_COMP; + break; + case 'u': + if (direction != DIR_UNDEF) + usage(); + direction = DIR_UNCOMP; + break; + case 'm': + max_size = strtoull(optarg, &scratch, 16); + break; + case 'h': + usage(); + } + } + if (!inf || !outf || direction == DIR_UNDEF) + usage(); + + if (direction == DIR_COMP) + do_compress(outf, inf, max_size); + else + do_uncompress(outf, inf, max_size); + + return 0; +} From bc4c903c1f0bbf5297309082f31cfc2f70addb99 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 11 Jun 2019 12:18:20 -0600 Subject: [PATCH 048/231] soc/amd/picasso: Change all remaining soc names Convert all remaining stoneyridge names to picasso. Change-Id: I0ed3eaa5b1d2696448ae18b62c7218de59c61883 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/33749 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/soc/amd/picasso/Kconfig | 34 +++++++++---------- src/soc/amd/picasso/Makefile.inc | 20 +++++------ src/soc/amd/picasso/acpi.c | 4 +-- src/soc/amd/picasso/chip.c | 10 +++--- src/soc/amd/picasso/chip.h | 8 ++--- src/soc/amd/picasso/cpu.c | 2 +- src/soc/amd/picasso/i2c.c | 10 +++--- src/soc/amd/picasso/include/soc/acpi.h | 2 +- src/soc/amd/picasso/include/soc/cpu.h | 2 +- src/soc/amd/picasso/include/soc/iomap.h | 12 +++---- src/soc/amd/picasso/include/soc/southbridge.h | 2 +- src/soc/amd/picasso/romstage.c | 4 +-- src/soc/amd/picasso/southbridge.c | 20 +++++------ 13 files changed, 65 insertions(+), 65 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 382aaef96e..9e96c1e98a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -185,9 +185,9 @@ config STONEYRIDGE_GEC_FWM_FILE config AMD_PUBKEY_FILE string "AMD public Key" - default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin" + default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyST.bin" -config STONEYRIDGE_SATA_MODE +config PICASSO_SATA_MODE int "SATA Mode" default 0 range 0 6 @@ -203,33 +203,33 @@ config STONEYRIDGE_SATA_MODE 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. comment "NATIVE" - depends on STONEYRIDGE_SATA_MODE = 0 + depends on PICASSO_SATA_MODE = 0 comment "AHCI" - depends on STONEYRIDGE_SATA_MODE = 2 + depends on PICASSO_SATA_MODE = 2 comment "LEGACY IDE" - depends on STONEYRIDGE_SATA_MODE = 3 + depends on PICASSO_SATA_MODE = 3 comment "IDE to AHCI" - depends on STONEYRIDGE_SATA_MODE = 4 + depends on PICASSO_SATA_MODE = 4 comment "AHCI7804" - depends on STONEYRIDGE_SATA_MODE = 5 + depends on PICASSO_SATA_MODE = 5 comment "IDE to AHCI7804" - depends on STONEYRIDGE_SATA_MODE = 6 + depends on PICASSO_SATA_MODE = 6 -if STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5 +if PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5 config AHCI_ROM_ID string "AHCI device PCI IDs" - default "1022,7801" if STONEYRIDGE_SATA_MODE = 2 - default "1022,7804" if STONEYRIDGE_SATA_MODE = 5 + default "1022,7801" if PICASSO_SATA_MODE = 2 + default "1022,7804" if PICASSO_SATA_MODE = 5 -endif # STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5 +endif # PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5 -config STONEYRIDGE_LEGACY_FREE +config PICASSO_LEGACY_FREE bool "System is legacy free" help Select y if there is no keyboard controller in the system. @@ -242,22 +242,22 @@ config SERIRQ_CONTINUOUS_MODE Set this option to y for serial IRQ in continuous mode. Otherwise it is in quiet mode. -config STONEYRIDGE_ACPI_IO_BASE +config PICASSO_ACPI_IO_BASE hex default 0x400 help Base address for the ACPI registers. This value must match the hardcoded value of AGESA. -config STONEYRIDGE_UART - bool "UART controller on Stoney Ridge" +config PICASSO_UART + bool "UART controller on Picasso" default n select DRIVERS_UART_8250MEM select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO select UART_OVERRIDE_REFCLK help - There are two UART controllers in Stoney Ridge. + There are two UART controllers in Picasso. The UART registers are memory-mapped. UART controller 0 registers range from FEDC_6000h to FEDC_6FFFh. UART controller 1 registers diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index e8c022fcda..b8a29c29a9 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -52,7 +52,7 @@ romstage-y += pmutil.c romstage-y += reset.c romstage-y += smbus.c romstage-y += ramtop.c -romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +romstage-$(CONFIG_PICASSO_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-$(CONFIG_SPI_FLASH) += spi.c @@ -63,12 +63,12 @@ verstage-y += i2c.c verstage-y += monotonic_timer.c verstage-y += pmutil.c verstage-y += reset.c -verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +verstage-$(CONFIG_PICASSO_UART) += uart.c verstage-y += tsc_freq.c verstage-$(CONFIG_SPI_FLASH) += spi.c postcar-y += monotonic_timer.c -postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c +postcar-$(CONFIG_PICASSO_UART) += uart.c postcar-y += ramtop.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c @@ -90,7 +90,7 @@ ramstage-y += smbus.c ramstage-y += ramtop.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c -ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +ramstage-$(CONFIG_PICASSO_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_SPI_FLASH) += spi.c @@ -117,7 +117,7 @@ CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi # +-----------+ # # EC ROM should be 64K aligned. -STONEYRIDGE_FWM_POSITION=$(call int-add, \ +PICASSO_FWM_POSITION=$(call int-add, \ $(call int-subtract, 0xffffffff \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) @@ -247,7 +247,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(OPT_SMUSCS_FILE) \ --combo-capable \ --flashsize $(CONFIG_ROM_SIZE) \ - --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ + --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) @@ -255,23 +255,23 @@ PHONY+=add_amdfw INTERMEDIATE+=add_amdfw # Calculate firmware position inside the ROM -STONEYRIDGE_FWM_ROM_POSITION=$(call int-add, \ +PICASSO_FWM_ROM_POSITION=$(call int-add, \ $(call int-subtract, $(CONFIG_ROM_SIZE) \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000) add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \ - "$(STONEYRIDGE_FWM_ROM_POSITION)" + "$(PICASSO_FWM_ROM_POSITION)" dd if=$(obj)/amdfw.rom \ of=$(obj)/coreboot.pre conv=notrunc bs=1 \ - seek=$(STONEYRIDGE_FWM_ROM_POSITION) >/dev/null 2>&1 + seek=$(PICASSO_FWM_ROM_POSITION) >/dev/null 2>&1 else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom -apu/amdfw-position := $(STONEYRIDGE_FWM_POSITION) +apu/amdfw-position := $(PICASSO_FWM_POSITION) apu/amdfw-type := raw endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index d1ea24ffd5..daeb7b60b4 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -75,7 +75,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", STONEYRIDGE_ACPI_IO_BASE); + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", PICASSO_ACPI_IO_BASE); /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); @@ -241,7 +241,7 @@ void generate_cpu_entries(struct device *device) { int cores, cpu; - /* Stoney Ridge is single node, just report # of cores */ + /* Picasso is single node, just report # of cores */ cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK; cores++; /* number of cores is CmpCap+1 */ diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 7221f955f6..19921e1c90 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -32,14 +32,14 @@ #include "chip.h" /* Supplied by i2c.c */ -extern struct device_operations stoneyridge_i2c_mmio_ops; +extern struct device_operations picasso_i2c_mmio_ops; extern const char *i2c_acpi_name(const struct device *dev); struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = stoney_init_cpus, + .init = picasso_init_cpus, .acpi_fill_ssdt_generator = generate_cpu_entries, }; @@ -132,7 +132,7 @@ static void enable_dev(struct device *dev) sb_enable(dev); else if (dev->path.type == DEVICE_PATH_MMIO) if (i2c_acpi_name(dev) != NULL) - dev->ops = &stoneyridge_i2c_mmio_ops; + dev->ops = &picasso_i2c_mmio_ops; } static void soc_init(void *chip_info) @@ -147,8 +147,8 @@ static void soc_final(void *chip_info) fam15_finalize(chip_info); } -struct chip_operations soc_amd_stoneyridge_ops = { - CHIP_NAME("AMD StoneyRidge SOC") +struct chip_operations soc_amd_picasso_ops = { + CHIP_NAME("AMD Picasso SOC") .enable_dev = enable_dev, .init = soc_init, .final = soc_final diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 4f241e7b6b..ff9c845898 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -27,9 +27,9 @@ #define MAX_DRAM_CH 1 #define MAX_DIMMS_PER_CH 2 -#define STONEY_I2C_DEV_MAX 4 +#define PICASSO_I2C_DEV_MAX 4 -struct soc_amd_stoneyridge_config { +struct soc_amd_picasso_config { u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH]; enum { DRAM_CONTENTS_KEEP, @@ -59,7 +59,7 @@ struct soc_amd_stoneyridge_config { * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) */ u8 i2c_scl_reset; - struct dw_i2c_bus_config i2c[STONEY_I2C_DEV_MAX]; + struct dw_i2c_bus_config i2c[PICASSO_I2C_DEV_MAX]; u8 stapm_percent; u32 stapm_time_ms; u32 stapm_power_mw; @@ -74,7 +74,7 @@ struct soc_amd_stoneyridge_config { u8 lvds_poseq_blon_to_varybl; }; -typedef struct soc_amd_stoneyridge_config config_t; +typedef struct soc_amd_picasso_config config_t; extern struct device_operations pci_domain_ops; diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 1d9804d99c..fc9e9ecf06 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -105,7 +105,7 @@ static const struct mp_ops mp_ops = { .post_mp_init = enable_smi_generation, }; -void stoney_init_cpus(struct device *dev) +void picasso_init_cpus(struct device *dev) { /* Clear for take-off */ if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 7f65a4f3f3..9fe15886d9 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -46,7 +46,7 @@ uintptr_t dw_i2c_base_address(unsigned int bus) return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0; } -static const struct soc_amd_stoneyridge_config *get_soc_config(void) +static const struct soc_amd_picasso_config *get_soc_config(void) { const struct device *dev = pcidev_path_on_root(GNB_DEVFN); @@ -61,7 +61,7 @@ static const struct soc_amd_stoneyridge_config *get_soc_config(void) const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { - const struct soc_amd_stoneyridge_config *config; + const struct soc_amd_picasso_config *config; if (bus >= ARRAY_SIZE(i2c_bus_address)) return NULL; @@ -107,7 +107,7 @@ int dw_i2c_soc_dev_to_bus(struct device *dev) static void dw_i2c_soc_init(bool is_early_init) { size_t i; - const struct soc_amd_stoneyridge_config *config; + const struct soc_amd_picasso_config *config; config = get_soc_config(); @@ -135,7 +135,7 @@ void i2c_soc_init(void) dw_i2c_soc_init(false); } -struct device_operations stoneyridge_i2c_mmio_ops = { +struct device_operations picasso_i2c_mmio_ops = { /* TODO(teravest): Move I2C resource info here. */ .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, @@ -188,7 +188,7 @@ static void restore_i2c_pin_registers(uint8_t gpio, /* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ void sb_reset_i2c_slaves(void) { - const struct soc_amd_stoneyridge_config *cfg; + const struct soc_amd_picasso_config *cfg; const struct device *dev = pcidev_path_on_root(GNB_DEVFN); struct soc_amd_i2c_save save_table[saved_pins_count]; uint8_t i, j, control; diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 71fe10eb26..f141a05714 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -20,7 +20,7 @@ #include -#if CONFIG(STONEYRIDGE_LEGACY_FREE) +#if CONFIG(PICASSO_LEGACY_FREE) #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE #else #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index d9d48ad27c..7d4764567a 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -29,7 +29,7 @@ #define SOC_EARLY_VMTRR_CAR_HEAP 2 #define SOC_EARLY_VMTRR_TEMPRAM 3 -void stoney_init_cpus(struct device *dev); +void picasso_init_cpus(struct device *dev); void check_mca(void); #endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index a63b16462b..7e2b7fc2f6 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -61,16 +61,16 @@ /* I/O Ranges */ #define ACPI_SMI_CTL_PORT 0xb2 -#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE -#define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define PICASSO_ACPI_IO_BASE CONFIG_PICASSO_ACPI_IO_BASE +#define ACPI_PM_EVT_BLK (PICASSO_ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ -#define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */ -#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */ +#define ACPI_PM1_CNT_BLK (PICASSO_ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_CPU_CONTROL (PICASSO_ACPI_IO_BASE + 0x08) /* 6 bytes */ +#define ACPI_GPE0_BLK (PICASSO_ACPI_IO_BASE + 0x10) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ -#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define ACPI_PM_TMR_BLK (PICASSO_ACPI_IO_BASE + 0x18) /* 4 bytes */ #define SMB_BASE_ADDR 0xb00 #define PM2_INDEX 0xcd0 #define PM2_DATA 0xcd1 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index fa9206e33a..7ba179fbea 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -316,7 +316,7 @@ #define RST_CMD BIT(2) #define SYS_RST BIT(1) -struct stoneyridge_aoac { +struct picasso_aoac { int enable; int status; }; diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 12ee2a8aca..5d1ed1877c 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -187,7 +187,7 @@ asmlinkage void car_stage_entry(void) void SetMemParams(AMD_POST_PARAMS *PostParams) { - const struct soc_amd_stoneyridge_config *cfg; + const struct soc_amd_picasso_config *cfg; const struct device *dev = pcidev_path_on_root(GNB_DEVFN); if (!dev || !dev->chip_info) { @@ -224,7 +224,7 @@ void SetMemParams(AMD_POST_PARAMS *PostParams) void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) { - const struct soc_amd_stoneyridge_config *cfg; + const struct soc_amd_picasso_config *cfg; const struct device *dev = pcidev_path_on_root(GNB_DEVFN); struct _PLATFORM_CONFIGURATION *platform; diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 45408ead02..711ebc592a 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -44,7 +44,7 @@ * waiting for each device to become available, a single delay will be * executed. */ -const static struct stoneyridge_aoac aoac_devs[] = { +const static struct picasso_aoac aoac_devs[] = { { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, @@ -56,22 +56,22 @@ const static struct stoneyridge_aoac aoac_devs[] = { static int is_sata_config(void) { - return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) - || (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE)); + return !((SataNativeIde == CONFIG_PICASSO_SATA_MODE) + || (SataLegacyIde == CONFIG_PICASSO_SATA_MODE)); } static inline int sb_sata_enable(void) { /* True if IDE or AHCI. */ - return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || - (SataAhci == CONFIG_STONEYRIDGE_SATA_MODE); + return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) || + (SataAhci == CONFIG_PICASSO_SATA_MODE); } static inline int sb_ide_enable(void) { /* True if IDE or LEGACY IDE. */ - return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || - (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE); + return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) || + (SataLegacyIde == CONFIG_PICASSO_SATA_MODE); } void SetFchResetParams(FCH_RESET_INTERFACE *params) @@ -91,11 +91,11 @@ void SetFchEnvParams(FCH_INTERFACE *params) { const struct device *dev = pcidev_path_on_root(SATA_DEVFN); params->AzaliaController = AzEnable; - params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; + params->SataClass = CONFIG_PICASSO_SATA_MODE; if (dev && dev->enabled) { params->SataEnable = is_sata_config(); params->IdeEnable = !params->SataEnable; - params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == + params->SataIdeMode = (CONFIG_PICASSO_SATA_MODE == SataLegacyIde); } else { params->SataEnable = FALSE; @@ -227,7 +227,7 @@ static void sb_lpc_decode(void) | DECODE_ENABLE_ADLIB_PORT; /* Decode SIOs at 2E/2F and 4E/4F */ - if (CONFIG(STONEYRIDGE_LEGACY_FREE)) + if (CONFIG(PICASSO_LEGACY_FREE)) tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; lpc_enable_decode(tmp); From 7e5a2660bc927adac1fc420f94c111b8f8aae191 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 11 Jun 2019 12:24:42 -0600 Subject: [PATCH 049/231] soc/amd/picasso: Remove stoneyridge GEC Remove the hudson-style support for the Gigabit Ethernet Controller. Change-Id: I2124b949a866148a97d9cd6e7fd418f7de8e2216 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/33751 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/soc/amd/picasso/Kconfig | 11 ----------- src/soc/amd/picasso/Makefile.inc | 3 --- 2 files changed, 14 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9e96c1e98a..9317119c99 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -167,22 +167,11 @@ config STONEYRIDGE_XHCI_FWM help Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0 -config STONEYRIDGE_GEC_FWM - bool - default n - help - Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC. - Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. - config STONEYRIDGE_XHCI_FWM_FILE string "XHCI firmware path and filename" default "3rdparty/blobs/soc/amd/stoneyridge/xhci.bin" depends on STONEYRIDGE_XHCI_FWM -config STONEYRIDGE_GEC_FWM_FILE - string "GEC firmware path and filename" - depends on STONEYRIDGE_GEC_FWM - config AMD_PUBKEY_FILE string "AMD public Key" default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyST.bin" diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b8a29c29a9..9aedbd1445 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -176,7 +176,6 @@ endif add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) -OPT_STONEYRIDGE_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_GEC_FWM_FILEddd), --gec) OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) @@ -198,7 +197,6 @@ OPT_SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --subpr $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ @@ -218,7 +216,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ $(OPT_STONEYRIDGE_XHCI_FWM_FILE) \ - $(OPT_STONEYRIDGE_GEC_FWM_FILE) \ $(OPT_AMD_PUBKEY_FILE) \ $(OPT_PSPBTLDR_FILE) \ $(OPT_SMUFWM_FILE) \ From 19ea0169108dc2eff743ae640a8108eb5852612d Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 11 Jun 2019 12:34:04 -0600 Subject: [PATCH 050/231] soc/amd/picasso: Remove most stoneyridge USB Picasso doesn't implement the AcpiMmio XHCI_PM registers. Remove source that uses these. Remove USB devices from the AOAC registers. Remove the D0/D3 support from ASL, including all supporting xHCI firmware loading support. Remove xHCI firmware from amdfw.rom. Change-Id: Iae4c72c5a8e353ca8db02d04735f8d2b28441793 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/33752 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/soc/amd/picasso/Kconfig | 21 -- src/soc/amd/picasso/Makefile.inc | 6 +- src/soc/amd/picasso/acpi/globalnvs.asl | 11 +- src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 41 --- src/soc/amd/picasso/acpi/usb.asl | 325 ------------------ src/soc/amd/picasso/include/soc/iomap.h | 1 - src/soc/amd/picasso/include/soc/nvs.h | 7 +- src/soc/amd/picasso/include/soc/southbridge.h | 40 +-- src/soc/amd/picasso/southbridge.c | 22 -- src/soc/amd/picasso/usb.c | 12 +- 10 files changed, 9 insertions(+), 477 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9317119c99..f692f95884 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -151,27 +151,6 @@ config EHCI_BAR hex default 0xfef00000 -config STONEYRIDGE_XHCI_ENABLE - bool "Enable Stoney Ridge XHCI Controller" - default y - help - The XHCI controller must be enabled and the XHCI firmware - must be added in order to have USB 3.0 support configured - by coreboot. The OS will be responsible for enabling the XHCI - controller if the XHCI firmware is available but the - XHCI controller is not enabled by coreboot. - -config STONEYRIDGE_XHCI_FWM - bool "Add xhci firmware" - default y - help - Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0 - -config STONEYRIDGE_XHCI_FWM_FILE - string "XHCI firmware path and filename" - default "3rdparty/blobs/soc/amd/stoneyridge/xhci.bin" - depends on STONEYRIDGE_XHCI_FWM - config AMD_PUBKEY_FILE string "AMD public Key" default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyST.bin" diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 9aedbd1445..dbb0e8e4fd 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -175,8 +175,6 @@ endif add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) -OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) - OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) OPT_SMUFWM_FILE=$(call add_opt_prefix, $(SMUFWM_FILE), --smufirmware) @@ -196,8 +194,7 @@ OPT_SMUFWM_FN_FILE=$(call add_opt_prefix, $(SMUFWM_FN_FILE), --subprogram $(SUBP OPT_SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware2) -$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ +$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPRCVR_FILE)) \ @@ -215,7 +212,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ - $(OPT_STONEYRIDGE_XHCI_FWM_FILE) \ $(OPT_AMD_PUBKEY_FILE) \ $(OPT_PSPBTLDR_FILE) \ $(OPT_SMUFWM_FILE) \ diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index e780a642c6..cdb32cc0d3 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -58,19 +58,10 @@ Field (GNVS, ByteAcc, NoLock, Preserve) UT1E, 1, // UART1, 12 , 2, ST_E, 1, // SATA, 15 - , 2, - EHCE, 1, // EHCI, 18 - , 4, - XHCE, 1, // XCHI, 23 + , 8, SD_E, 1, // SD, 24 , 2, ESPI, 1, // ESPI, 27 - , 4, - FW00, 16, // 0x38 - xHCI FW ROM addr, boot RAM - FW02, 16, // 0x3A - xHCI FW ROM addr, Instruction RAM - FW01, 32, // 0x3C - xHCI FW RAM addr, boot RAM - FW03, 32, // 0x40 - xHCI FW RAM addr, Instruction RAM - EH10, 32, // 0x44 - EHCI BAR /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 3623814080..8cdb4d2750 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -208,27 +208,6 @@ Field( SMIC, ByteAcc, NoLock, Preserve) { U2RP, 1, /* Usb2 Ref Clock Powerdown */ U3RP, 1, /* Usb3 Ref Clock Powerdown */ - /* XHCI_PM registers */ - offset (0x1c00), - , 1, - ,6, - U3PY, 1, - , 7, - UD3P, 1, /* bit 15 */ - U3PR, 1, /* bit 16 */ - , 11, - FWLM, 1, /* FirmWare Load Mode */ - FPLS, 1, /* Fw PreLoad Start */ - FPLC, 1, /* Fw PreLoad Complete */ - - offset (0x1c04), - UA04, 16, - , 15, - ROAM, 1, /* 1= ROM 0=RAM */ - - offset (0x1c08), - UA08, 32, - /* AOAC Registers */ offset (0x1e4a), /* I2C0 D3 Control */ I0TD, 2, @@ -442,8 +421,6 @@ Method(FDDC, 2, Serialized) } } /* todo Case(15) { STD0()} */ /* SATA */ - Case(18) { U2D0()} /* EHCI */ - Case(23) { U3D0()} /* XHCI */ Case(24) { /* SD */ Store(0x00, SDTD) Store(One, SDPD) @@ -505,8 +482,6 @@ Method(FDDC, 2, Serialized) Store(0x03, U1TD) } /* todo Case(15) { STD3()} */ /* SATA */ - Case(18) { U2D3()} /* EHCI */ - Case(23) { U3D3()} /* XHCI */ Case(24) { /* SD */ Store(Zero, SDPD) Store(SDDS, Local0) @@ -541,26 +516,10 @@ Method(FDDC, 2, Serialized) Method(FPTS,0, Serialized) /* FCH _PTS */ { - if(LEqual(\XHCE, one)) { - if(LNotEqual(U3TD, 0x03)) { - FDDC(23, 3) - } - } - if(LNotEqual(U2TD, 0x03)) { - FDDC(18, 3) - } } Method(FWAK,0, Serialized) /* FCH _WAK */ { - if(LEqual(\XHCE, one)) { - if(LEqual(U3TD, 0x03)) { - FDDC(23, 0) - } - } - if(LEqual(U2TD, 0x03)) { - FDDC(18, 0) - } if(LEqual(\UT0E, zero)) { if(LNotEqual(U0TD, 0x03)) { FDDC(11, 3) diff --git a/src/soc/amd/picasso/acpi/usb.asl b/src/soc/amd/picasso/acpi/usb.asl index f2ee8f6427..2af0c1a794 100644 --- a/src/soc/amd/picasso/acpi/usb.asl +++ b/src/soc/amd/picasso/acpi/usb.asl @@ -30,9 +30,6 @@ Device(EHC0) { Device (HS08) { Name (_ADR, 8) } } - Name(_PR0, Package() { P0U2 }) /* Indicate support for D0 */ - Name(_PR3, Package() { P3U2 }) /* Indicate support for D3cold */ - Method(_S0W,0) { Return(0) } @@ -55,9 +52,6 @@ Device(XHC0) { Device (SS02) { Name (_ADR, 2) } Device (SS03) { Name (_ADR, 3) } - Name(_PR0, Package() { P0U3 }) /* Indicate support for D0 */ - Name(_PR3, Package() { P3U3 }) /* Indicate support for D3cold */ - Method(_S0W,0) { Return(0) } @@ -71,322 +65,3 @@ Device(XHC0) { } } /* end XHC0 */ - -Scope(\_SB) -{ - Name(XHD0, 0) - Name(XHD3, 0) - PowerResource(P0U3, 0, 0) { - Method(_STA) { - Return(XHD0) - } - Method(_ON) { - Store(0x01, XHD0) - } - Method(_OFF) { - Store(0x00, XHD0) - } - } - PowerResource(P3U3, 0, 0) { - Method(_STA) { - Return(XHD3) - } - Method(_ON) { - Store(0x01, XHD3) - } - Method(_OFF) { - Store(0x00, XHD3) - } - } - - Name(EHD0, 0) - Name(EHD3, 0) - PowerResource(P0U2, 0, 0) { - Method(_STA) { - Return(EHD0) - } - Method(_ON) { - Store(0x01, EHD0) - } - Method(_OFF) { - Store(0x00, EHD0) - } - } - PowerResource(P3U2, 0, 0) { - Method(_STA) { - Return(EHD3) - } - Method(_ON) { - Store(0x01, EHD3) - } - Method(_OFF) { - Store(0x00, EHD3) - } - } -} - -OperationRegion(EHMC, SystemMemory, EH10, 0x100) -Field(EHMC, DwordAcc, NoLock, Preserve) -{ - Offset(0xb0), - , 5, - ESIM, 1, -} - -Method(U2D3,0, Serialized) -{ - if (LNotEqual(EH10, Zero)) { - Store (EH10, EHBA) - Store (One, EHME) - Store (ESIM, SSIM) - } - - if (LEqual(E_PS, 3)) { - Store (Zero, RQTY) - Store (One, RQ18) - - Store (U2SR, Local0) - while (Local0) { - Store (U2SR, Local0) - } - - Store (Zero, U2PD) - - Store (U2DS, Local0) - while (LNotEqual(Local0, Zero)) { - Store (U2DS, Local0) - } - - Store (0x03,U2TD) - - if (LEqual(U3TD, 0x03)) { /* Shutdown USB2 PLL */ - PWGC (0x40, 0) - Store (One, U2RP) - } - } -} - -Method(U2D0,0, Serialized) -{ - PWGC (0x40, 1) - Store (Zero, U2RP) - Store (0x00,U2TD) - - Store (Zero, U2TD) - Store (One, U2PD) - - Store (U2DS, Local0) - while (LNotEqual(Local0,0x7)) { - Store (U2DS, Local0) - } - - Store (One, RQTY) - Store (One, RQ18) - Store (U2SR, Local0) - while (LNot(Local0)) { - Store (U2SR, Local0) - } - Store (EHID, EH2C) - - - if (LNotEqual(EH10, Zero)) { - Store (EH10, EHBA) - Store (One, EHME) - Store (SSIM, ESIM) - } - - Store (ES54, EH54) - Store (ES64, EH64) -} - -Method(LXFW,3, Serialized) //Load Xhci FirmWare -{ - Store (One, FWLM) /* Firmware Load Mode */ - Store (Arg0, ROAM) /* ROM/RAM */ - Store (Arg1, UA04) - Store (Arg2, UA08) - Store (One, FPLS) /* Firmware Preload Start */ - Store (FPLC, Local0) /* Firmware Preload Complete */ - while (LNot(Local0)) { - Store (FPLC, Local0) - } - Store (Zero, FPLS) -} - -Method(U3D3,0, Serialized) -{ - if (LEqual(U_PS, 3)) { - X0_S () - - Or (PGA3, 0x20, PGA3) /* SwUsb3SlpShutdown */ - And (PGA3, 0x20, Local0) - while (LNot(Local0)) { /* wait for it to complete */ - And (PGA3, 0x20, Local0) - } - Store (One, UD3P) /* U3P_D3Cold_PWRDN */ - - Store (Zero, U3PD) /* PwrOnDev */ - Store (U3DS, Local0) - while (Local0) { /* RstBState, RefClkOkState, PwrRstBState */ - Store (U3DS, Local0) - } - - Store (0x3, U3TD) /* TargetedDeviceState */ - - Store (One, U3RP) /* USB3_RefClk_Pwdn */ - - if (Lequal(U2TD, 0x3)) { /* If EHCI targeted in D3cold */ - And (PGA3, 0x9f, PGA3) /* SwUsb2S5RstB */ - Store (One, U2RP) /* USB2_RefClk_Pwdn */ - } - Store (Zero, U3PG) /* XhcPwrGood */ - Store (One, U3PS) /* Usb3PowerSel */ - } -} - -Method(U3D0,0, Serialized) -{ - Store (Zero, U3PS) /* Usb3PowerSel */ - Store (One, U3PG) /* XhcPwrGood */ - - Store (Zero, U2RP) - Store (Zero, U3RP) - - And (PGA3, 0xdf, Local0) - Or (Local0, 0x40, Local0) - Store (Local0, PGA3) /* SwUsb2S5RstB */ - - Store (Zero, U3TD) /* TargetedDeviceState */ - Store (One, U3PD) /* PwrOnDev */ - - Store (U3DS, Local0) /* wait for RstBState, RefClkOkState, PwrRstBState */ - while (LNot(Lequal(Local0, 0x7))) { - Store (U3DS, Local0) - } - - Store (U3PY, Local0) /* USB3 PHY Lock */ - while (LNot(Local0)) { - Store (U3PY, Local0) - } - - Store (Zero, U3PR) /* U3P_RESTORE_RESET */ - - Store (AUSS, Local0) /* AutoSizeStart */ - if (LNotEqual(Local0,1)) { - Store(One, AUSS) - } - Store (AUSS, Local0) - while (LNotEqual(Local0,1)) { - Store (AUSS, Local0) - } - - LXFW (1, FW00, FW01) - LXFW (0, FW02, FW03) - - X0_R () - - Store (One, U3PR) /* U3P_RESTORE_RESET */ - Store (Zero, UD3P) /* U3P_D3Cold_PWRDN */ - Store (One, U3TD) /* TargetedDeviceState */ -} - -Name (SVBF, Buffer (0x1000) {0}) /* length from FchCarrizo.asl, new fields */ -CreateDWordField(SVBF, 0x000, S000) /* will be easier to add from there */ -CreateDWordField(SVBF, 0x004, S004) -CreateDWordField(SVBF, 0x008, S008) -CreateDWordField(SVBF, 0x00C, S00C) -CreateDWordField(SVBF, 0x018, S018) -CreateDWordField(SVBF, 0x01C, S01C) -CreateDWordField(SVBF, 0x020, S020) -CreateDWordField(SVBF, 0x030, S030) -CreateDWordField(SVBF, 0x118, S118) -CreateDWordField(SVBF, 0x158, S158) -CreateDWordField(SVBF, 0x198, S198) -CreateDWordField(SVBF, 0x1D8, S1D8) -CreateDWordField(SVBF, 0x300, S300) -CreateDWordField(SVBF, 0x304, S304) -CreateDWordField(SVBF, 0x308, S308) -CreateDWordField(SVBF, 0x30C, S30C) -CreateDWordField(SVBF, 0x310, S310) -CreateDWordField(SVBF, 0x428, S428) -CreateDWordField(SVBF, 0x438, S438) -CreateDWordField(SVBF, 0x43C, S43C) -CreateDWordField(SVBF, 0x458, S458) -CreateDWordField(SVBF, 0x468, S468) -CreateDWordField(SVBF, 0x46C, S46C) -CreateDWordField(SVBF, 0x470, S470) -CreateDWordField(SVBF, 0x480, S480) -CreateDWordField(SVBF, 0x484, S484) -CreateDWordField(SVBF, 0x488, S488) -CreateDWordField(SVBF, 0x48C, S48C) -CreateDWordField(SVBF, 0x730, EHID) /* EHCI SSID */ -CreateDWordField(SVBF, 0x734, XHID) /* XHCI SSID */ -CreateByteField(SVBF, 0x740, ES54) /* EHCI PCIx54 */ -CreateByteField(SVBF, 0x741, ES64) /* EHCI PCIx64 */ -CreateDWordField(SVBF, 0x7B0, SSIM) /* EHCI SIM BIT */ - -Method(X0_S,0) -{ - Store (XH2C, XHID) - Store (0x00000000, IDEX) Store (DATA, S000) - Store (0x00000004, IDEX) Store (DATA, S004) - Store (0x00000008, IDEX) Store (DATA, S008) - Store (0x0000000c, IDEX) Store (DATA, S00C) - Store (0x00000018, IDEX) Store (DATA, S018) - Store (0x0000001c, IDEX) Store (DATA, S01C) - Store (0x00000020, IDEX) Store (DATA, S020) - Store (0x00000030, IDEX) Store (DATA, S030) - Store (0x00000118, IDEX) Store (DATA, S118) - Store (0x00000158, IDEX) Store (DATA, S158) - Store (0x00000198, IDEX) Store (DATA, S198) - Store (0x000001d8, IDEX) Store (DATA, S1D8) - Store (0x00000300, IDEX) Store (DATA, S300) - Store (0x00000304, IDEX) Store (DATA, S304) - Store (0x00000308, IDEX) Store (DATA, S308) - Store (0x0000030c, IDEX) Store (DATA, S30C) - Store (0x00000310, IDEX) Store (DATA, S310) - Store (0x40000028, IDEX) Store (DATA, S428) - Store (0x40000038, IDEX) Store (DATA, S438) - Store (0x4000003c, IDEX) Store (DATA, S43C) - Store (0x40000058, IDEX) Store (DATA, S458) - Store (0x40000068, IDEX) Store (DATA, S468) - Store (0x4000006c, IDEX) Store (DATA, S46C) - Store (0x40000070, IDEX) Store (DATA, S470) - Store (0x40000080, IDEX) Store (DATA, S480) - Store (0x40000084, IDEX) Store (DATA, S484) - Store (0x40000088, IDEX) Store (DATA, S488) - Store (0x4000008c, IDEX) Store (DATA, S48C) -} - -Method(X0_R,0) -{ - Store (XHID, XH2C) - Store (0x00000000, IDEX) Store (S000, DATA) - Store (0x00000004, IDEX) Store (S004, DATA) - Store (0x00000008, IDEX) Store (S008, DATA) - Store (0x0000000c, IDEX) Store (S00C, DATA) - Store (0x00000018, IDEX) Store (S018, DATA) - Store (0x0000001c, IDEX) Store (S01C, DATA) - Store (0x00000020, IDEX) Store (S020, DATA) - Store (0x00000030, IDEX) Store (S030, DATA) - Store (0x00000118, IDEX) Store (S118, DATA) - Store (0x00000158, IDEX) Store (S158, DATA) - Store (0x00000198, IDEX) Store (S198, DATA) - Store (0x000001d8, IDEX) Store (S1D8, DATA) - Store (0x00000300, IDEX) Store (S300, DATA) - Store (0x00000304, IDEX) Store (S304, DATA) - Store (0x00000308, IDEX) Store (S308, DATA) - Store (0x0000030c, IDEX) Store (S30C, DATA) - Store (0x00000310, IDEX) Store (S310, DATA) - Store (0x40000028, IDEX) Store (S428, DATA) - Store (0x40000038, IDEX) Store (S438, DATA) - Store (0x4000003c, IDEX) Store (S43C, DATA) - Store (0x40000058, IDEX) Store (S458, DATA) - Store (0x40000068, IDEX) Store (S468, DATA) - Store (0x4000006c, IDEX) Store (S46C, DATA) - Store (0x40000070, IDEX) Store (S470, DATA) - Store (0x40000080, IDEX) Store (S480, DATA) - Store (0x40000084, IDEX) Store (S484, DATA) - Store (0x40000088, IDEX) Store (S488, DATA) - Store (0x4000008c, IDEX) Store (S48C, DATA) -} diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 7e2b7fc2f6..ad76f3a83d 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -39,7 +39,6 @@ #define SUPPORTS_ACPIMMIO_GPIO0_BASE 1 /* 0xfed81500 */ #define SUPPORTS_ACPIMMIO_GPIO1_BASE 1 /* 0xfed81800 */ #define SUPPORTS_ACPIMMIO_GPIO2_BASE 1 /* 0xfed81700 */ -#define SUPPORTS_ACPIMMIO_XHCIPM_BASE 1 /* 0xfed81c00 */ #define SUPPORTS_ACPIMMIO_AOAC_BASE 1 /* 0xfed81e00 */ #define ALINK_AHB_ADDRESS 0xfedc0000 diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 5023df6b27..1c02bb7e87 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -52,12 +52,7 @@ typedef struct global_nvs_t { uint8_t tmax; /* 0x30 - CPU Tj_max */ uint8_t pad1[3]; aoac_devs_t aoac; /* 0x34 - AOAC device enables */ - uint16_t fw00; /* 0x38 - XhciFwRomAddr_Rom, Boot RAM */ - uint16_t fw02; /* 0x3A - XhciFwRomAddr_Ram, Instr RAM */ - uint32_t fw01; /* 0x3C - XhciFwRamAddr_Rom, Boot RAM sz/base */ - uint32_t fw03; /* 0x40 - XhciFwRomAddr_Ram, Instr RAM sz/base */ - uint32_t eh10; /* 0x40 - EHCI BAR */ - uint8_t unused[184]; + uint8_t unused[200]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 7ba179fbea..a5892bbd87 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -178,31 +178,6 @@ #define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ #define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ -/* XHCI_PM Registers: 0xfed81c00 */ -#define XHCI_PM_INDIRECT_INDEX 0x48 -#define XHCI_PM_INDIRECT_DATA 0x4c -#define XHCI_OVER_CURRENT_CONTROL 0x30 -#define USB_OC0 0 -#define USB_OC1 1 -#define USB_OC2 2 -#define USB_OC3 3 -#define USB_OC4 4 -#define USB_OC5 5 -#define USB_OC6 6 -#define USB_OC7 7 -#define USB_OC_DISABLE 0xf -#define USB_OC_DISABLE_ALL 0xffff -#define OC_PORT0_SHIFT 0 -#define OC_PORT1_SHIFT 4 -#define OC_PORT2_SHIFT 8 -#define OC_PORT3_SHIFT 12 - -#define EHCI_OVER_CURRENT_CONTROL 0x70 -#define EHCI_HUB_CONFIG4 0x90 -#define DEBUG_PORT_SELECT_SHIFT 16 -#define DEBUG_PORT_ENABLE BIT(18) -#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18)) - /* FCH AOAC Registers 0xfed81e00 */ #define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 #define FCH_AOAC_D3_CONTROL_I2C0 0x4a @@ -212,8 +187,6 @@ #define FCH_AOAC_D3_CONTROL_UART0 0x56 #define FCH_AOAC_D3_CONTROL_UART1 0x58 #define FCH_AOAC_D3_CONTROL_AMBA 0x62 -#define FCH_AOAC_D3_CONTROL_USB2 0x64 -#define FCH_AOAC_D3_CONTROL_USB3 0x6e /* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */ #define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) #define FCH_AOAC_DEVICE_STATE BIT(2) @@ -231,8 +204,6 @@ #define FCH_AOAC_D3_STATE_UART0 0x57 #define FCH_AOAC_D3_STATE_UART1 0x59 #define FCH_AOAC_D3_STATE_AMBA 0x63 -#define FCH_AOAC_D3_STATE_USB2 0x65 -#define FCH_AOAC_D3_STATE_USB3 0x6f /* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */ #define FCH_AOAC_PWR_RST_STATE BIT(0) #define FCH_AOAC_RST_CLK_OK_STATE BIT(1) @@ -332,10 +303,7 @@ typedef struct aoac_devs { unsigned int ut1e:1; /* 12: UART1 */ unsigned int :2; unsigned int st_e:1; /* 15: SATA */ - unsigned int :2; - unsigned int ehce:1; /* 18: EHCI */ - unsigned int :4; - unsigned int xhce:1; /* 23: xHCI */ + unsigned int :8; unsigned int sd_e:1; /* 24: SDIO */ unsigned int :2; unsigned int espi:1; /* 27: ESPI */ @@ -350,11 +318,6 @@ struct soc_power_reg { uint16_t wake_from; }; -#define XHCI_FW_SIG_OFFSET 0xc -#define XHCI_FW_ADDR_OFFSET 0x6 -#define XHCI_FW_SIZE_OFFSET 0x8 -#define XHCI_FW_BOOTRAM_SIZE 0x8000 - void enable_aoac_devices(void); void sb_clk_output_48Mhz(u32 osc); void sb_disable_4dw_burst(void); @@ -403,6 +366,7 @@ uint64_t get_uma_base(void); * a default weak function in usb.c if the mainboard doesn't have any * over current support. */ +#define USB_OC_DISABLE_ALL 0xffff int mainboard_get_xhci_oc_map(uint16_t *usb_oc_map); int mainboard_get_ehci_oc_map(uint16_t *usb_oc_map); diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 711ebc592a..dca3591f85 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -77,7 +77,6 @@ static inline int sb_ide_enable(void) void SetFchResetParams(FCH_RESET_INTERFACE *params) { const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE); if (dev && dev->enabled) { params->SataEnable = sb_sata_enable(); params->IdeEnable = sb_ide_enable(); @@ -579,10 +578,6 @@ void southbridge_init(void *chip_info) static void set_sb_final_nvs(void) { - uintptr_t amdfw_rom; - uintptr_t xhci_fw; - uintptr_t fwaddr; - size_t fwsize; const struct device *sd, *sata; struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); @@ -595,29 +590,12 @@ static void set_sb_final_nvs(void) gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); - gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2); - gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); /* Rely on these being in sync with devicetree */ sd = pcidev_path_on_root(SD_DEVFN); gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0; sata = pcidev_path_on_root(SATA_DEVFN); gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; gnvs->aoac.espi = 1; - - amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); - xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET)); - - fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET - + XHCI_FW_BOOTRAM_SIZE)); - fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET - + XHCI_FW_BOOTRAM_SIZE)); - gnvs->fw00 = 0; - gnvs->fw01 = ((32 * KiB) << 16) + 0; - gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; - gnvs->fw03 = fwsize << 16; - - gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) - & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; } void southbridge_final(void *chip_info) diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index 00f82375e8..ae6c476055 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -29,17 +29,13 @@ static void set_usb_over_current(struct device *dev) uint16_t map = USB_OC_DISABLE_ALL; if (dev->path.pci.devfn == XHCI_DEVFN) { - if (mainboard_get_xhci_oc_map(&map) == 0) { - xhci_pm_write32(XHCI_PM_INDIRECT_INDEX, - XHCI_OVER_CURRENT_CONTROL); - xhci_pm_write16(XHCI_PM_INDIRECT_DATA, map); - } + if (mainboard_get_xhci_oc_map(&map) == 0) + ; // TODO } - if (dev->path.pci.devfn == EHCI1_DEVFN) { + if (dev->path.pci.devfn == EHCI1_DEVFN) if (mainboard_get_ehci_oc_map(&map) == 0) - pci_write_config16(dev, EHCI_OVER_CURRENT_CONTROL, map); - } + ; // TODO } int __weak mainboard_get_xhci_oc_map(uint16_t *map) From fa4a74b098731bf3e0979c20a65fa883bf4c57f3 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Sun, 30 Jun 2019 18:26:35 -0500 Subject: [PATCH 051/231] soc/amd/picasso: Add xhci1 and remove ehci Change-Id: I9d0098082c224bbf5ab2b4f0f41eb8b5b729eec7 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/33987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/picasso/chip.c | 6 ++--- src/soc/amd/picasso/include/soc/pci_devs.h | 26 +++++++++---------- src/soc/amd/picasso/include/soc/southbridge.h | 4 +-- src/soc/amd/picasso/usb.c | 13 +++++----- 4 files changed, 25 insertions(+), 24 deletions(-) diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 19921e1c90..dad9d22e7e 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -96,8 +96,6 @@ const char *soc_acpi_name(const struct device *dev) return "PBR8"; case HDA1_DEVFN: return "AZHD"; - case EHCI1_DEVFN: - return "EHC0"; case LPC_DEVFN: return "LPCB"; case SATA_DEVFN: @@ -106,8 +104,10 @@ const char *soc_acpi_name(const struct device *dev) return "SDCN"; case SMBUS_DEVFN: return "SBUS"; - case XHCI_DEVFN: + case XHCI0_DEVFN: return "XHC0"; + case XHCI1_DEVFN: + return "XHC1"; default: return NULL; } diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 478a2cb623..c823fdbfdc 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -151,12 +151,19 @@ #define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC) #define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC) -/* XHCI */ -#define XHCI_DEV 0x10 -#define XHCI_FUNC 0 -#define XHCI_DEVID 0x7914 -#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) -#define SOC_XHCI_DEV _SOC_DEV(XHCI_DEV, XHCI_FUNC) +/* USB 3.1 */ +#define XHCI0_DEV 0x0 +#define XHCI0_FUNC 3 +#define XHCI0_DEVID 0x15e0 +#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) +#define SOC_XHCI0_DEV _SOC_DEV(XHCI0_DEV, XHCI0_FUNC) + +/* USB 3.1 */ +#define XHCI1_DEV 0x0 +#define XHCI1_FUNC 4 +#define XHCI1_DEVID 0x15e1 +#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) +#define SOC_XHCI1_DEV _SOC_DEV(XHCI1_DEV, XHCI1_FUNC) /* SATA */ #define SATA_DEV 0x11 @@ -167,13 +174,6 @@ #define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) #define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) -/* EHCI */ -#define EHCI_DEV 0x12 -#define EHCI_FUNC 0 -#define EHCI_DEVID 0x7908 -#define EHCI1_DEVFN PCI_DEVFN(EHCI_DEV, EHCI_FUNC) -#define SOC_EHCI1_DEV _SOC_DEV(EHCI_DEV, EHCI_FUNC) - /* SMBUS */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index a5892bbd87..4392e4f099 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -367,8 +367,8 @@ uint64_t get_uma_base(void); * over current support. */ #define USB_OC_DISABLE_ALL 0xffff -int mainboard_get_xhci_oc_map(uint16_t *usb_oc_map); -int mainboard_get_ehci_oc_map(uint16_t *usb_oc_map); +int mainboard_get_xhci0_oc_map(uint16_t *usb_oc_map); +int mainboard_get_xhci1_oc_map(uint16_t *usb_oc_map); /* Initialize all the i2c buses that are marked with early init. */ void i2c_soc_early_init(void); diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index ae6c476055..66c8266cd3 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -28,23 +28,24 @@ static void set_usb_over_current(struct device *dev) { uint16_t map = USB_OC_DISABLE_ALL; - if (dev->path.pci.devfn == XHCI_DEVFN) { - if (mainboard_get_xhci_oc_map(&map) == 0) + if (dev->path.pci.devfn == XHCI0_DEVFN) { + if (mainboard_get_xhci0_oc_map(&map) == 0) ; // TODO } - if (dev->path.pci.devfn == EHCI1_DEVFN) - if (mainboard_get_ehci_oc_map(&map) == 0) + if (dev->path.pci.devfn == XHCI1_DEVFN) { + if (mainboard_get_xhci1_oc_map(&map) == 0) ; // TODO + } } -int __weak mainboard_get_xhci_oc_map(uint16_t *map) +int __weak mainboard_get_xhci0_oc_map(uint16_t *map) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); return -1; } -int __weak mainboard_get_ehci_oc_map(uint16_t *map) +int __weak mainboard_get_xhci1_oc_map(uint16_t *map) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); return -1; From 7997f1ff88d6154890b2489c93548f266ae6b8a9 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 1 Jul 2019 10:53:40 -0500 Subject: [PATCH 052/231] soc/amd/picasso: Remove SD controller Change-Id: Ie9cf361ed0caba9c73727453c4a503557edc854d Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/33988 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/picasso/acpi/globalnvs.asl | 4 +- src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 46 ------------------- src/soc/amd/picasso/chip.c | 2 - src/soc/amd/picasso/include/soc/pci_devs.h | 7 --- src/soc/amd/picasso/include/soc/southbridge.h | 4 +- src/soc/amd/picasso/southbridge.c | 4 +- 6 files changed, 3 insertions(+), 64 deletions(-) diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index cdb32cc0d3..cc264e6f85 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -58,9 +58,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) UT1E, 1, // UART1, 12 , 2, ST_E, 1, // SATA, 15 - , 8, - SD_E, 1, // SD, 24 - , 2, + , 11, ESPI, 1, // ESPI, 27 /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 8cdb4d2750..206fdfd0e1 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -53,21 +53,6 @@ Device(SBUS) { /* 0:14.3 - LPC */ #include -/* 0:14.7 - SD Controller */ -Device(SDCN) { - Name(_ADR, 0x00140007) - - Method(_PS0) { - FDDC(24, 0) - } - Method(_PS3) { - FDDC(24, 3) - } - Method(_PSC) { - Return(SDTD) - } -} /* end SDCN */ - Name(CRES, ResourceTemplate() { /* Set the Bus number and Secondary Bus number for the PCI0 device * The Secondary bus range for PCI0 lets the system @@ -272,15 +257,6 @@ Field( SMIC, ByteAcc, NoLock, Preserve) { offset (0x1e6f), /* USB3 D3 State */ U3DS, 3, - offset (0x1e70), /* SD D3 Control */ - SDTD, 2, - , 1, - SDPD, 1, - , 1, - , 1, - SDRT, 1, - SDSC, 1, - offset (0x1e71), /* SD D3 State */ SDDS, 3, @@ -421,14 +397,6 @@ Method(FDDC, 2, Serialized) } } /* todo Case(15) { STD0()} */ /* SATA */ - Case(24) { /* SD */ - Store(0x00, SDTD) - Store(One, SDPD) - Store(SDDS, Local0) - while(LNotEqual(Local0,0x7)) { - Store(SDDS, Local0) - } - } } } else { /* put device into D3cold */ @@ -482,20 +450,6 @@ Method(FDDC, 2, Serialized) Store(0x03, U1TD) } /* todo Case(15) { STD3()} */ /* SATA */ - Case(24) { /* SD */ - Store(Zero, SDPD) - Store(SDDS, Local0) - while(LNotEqual(Local0,0x0)) { - Store(SDDS, Local0) - } - Store(0x03, SDTD) - } - } - /* Turn off Power */ - if(LEqual(I0TD, 3)) { - if(LEqual(SATD, 3)) { - if(LEqual(SDTD, 3)) { Store(Zero, PG1A) } - } } if(LEqual(I1TD, 3)) { if(LEqual(I2TD, 3)) { diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index dad9d22e7e..776f328c86 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -100,8 +100,6 @@ const char *soc_acpi_name(const struct device *dev) return "LPCB"; case SATA_DEVFN: return "STCR"; - case SD_DEVFN: - return "SDCN"; case SMBUS_DEVFN: return "SBUS"; case XHCI0_DEVFN: diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index c823fdbfdc..8a885f2c0b 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -188,11 +188,4 @@ #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) #define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) -/* SD Controller */ -#define SD_DEV 0x14 -#define SD_FUNC 7 -#define SD_DEVID 0x7906 -#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) -#define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC) - #endif /* __PI_PICASSO_PCI_DEVS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 4392e4f099..0f72a68567 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -303,9 +303,7 @@ typedef struct aoac_devs { unsigned int ut1e:1; /* 12: UART1 */ unsigned int :2; unsigned int st_e:1; /* 15: SATA */ - unsigned int :8; - unsigned int sd_e:1; /* 24: SDIO */ - unsigned int :2; + unsigned int :11; unsigned int espi:1; /* 27: ESPI */ unsigned int :4; } __packed aoac_devs_t; diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index dca3591f85..87b933e119 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -578,7 +578,7 @@ void southbridge_init(void *chip_info) static void set_sb_final_nvs(void) { - const struct device *sd, *sata; + const struct device *sata; struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs == NULL) @@ -591,8 +591,6 @@ static void set_sb_final_nvs(void) gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); /* Rely on these being in sync with devicetree */ - sd = pcidev_path_on_root(SD_DEVFN); - gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0; sata = pcidev_path_on_root(SATA_DEVFN); gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; gnvs->aoac.espi = 1; From a392b00131d1ddc8489bf24c2eb7a14300374680 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 11 Jun 2019 13:11:07 -0600 Subject: [PATCH 053/231] soc/amd/picasso: Remove fanless SKU option The command line options for picasso will look different than stoneyridge. Remove the fanned/fanless distinction to simplify the makefile. Picasso will use subprograms instead of fanned/fanless SKUs. Change-Id: I50d8751e14b00ca53a6498f8e6c7f3f42543dace Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/33753 Reviewed-by: Martin Roth Reviewed-by: Richard Spiegel Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Kconfig | 16 ---------------- src/soc/amd/picasso/Makefile.inc | 24 ++---------------------- 2 files changed, 2 insertions(+), 38 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index f692f95884..f691cb51a1 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -271,22 +271,6 @@ config USE_PSPSECUREOS If unsure, answer 'y' -config SOC_AMD_SMU_FANLESS - bool - depends on SOC_AMD_PSP_SELECTABLE_SMU_FW - default n if SOC_AMD_SMU_NOTFANLESS - default y - -config SOC_AMD_SMU_FANNED - bool - depends on SOC_AMD_PSP_SELECTABLE_SMU_FW - default n - select SOC_AMD_SMU_NOTFANLESS - -config SOC_AMD_SMU_NOTFANLESS # helper symbol - do not use - bool - depends on SOC_AMD_PSP_SELECTABLE_SMU_FW - config AMDFW_OUTSIDE_CBFS bool "The AMD firmware is outside CBFS" default n diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index dbb0e8e4fd..f6fa9fae90 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -141,10 +141,8 @@ PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin ###8 - Check for SMU firmware named either *.sbin or *.csbin ### TODO: Remove *.sbin section after the blobs repo is updated. SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE).csbin -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE)_FN.csbin ifeq ("$(wildcard $(SMUFWM_FILE))","") SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin endif ###95 @@ -167,10 +165,8 @@ endif ###18- Check for SMU firmware2 named either *.sbin or *.csbin ### TODO: Remove *.sbin section after the blobs repo is updated. SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).csbin -SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE)_FN.csbin ifeq ("$(wildcard $(SMUFIRMWARE2_FILE))","") SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin -SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE)_FN.sbin endif add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) @@ -189,10 +185,6 @@ OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(TRUSTLETKEY_FILE), --trustletkey) endif OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware2) OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) -SUBPROG_FN_SMU_FW=1 -OPT_SMUFWM_FN_FILE=$(call add_opt_prefix, $(SMUFWM_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware) -OPT_SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware2) - $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ @@ -201,13 +193,11 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ $(call strip_quotes, $(PSPNVRAM_FILE)) \ $(call strip_quotes, $(SMUFWM_FILE)) \ - $(call strip_quotes, $(SMUFWM_FN_FILE)) \ $(call strip_quotes, $(SMUSCS_FILE)) \ $(call strip_quotes, $(PSPSECUREDEBUG_FILE)) \ $(call strip_quotes, $(PSPTRUSTLETS_FILE)) \ $(call strip_quotes, $(TRUSTLETKEY_FILE)) \ $(call strip_quotes, $(SMUFIRMWARE2_FILE)) \ - $(call strip_quotes, $(SMUFIRMWARE2_FN_FILE)) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" @@ -227,7 +217,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(OPT_AMD_PUBKEY_FILE) \ $(OPT_PSPBTLDR_FILE) \ $(OPT_SMUFWM_FILE) \ - $(OPT_SMUFWM_FN_FILE) \ $(OPT_PSPRCVR_FILE) \ $(OPT_PUBSIGNEDKEY_FILE) \ $(OPT_PSPSCUREOS_FILE) \ @@ -236,7 +225,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(OPT_PSPTRUSTLETS_FILE) \ $(OPT_TRUSTLETKEY_FILE) \ $(OPT_SMUFIRMWARE2_FILE) \ - $(OPT_SMUFIRMWARE2_FN_FILE) \ $(OPT_SMUSCS_FILE) \ --combo-capable \ --flashsize $(CONFIG_ROM_SIZE) \ @@ -273,18 +261,10 @@ ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) cbfs-files-y += smu_fw cbfs-files-y += smu_fw2 -smu_fw-type := raw -smu_fw2-type := raw - -ifeq ($(CONFIG_SOC_AMD_SMU_FANLESS),y) -smu_fw-file := $(SMUFWM_FN_FILE) -smu_fw2-file := $(SMUFIRMWARE2_FN_FILE) -else ifeq ($(CONFIG_SOC_AMD_SMU_FANNED),y) smu_fw-file := $(SMUFWM_FILE) +smu_fw-type := raw smu_fw2-file := $(SMUFIRMWARE2_FILE) -else -$(error "Proper SMU Firmware not selected") -endif +smu_fw2-type := raw endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) From 9df03a168fd54bc8e872448ff9fdfa30313c40ba Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 13 Jun 2019 15:59:38 -0600 Subject: [PATCH 054/231] soc/amd/picasso: Remove all PSP runtime functions Remove the mailbox call to notify the PSP that DRAM is ready. This is not supported on Family 17h. Remove the selectable SMU firmware. This is a feature of the PSP bootloader and the standard bootloader doesn't contain the ability. Clean up additional mentions of PSP within picasso. Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/33754 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/soc/amd/picasso/Kconfig | 2 -- src/soc/amd/picasso/Makefile.inc | 4 --- src/soc/amd/picasso/chip.c | 5 ---- src/soc/amd/picasso/cpu.c | 17 ----------- src/soc/amd/picasso/include/soc/iomap.h | 1 - src/soc/amd/picasso/include/soc/pci_devs.h | 7 ----- src/soc/amd/picasso/include/soc/southbridge.h | 5 ---- src/soc/amd/picasso/romstage.c | 29 ------------------- 8 files changed, 70 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index f691cb51a1..33aae2655f 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -50,7 +50,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_PI - select SOC_AMD_COMMON_BLOCK_PSP select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 select C_ENVIRONMENT_BOOTBLOCK @@ -65,7 +64,6 @@ config CPU_SPECIFIC_OPTIONS select POSTCAR_CONSOLE select SSE2 select RTC - select SOC_AMD_PSP_SELECTABLE_SMU_FW config VBOOT select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index f6fa9fae90..93a8bbbbf2 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -257,8 +257,6 @@ apu/amdfw-type := raw endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) - cbfs-files-y += smu_fw cbfs-files-y += smu_fw2 smu_fw-file := $(SMUFWM_FILE) @@ -266,6 +264,4 @@ smu_fw-type := raw smu_fw2-file := $(SMUFIRMWARE2_FILE) smu_fw2-type := raw -endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) - endif # ($(CONFIG_SOC_AMD_PICASSO),y) diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 776f328c86..b9e98c538c 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include @@ -157,10 +156,6 @@ static void earliest_ramstage(void *unused) int s3_resume = acpi_s3_resume_allowed() && romstage_handoff_is_resume(); if (!s3_resume) { - post_code(0x46); - if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2"); - post_code(0x47); do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); } else { diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index fc9e9ecf06..bee2b4b49f 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -121,23 +121,6 @@ static void model_15_init(struct device *dev) { check_mca(); setup_lapic(); - - /* - * Per AMD, sync an undocumented MSR with the PSP base address. - * Experiments showed that if you write to the MSR after it has - * been previously programmed, it causes a general protection fault. - * Also, the MSR survives warm reset and S3 cycles, so we need to - * test if it was previously written before writing to it. - */ - msr_t psp_msr; - uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */ - psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4); - psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - psp_msr = rdmsr(0xc00110a2); - if (psp_msr.lo == 0) { - psp_msr.lo = psp_bar; - wrmsr(0xc00110a2, psp_msr); - } } static struct device_operations cpu_dev_ops = { diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index ad76f3a83d..1d89fd7ec0 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -18,7 +18,6 @@ #define __SOC_PICASSO_IOMAP_H__ /* MMIO Ranges */ -#define PSP_MAILBOX_BAR3_BASE 0xf0a00000 #define SPI_BASE_ADDRESS 0xfec10000 #define IO_APIC2_ADDR 0xfec20000 diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 8a885f2c0b..d6887f9b38 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -95,13 +95,6 @@ #define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC) #define SOC_PCIE4_DEV _SOC_DEV(PCIE4_DEV, PCIE4_FUNC) -/* Platform Security Processor */ -#define PSP_DEV 0x8 -#define PSP_FUNC 0 -#define PSP_DEVID 0x1578 -#define PSP_DEVFN PCI_DEVFN(PSP_DEV, PSP_FUNC) -#define SOC_PSP_DEV _SOC_DEV(PSP_DEV, PSP_FUNC) - /* HD Audio 1 */ #define HDA1_DEV 0x9 #define HDA1_FUNC 2 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 0f72a68567..b28522e60f 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -277,11 +277,6 @@ #define SPI100_HOST_PREF_CONFIG 0x2c #define SPI_RD4DW_EN_HOST BIT(15) -/* Platform Security Processor D8F0 */ -#define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */ -#define PSP_BAR_ENABLES 0x48 -#define PSP_MAILBOX_BAR_EN 0x10 - /* IO 0xcf9 - Reset control port*/ #define FULL_RST BIT(3) #define RST_CMD BIT(2) diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 5d1ed1877c..904f556202 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -32,7 +32,6 @@ #include #include #include -#include #include "chip.h" @@ -41,28 +40,6 @@ void __weak mainboard_romstage_entry(int s3_resume) /* By default, don't do anything */ } -static void load_smu_fw1(void) -{ - u32 base, limit, cmd; - - /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ - base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; - limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); - pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit); - pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base); - - /* Preload a value into "BAR3" and enable it */ - pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); - pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); - - /* Enable memory access and master */ - cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); - cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd); - - psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw"); -} - static void agesa_call(void) { post_code(0x37); @@ -94,9 +71,6 @@ asmlinkage void car_stage_entry(void) console_init(); - if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) - load_smu_fw1(); - mainboard_romstage_entry(s3_resume); bsp_agesa_call(); @@ -143,9 +117,6 @@ asmlinkage void car_stage_entry(void) post_code(0x61); } - post_code(0x42); - psp_notify_dram(); - post_code(0x43); if (cbmem_recovery(s3_resume)) printk(BIOS_CRIT, "Failed to recover cbmem\n"); From 57c9bb0a97f757ac941d3cee8b2d749d6d770fc3 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 20 Jun 2019 14:34:22 -0600 Subject: [PATCH 055/231] soc/amd/common/hda: Add Picasso IDs Signed-off-by: Marshall Dawson Change-Id: I02b279a2b625ecbdf827cb4643d772eb81ddfe70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33756 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/soc/amd/common/block/hda/hda.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index f4ea732fba..49fc1a6648 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -21,6 +21,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_SB900_HDA, PCI_DEVICE_ID_AMD_CZ_HDA, + PCI_DEVICE_ID_AMD_PCO_HDA0, + PCI_DEVICE_ID_AMD_PCO_HDA1, 0 }; From 762621f27cc50a565b4ec88fbce6349a488c1c86 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 20 Jun 2019 14:39:17 -0600 Subject: [PATCH 056/231] soc/amd/common/iommu: Add Picasso ID Signed-off-by: Marshall Dawson Change-Id: Ib000e12cd568dd83b9533efe66e67878b806b3f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33757 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Richard Spiegel --- src/soc/amd/common/block/iommu/iommu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index 1c982ca00d..c068501d49 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -49,6 +49,7 @@ static struct device_operations iommu_ops = { static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU, PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU, + PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB_IOMMU, 0 }; From 6044be7f9e0c985a4e6e3fc8d28ce2270c67cbba Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 20 Jun 2019 15:07:39 -0600 Subject: [PATCH 057/231] soc/amd/common/lpc: Add Picasso ID Signed-off-by: Marshall Dawson Change-Id: I02e6fdcd6685e0dd3fa7872b054ebe508157a0ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/33758 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/lpc/lpc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index b896517214..c7946015cb 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -337,6 +337,7 @@ static struct device_operations lpc_ops = { static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_SB900_LPC, PCI_DEVICE_ID_AMD_CZ_LPC, + PCI_DEVICE_ID_AMD_PCO_LPC, 0 }; static const struct pci_driver lpc_driver __pci_driver = { From 8560db611608cbe0e344c1a301cf23e4c1fb36c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 3 Jul 2019 06:08:13 +0300 Subject: [PATCH 058/231] amdfam10: Declare empty activate_spd_rom() stub MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I1d0940a08f7ae5901b812618a6859c4297274591 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/33994 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/mainboard/advansus/a785e-i/romstage.c | 4 ---- src/mainboard/amd/bimini_fam10/romstage.c | 4 ---- src/mainboard/amd/mahogany_fam10/romstage.c | 2 -- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 1 - src/mainboard/amd/tilapia_fam10/romstage.c | 2 -- src/mainboard/asus/kcma-d8/romstage.c | 1 - src/mainboard/asus/kfsn4-dre/romstage.c | 4 ++-- src/mainboard/asus/kgpe-d16/romstage.c | 4 ++-- src/mainboard/asus/m4a78-em/romstage.c | 2 -- src/mainboard/asus/m4a785-m/romstage.c | 2 -- src/mainboard/asus/m5a88-v/romstage.c | 4 ---- src/mainboard/avalue/eax-785e/romstage.c | 4 ---- src/mainboard/gigabyte/ma785gm/romstage.c | 2 -- src/mainboard/gigabyte/ma785gmt/romstage.c | 2 -- src/mainboard/gigabyte/ma78gm/romstage.c | 2 -- src/mainboard/hp/dl165_g6_fam10/romstage.c | 3 +-- src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 -- src/mainboard/jetway/pa78vm5/romstage.c | 2 -- src/mainboard/msi/ms9652_fam10/romstage.c | 2 -- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 -- src/mainboard/supermicro/h8qme_fam10/romstage.c | 3 +-- src/mainboard/supermicro/h8scm_fam10/romstage.c | 4 ---- src/mainboard/tyan/s2912_fam10/romstage.c | 2 -- src/northbridge/amd/amdfam10/raminit.h | 2 ++ src/northbridge/amd/amdfam10/raminit_amdmct.c | 5 ++++- 25 files changed, 12 insertions(+), 55 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 4a817cf844..d8e618570f 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -45,13 +45,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) -{ -} int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 7b2f0513a4..e9d391cb0a 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -41,13 +41,9 @@ #include "cpu/amd/quadcore/quadcore.c" -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) -{ -} int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index c73eb0d388..2376414206 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -45,11 +45,9 @@ #include "cpu/amd/quadcore/quadcore.c" -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index a525154eb3..1ba65427c2 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -41,7 +41,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index a45d8f6510..9aa59b285a 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -43,11 +43,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 6c40627823..4bcfeddf53 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -50,7 +50,6 @@ #define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index dbf704b288..817e6db22a 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -53,7 +53,6 @@ #define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; @@ -170,7 +169,8 @@ static const uint8_t spd_addr[] = { RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, }; -void activate_spd_rom(const struct mem_controller *ctrl) { +void activate_spd_rom(const struct mem_controller *ctrl) +{ printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { printk(BIOS_DEBUG, "enable_spd_node0()\n"); diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index d017b0616a..85ad0b6f64 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -51,7 +51,6 @@ #define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1) #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; @@ -179,7 +178,8 @@ static const uint8_t spd_addr_fam10[] = { RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, }; -void activate_spd_rom(const struct mem_controller *ctrl) { +void activate_spd_rom(const struct mem_controller *ctrl) +{ struct sys_info *sysinfo = &sysinfo_car; printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index c99179e48e..072b758bef 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -46,11 +46,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 1d5921440d..c03115dc0b 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -46,11 +46,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 9216ecb910..ad05371367 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -46,13 +46,9 @@ #define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) -{ -} int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 934791926c..2d3c762c1a 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -45,13 +45,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) -{ -} int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 4ca318a4d8..cbcb54d709 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -46,11 +46,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 746be76642..2af958b335 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -46,11 +46,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 4d23bac7b8..4a28a2edbb 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -46,11 +46,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index c02b0e624e..94489c4ca3 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -52,11 +52,10 @@ #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { u8 val; outb(0x3d, 0x0cd6); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 421e613072..fa578942ad 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -45,11 +45,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 7fcb594391..8296b4c1c5 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -50,11 +50,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1) #endif -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 2da427d710..ecb3ab9a0f 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -44,11 +44,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } inline int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 4d6846c2de..c6f5d63b9f 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -47,11 +47,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SUPERIO_DEV PNP_DEV(0x2e, 0) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } inline int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 051cd61efb..87957e9443 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -50,11 +50,10 @@ #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f); smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f); diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index f3958f8d61..93dca0293c 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -42,13 +42,9 @@ #include "cpu/amd/quadcore/quadcore.c" -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) -{ -} int spd_read_byte(u32 device, u32 address) { diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 3f504e1957..85824aa494 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -43,11 +43,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); extern struct sys_info sysinfo_car; -void activate_spd_rom(const struct mem_controller *ctrl) { } inline int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index 029fa0e32a..9d1d91d536 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -24,6 +24,8 @@ struct sys_info; struct DCTStatStruc; struct MCTStatStruc; +void activate_spd_rom(const struct mem_controller *ctrl); + int mctRead_SPD(u32 smaddr, u32 reg); void mctSMBhub_Init(u32 node); void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 4f31a5e848..1f2b51d8bf 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -32,9 +32,12 @@ struct sys_info sysinfo_car CAR_GLOBAL; struct mem_controller; -extern void activate_spd_rom(const struct mem_controller *ctrl); extern int spd_read_byte(unsigned int device, unsigned int address); +void __weak activate_spd_rom(const struct mem_controller *ctrl) +{ +} + void fam15h_switch_dct(uint32_t dev, uint8_t dct) { uint32_t dword; From 04d025cf5015b06f9e4dafc7092cfbd5d24b241e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 3 Jul 2019 06:50:19 +0300 Subject: [PATCH 059/231] amdfam10: Declare get_sysinfo() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's forbidden to use dereference CAR_GLOBAL variables directly. The notation fails after CAR teardown for romstage. Change-Id: I6e6285ca0f520608c2a344517fbac943aeb36d87 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/33995 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/advansus/a785e-i/romstage.c | 3 +-- src/mainboard/amd/bimini_fam10/romstage.c | 3 +-- src/mainboard/amd/mahogany_fam10/romstage.c | 3 +-- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 3 +-- src/mainboard/amd/tilapia_fam10/romstage.c | 3 +-- src/mainboard/asus/kcma-d8/romstage.c | 3 +-- src/mainboard/asus/kfsn4-dre/romstage.c | 3 +-- src/mainboard/asus/kgpe-d16/romstage.c | 5 ++--- src/mainboard/asus/m4a78-em/romstage.c | 3 +-- src/mainboard/asus/m4a785-m/romstage.c | 3 +-- src/mainboard/asus/m5a88-v/romstage.c | 3 +-- src/mainboard/avalue/eax-785e/romstage.c | 3 +-- src/mainboard/gigabyte/ma785gm/romstage.c | 3 +-- src/mainboard/gigabyte/ma785gmt/romstage.c | 3 +-- src/mainboard/gigabyte/ma78gm/romstage.c | 3 +-- src/mainboard/hp/dl165_g6_fam10/romstage.c | 3 +-- src/mainboard/iei/kino-780am2-fam10/romstage.c | 3 +-- src/mainboard/jetway/pa78vm5/romstage.c | 3 +-- src/mainboard/msi/ms9652_fam10/romstage.c | 3 +-- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 3 +-- src/mainboard/supermicro/h8qme_fam10/romstage.c | 3 +-- src/mainboard/supermicro/h8scm_fam10/romstage.c | 3 +-- src/mainboard/tyan/s2912_fam10/romstage.c | 3 +-- src/northbridge/amd/amdfam10/amdfam10.h | 6 ------ src/northbridge/amd/amdfam10/raminit.h | 1 + src/northbridge/amd/amdfam10/raminit_amdmct.c | 7 ++++++- 26 files changed, 31 insertions(+), 54 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index d8e618570f..ca32977e10 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -46,7 +46,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -56,7 +55,7 @@ int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index e9d391cb0a..e2142f2791 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -42,7 +42,6 @@ #include "cpu/amd/quadcore/quadcore.c" int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -52,7 +51,7 @@ int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 2376414206..3397d26d96 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -46,7 +46,6 @@ #include "cpu/amd/quadcore/quadcore.c" int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -57,7 +56,7 @@ int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 1ba65427c2..3871c592d5 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -42,7 +42,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; static void memreset_setup(void) { @@ -167,7 +166,7 @@ static const u8 spd_addr[] = { void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 9aa59b285a..702e9db9df 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -44,7 +44,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -55,7 +54,7 @@ int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 4bcfeddf53..51d178fe88 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -51,7 +51,6 @@ #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; inline int spd_read_byte(unsigned int device, unsigned int address) { @@ -355,7 +354,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) : "=r" (esp) ); - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); /* Limit the maximum HT speed to 2.6GHz to prevent lockups * due to HT CPU <--> CPU wiring not being validated to 3.2GHz diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 817e6db22a..7b20243863 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -54,7 +54,6 @@ #define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(unsigned int device, unsigned int address) { @@ -184,7 +183,7 @@ void activate_spd_rom(const struct mem_controller *ctrl) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); u32 bsp_apicid = 0, val, wants_reset; msr_t msr; diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 85ad0b6f64..637ec42109 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -52,7 +52,6 @@ #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(unsigned int device, unsigned int address) { @@ -180,7 +179,7 @@ static const uint8_t spd_addr_fam10[] = { void activate_spd_rom(const struct mem_controller *ctrl) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { printk(BIOS_DEBUG, "enable_spd_node0()\n"); @@ -467,7 +466,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) : "=r" (esp) ); - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); /* Limit the maximum HT speed to 2.6GHz to prevent lockups * due to HT CPU <--> CPU wiring not being validated to 3.2GHz diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 072b758bef..c52b35b22f 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -47,7 +47,6 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -57,7 +56,7 @@ int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index c03115dc0b..b7af9e2cf5 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -47,7 +47,6 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -57,7 +56,7 @@ int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index ad05371367..1309d67d88 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -47,7 +47,6 @@ #define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -58,7 +57,7 @@ int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 2d3c762c1a..b4b536e1e4 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -46,7 +46,6 @@ #define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -56,7 +55,7 @@ int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index cbcb54d709..0d1f45d7af 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -47,7 +47,6 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -57,7 +56,7 @@ int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 2af958b335..384eccdb11 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -47,7 +47,6 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -57,7 +56,7 @@ int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 4a28a2edbb..48af367817 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -47,7 +47,6 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -57,7 +56,7 @@ int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 94489c4ca3..354bf125be 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -53,7 +53,6 @@ #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { @@ -83,7 +82,7 @@ static const u8 spd_addr[] = { void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index fa578942ad..d8afd67e94 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -46,7 +46,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -56,7 +55,7 @@ int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 8296b4c1c5..33d40b8876 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -51,7 +51,6 @@ #endif int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -61,7 +60,7 @@ int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index ecb3ab9a0f..2fc6fb42f0 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -45,7 +45,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; inline int spd_read_byte(unsigned int device, unsigned int address) @@ -100,7 +99,7 @@ static const u8 spd_addr[] = { void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); u32 bsp_apicid = 0, val, wants_reset; u8 reg; msr_t msr; diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index c6f5d63b9f..2750129859 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -48,7 +48,6 @@ #define SUPERIO_DEV PNP_DEV(0x2e, 0) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; inline int spd_read_byte(unsigned int device, unsigned int address) @@ -101,7 +100,7 @@ static const u8 spd_addr[] = { void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); u32 bsp_apicid = 0, val, wants_reset; msr_t msr; diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 87957e9443..56d9f35ef2 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -51,7 +51,6 @@ #define SMBUS_SWITCH2 0x72 int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; void activate_spd_rom(const struct mem_controller *ctrl) { @@ -154,7 +153,7 @@ static void write_GPIO(void) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); u32 bsp_apicid = 0, val, wants_reset; msr_t msr; diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 93dca0293c..302e86f4e8 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -43,7 +43,6 @@ #include "cpu/amd/quadcore/quadcore.c" int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(u32 device, u32 address) @@ -53,7 +52,7 @@ int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); static const u8 spd_addr[] = { RC00, 0x52, 0x53, 0, 0, 0x50, 0x51, 0, 0, //RC00, DIMM2, DIMM3, 0, 0, DIMM0, DIMM1, 0, 0, diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 85824aa494..f44346bbb6 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -44,7 +44,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; inline int spd_read_byte(unsigned int device, unsigned int address) @@ -104,7 +103,7 @@ static const u8 spd_addr[] = { void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); u32 bsp_apicid = 0, val, wants_reset; msr_t msr; diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index d2a05287df..0fbcea687c 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -989,12 +989,6 @@ struct sys_info { struct DCTStatStruc DCTstatA[NODE_NUMS]; } __packed; - -/* -#ifdef __PRE_RAM__ -extern struct sys_info sysinfo_car; -#endif -*/ #ifndef __PRE_RAM__ struct device *get_node_pci(u32 nodeid, u32 fn); #endif diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index 9d1d91d536..c9c57ff2c2 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -30,6 +30,7 @@ int mctRead_SPD(u32 smaddr, u32 reg); void mctSMBhub_Init(u32 node); void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); void set_sysinfo_in_ram(u32 val); +struct sys_info *get_sysinfo(void); void raminit_amdmct(struct sys_info *sysinfo); void amdmct_cbmem_store_info(struct sys_info *sysinfo); void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr); diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 1f2b51d8bf..440a02635b 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -29,7 +29,12 @@ /* Global allocation of sysinfo_car */ #include -struct sys_info sysinfo_car CAR_GLOBAL; +static struct sys_info sysinfo_car CAR_GLOBAL; + +struct sys_info *get_sysinfo(void) +{ + return car_get_var_ptr(&sysinfo_car); +} struct mem_controller; extern int spd_read_byte(unsigned int device, unsigned int address); From 2874330828fa6950bccba04872dbfc8cfae91d99 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 27 Jun 2019 14:31:02 +0000 Subject: [PATCH 060/231] Revert "soc/intel/skylake/romstage: Increase size of postcar stack" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit f70cb8bf968af75669325104756464ce6f4b824b. It was merged prematurely with some vague argumentation in the commit message and not all issues of reviewers were addressed. Change-Id: Ia336f3499fb29976a6b80383ef8b0f3d552f5640 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/33585 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans --- src/soc/intel/skylake/romstage/romstage_fsp20.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 83fc27eaa5..6ff59bad65 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -158,7 +158,7 @@ asmlinkage void car_stage_entry(void) pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 8*KiB)) + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); /* From 8f23b5d4343c5c8ec1f7f7d453f9d8784fc0d5a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 30 Jun 2019 21:00:07 +0300 Subject: [PATCH 061/231] drivers/intel/fsp1_1: Adjust postcar MTRRs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use of romstage_ram_stack_bottom() was invalid, it potentially uses a different ROMSTAGE_RAM_STACK_SIZE from the postcar_frame_init() call. If alignment evaluated to 1 MiB, that WB MTRR may not have covered all of CBMEM range, having some impact on boot speeds. There is no need to accurately describe write-back MTRR ranges for postcar. Change-Id: Icb65cef079df56fadcc292c648cab8bdbb667f47 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/33927 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/drivers/intel/fsp1_1/car.c | 56 +++++----------------------------- 1 file changed, 7 insertions(+), 49 deletions(-) diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index bd3f4787a0..84ea7d153c 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -32,8 +33,7 @@ void platform_enter_postcar(void) { struct postcar_frame pcf; - size_t alignment; - uint32_t aligned_ram; + uintptr_t top_of_ram; if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) die("Unable to initialize postcar frame.\n"); @@ -44,53 +44,11 @@ void platform_enter_postcar(void) /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* - * +-------------------------+ Top of RAM (aligned) - * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE - * | (TSEG) | - * +-------------------------+ SMM base (aligned) - * | | - * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE - * | | - * +-------------------------+ top_of_ram (aligned) - * | | - * | CBMEM Root | - * | | - * +-------------------------+ - * | | - * | FSP Reserved Memory | - * | | - * +-------------------------+ - * | | - * | Various CBMEM Entries | - * | | - * +-------------------------+ top_of_stack (8 byte aligned) - * | | - * | stack (CBMEM Entry) | - * | | - * +-------------------------+ - */ - - alignment = mmap_region_granularity(); - aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); - postcar_frame_add_mtrr(&pcf, aligned_ram, alignment, MTRR_TYPE_WRBACK); - - if (CONFIG(HAVE_SMI_HANDLER)) { - void *smm_base; - size_t smm_size; - - /* - * Cache the TSEG region at the top of ram. This region is not - * restricted to SMM mode until SMM has been relocated. By - * setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, (uintptr_t)smm_base, alignment, - MTRR_TYPE_WRBACK); - } + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); run_postcar_phase(&pcf); } From 6e2d0c1b90251b4b61af582d2598cdbd38591db7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 28 Jun 2019 10:08:51 +0300 Subject: [PATCH 062/231] arch/x86: Adjust size of postcar stack MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With VBOOT=y && VBOOT_MEASURED_BOOT=y message digest will be allocated from the stack and 1 KiB reserve used with the recent platforms was no longer sufficient. The comment of LZMA scratchpad consuming stack was obsolete for postcar, so these can be reduced to same 4 KiB. Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a Signed-off-by: Mario Scheithauer Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Werner Zeh --- src/arch/x86/include/arch/cpu.h | 5 +++-- src/arch/x86/postcar_loader.c | 9 +++++++++ src/cpu/intel/haswell/romstage.c | 4 +--- src/drivers/intel/fsp1_1/car.c | 4 +--- src/mainboard/emulation/qemu-i440fx/romstage.c | 7 ++----- src/mainboard/emulation/qemu-q35/romstage.c | 7 ++----- src/northbridge/intel/e7505/memmap.c | 4 +--- src/northbridge/intel/gm45/ram_calc.c | 4 +--- src/northbridge/intel/i440bx/ram_calc.c | 5 ++--- src/northbridge/intel/i945/ram_calc.c | 4 +--- src/northbridge/intel/nehalem/ram_calc.c | 4 +--- src/northbridge/intel/pineview/ram_calc.c | 5 ++--- src/northbridge/intel/sandybridge/ram_calc.c | 4 +--- src/northbridge/intel/x4x/ram_calc.c | 4 +--- src/soc/amd/stoneyridge/romstage.c | 2 +- src/soc/intel/apollolake/romstage.c | 2 +- src/soc/intel/baytrail/romstage/romstage.c | 4 +--- src/soc/intel/broadwell/romstage/romstage.c | 5 ++--- src/soc/intel/cannonlake/romstage/romstage.c | 3 ++- src/soc/intel/denverton_ns/romstage.c | 3 ++- src/soc/intel/icelake/romstage/romstage.c | 3 ++- src/soc/intel/quark/romstage/fsp2_0.c | 3 ++- src/soc/intel/skylake/romstage/romstage_fsp20.c | 2 +- 23 files changed, 42 insertions(+), 55 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 75f1f439b8..38066c15a2 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -309,8 +309,9 @@ struct postcar_frame { }; /* - * Initialize postcar_frame object allocating stack size in cbmem - * with the provided size. Returns 0 on success, < 0 on error. + * Initialize postcar_frame object allocating stack from cbmem, + * with stack_size == 0, default 4 KiB is allocated. + * Returns 0 on success, < 0 on error. */ int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size); diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 732b767bf6..35e139fe1c 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -48,6 +48,15 @@ int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size) { void *stack; + /* + * Use default postcar stack size of 4 KiB. This value should + * not be decreased, because if mainboards use vboot, 1 KiB will + * not be enough anymore. + */ + + if (stack_size == 0) + stack_size = 4 * KiB; + stack = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, stack_size); if (stack == NULL) { printk(BIOS_ERR, "Couldn't add %zd byte stack in cbmem.\n", diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 3cbdf44c1d..47b9976786 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -38,8 +38,6 @@ #include #include "haswell.h" -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -48,7 +46,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 84ea7d153c..1e89a8eb89 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -25,8 +25,6 @@ #include #include -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -35,7 +33,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index e1d4f62708..6b1883ccbd 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -31,11 +32,7 @@ asmlinkage void car_stage_entry(void) timestamp_add_now(TS_START_ROMSTAGE); - /** - * The LZMA decoder needs about 4 KiB stack. - * Leave 1 KiB stack for general postcar code. - */ - if (postcar_frame_init(&pcf, 5 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /** diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 3e0870ffec..e409ad1e5f 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -32,11 +33,7 @@ asmlinkage void car_stage_entry(void) timestamp_add_now(TS_START_ROMSTAGE); - /** - * The LZMA decoder needs about 4 KiB stack. - * Leave 1 KiB stack for general postcar code. - */ - if (postcar_frame_init(&pcf, 5 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /** diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index f7a08bc28d..d45006566e 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -35,8 +35,6 @@ void *cbmem_top(void) return (void *)tolm; } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -45,7 +43,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index c1307c48f5..c6140824f0 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -123,8 +123,6 @@ void *cbmem_top(void) return (void *) top_of_ram; } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -133,7 +131,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c index 09a3b03272..495ca8682a 100644 --- a/src/northbridge/intel/i440bx/ram_calc.c +++ b/src/northbridge/intel/i440bx/ram_calc.c @@ -15,6 +15,7 @@ #define __SIMPLE_DEVICE__ +#include #include #include #include @@ -67,8 +68,6 @@ void *cbmem_top(void) return (void *)tom; } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -77,7 +76,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 752c8f901c..525a5b9c0e 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -88,8 +88,6 @@ u32 decode_igd_memory_size(const u32 gms) return ggc2uma[gms] << 10; } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -98,7 +96,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index e32190f519..ba3761065b 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -43,8 +43,6 @@ void *cbmem_top(void) return (void *) smm_region_start(); } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -53,7 +51,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index a789956ea3..d1b43aa42d 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -16,6 +16,7 @@ #define __SIMPLE_DEVICE__ +#include #include #include #include @@ -137,8 +138,6 @@ void *cbmem_top(void) } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -147,7 +146,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 5cda8a33fe..343ae62711 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -43,8 +43,6 @@ void *cbmem_top(void) return (void *) smm_region_start(); } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -53,7 +51,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 371496985f..be9c10f001 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -134,8 +134,6 @@ void *cbmem_top(void) return (void *) top_of_ram; } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -144,7 +142,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 12ee2a8aca..000d100fa3 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -153,7 +153,7 @@ asmlinkage void car_stage_entry(void) printk(BIOS_ERR, "Failed to set romstage handoff data\n"); post_code(0x44); - if (postcar_frame_init(&pcf, 1 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 5bf501dcfa..5d65a0029e 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -240,7 +240,7 @@ asmlinkage void car_stage_entry(void) else printk(BIOS_ERR, "Failed to determine variable data\n"); - if (postcar_frame_init(&pcf, 1*KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); mainboard_save_dimm_info(); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 5621dd16eb..7e2bb64ba6 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -238,8 +238,6 @@ void romstage_common(struct romstage_params *params) romstage_handoff_init(prev_sleep_state == ACPI_S3); } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ static void platform_enter_postcar(void) @@ -247,7 +245,7 @@ static void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 9bca716447..9c86809368 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -34,8 +35,6 @@ #include #include -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -44,7 +43,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 9dadb2d14e..94b9899422 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -146,7 +147,7 @@ asmlinkage void car_stage_entry(void) pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 1 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 4477c927e9..6d8eaab9b1 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -161,7 +162,7 @@ asmlinkage void car_stage_entry(void) display_fsp_smbios_memory_info_hob(); #endif - if (postcar_frame_init(&pcf, 1 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index b0eeb2e959..514e5e8925 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -131,7 +132,7 @@ asmlinkage void car_stage_entry(void) pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 1 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 5ebbacbd2a..a8bd26eceb 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -61,7 +62,7 @@ asmlinkage void car_stage_c_entry(void) /* Initialize the PCIe bridges */ pcie_init(); - if (postcar_frame_init(&pcf, 1*KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Locate the top of RAM */ diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 6ff59bad65..fafa343780 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -158,7 +158,7 @@ asmlinkage void car_stage_entry(void) pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 1*KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* From 70b421f3bd81923c01e16989dfec045d56a5c447 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 1 Jul 2019 12:19:48 +0200 Subject: [PATCH 063/231] lib/romstage_stack.c: Remove unused functions Change-Id: I1e66ff3fe7462dfeae2a7ce7e3a8083cf90a15f9 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33936 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/include/program_loading.h | 2 -- src/lib/romstage_stack.c | 17 ----------------- 2 files changed, 19 deletions(-) diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 7be59e2878..223fc0bef1 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -176,8 +176,6 @@ void run_ramstage(void); /* Determine where stack for ramstage loader is located. */ enum { ROMSTAGE_STACK_CBMEM, ROMSTAGE_STACK_LOW_MEM }; uintptr_t romstage_ram_stack_base(size_t size, int src); -uintptr_t romstage_ram_stack_top(void); -uintptr_t romstage_ram_stack_bottom(void); /* Backup OS memory to CBMEM_ID_RESUME on ACPI S3 resume path, * if ramstage overwrites low memory. */ diff --git a/src/lib/romstage_stack.c b/src/lib/romstage_stack.c index ed6f09b4cb..4fe1459532 100644 --- a/src/lib/romstage_stack.c +++ b/src/lib/romstage_stack.c @@ -32,20 +32,3 @@ uintptr_t romstage_ram_stack_base(size_t size, int src) return CONFIG_RAMTOP - size; return 0; } - -uintptr_t romstage_ram_stack_bottom(void) -{ - return romstage_ram_stack_base(ROMSTAGE_RAM_STACK_SIZE, - ROMSTAGE_STACK_CBMEM); -} - -uintptr_t romstage_ram_stack_top(void) -{ - uintptr_t stack_top = romstage_ram_stack_base(ROMSTAGE_RAM_STACK_SIZE, - ROMSTAGE_STACK_CBMEM); - stack_top += ROMSTAGE_RAM_STACK_SIZE; - - /* Make it aligned to a 8-byte boundary. */ - stack_top = ALIGN_DOWN(stack_top, 8); - return stack_top; -} From 367497486d637ff07518872ad21f2cf2d8443e80 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 2 Jul 2019 11:08:53 -0600 Subject: [PATCH 064/231] sb/intel/common: Use correct bitwise operator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Like the line above it, this should be & instead of | (otherwise it will always incorrectly return true). spi_locked() is only used internally to decide which opcodes will be used to talk to the flash, and if it is falsely reported as locked, the worst case should be a denial of service (unless there are more bugs). Change-Id: I5208b523c815d15d7263594f06ccfacd8a9510b1 Signed-off-by: Jacob Garber Found-by: Coverity CID 1402092 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33963 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/southbridge/intel/common/spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index e8c8f01407..e9e66dcda3 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -338,7 +338,7 @@ static int spi_locked(void) if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { return !!(readw_(&cntlr->ich7_spi->spis) & HSFS_FLOCKDN); } else { - return !!(readw_(&cntlr->ich9_spi->hsfs) | HSFS_FLOCKDN); + return !!(readw_(&cntlr->ich9_spi->hsfs) & HSFS_FLOCKDN); } } From dace2498ecfadf645599aaa3ba8fef8cbb111c2d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 3 Jul 2019 10:49:44 +0300 Subject: [PATCH 065/231] pcengines/apuX: Replace use of dev_find_slot() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Find the NIC device based on the PCIe root port function. Change-Id: Ia8c6e115c9b836ee60862427dfc9d46ca3dd1b69 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34003 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/mainboard/pcengines/apu1/mainboard.c | 14 ++++++++++---- src/mainboard/pcengines/apu2/mainboard.c | 17 +++++------------ 2 files changed, 15 insertions(+), 16 deletions(-) diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index e5e30e031c..088c839239 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -206,17 +206,23 @@ static void mainboard_enable(struct device *dev) const char *smbios_mainboard_serial_number(void) { static char serial[10]; - struct device *nic_dev; + struct device *dev; uintptr_t bar18; u32 mac_addr = 0; int i; - nic_dev = dev_find_slot(1, PCI_DEVFN(0, 0)); - if ((serial[0] != 0) || !nic_dev) + /* Already initialized. */ + if (serial[0] != 0) + return serial; + + dev = pcidev_on_root(4, 0); + if (dev) + dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0)); + if (!dev) return serial; /* Read in the last 3 bytes of NIC's MAC address. */ - bar18 = pci_read_config32(nic_dev, 0x18); + bar18 = pci_read_config32(dev, 0x18); bar18 &= 0xFFFFFC00; for (i = 3; i < 6; i++) { mac_addr <<= 8; diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 5a19d20efc..682120bc65 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -197,22 +197,15 @@ const char *smbios_mainboard_serial_number(void) struct device *dev; uintptr_t bar10; u32 mac_addr = 0; - u32 bus_no; int i; - /* - * In case we have PCIe module connected to mPCIe2 slot, BDF 1:0.0 may - * not be a NIC, because mPCIe2 slot is routed to the very first PCIe - * bridge and the first NIC is connected to the second PCIe bridge. - * Read secondary bus number from the PCIe bridge where the first NIC is - * connected. - */ - dev = pcidev_on_root(2, 2); - if ((serial[0] != 0) || !dev) + /* Already initialized. */ + if (serial[0] != 0) return serial; - bus_no = dev->link_list->secondary; - dev = dev_find_slot(bus_no, PCI_DEVFN(0, 0)); + dev = pcidev_on_root(2, 2); + if (dev) + dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0)); if (!dev) return serial; From 9c0e14e7c43e85e99c0bbfdff72019d908de1711 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 23 Jan 2019 16:46:35 +0200 Subject: [PATCH 066/231] device/pci_ops: Define pci_find_capability() just once MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Wrap the simple romstage implementation to be called from ramstage. Change-Id: Iadadf3d550416850d6c37233bd4eda025f4d3960 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31755 Reviewed-by: Paul Menzel Reviewed-by: Martin Roth Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/device/pci_device.c | 67 ---------------------------------- src/device/pci_early.c | 48 ------------------------ src/device/pci_ops.c | 71 ++++++++++++++++++++++++++++++++++++ src/drivers/usb/pci_ehci.c | 4 +- src/include/device/pci.h | 10 ----- src/include/device/pci_ops.h | 17 +++++++++ src/soc/cavium/common/ecam.c | 10 ++--- 7 files changed, 94 insertions(+), 133 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 31c35dc02e..a2af0ec999 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -101,73 +101,6 @@ u32 pci_moving_config32(struct device *dev, unsigned int reg) return ones ^ zeroes; } -/** - * Given a device, a capability type, and a last position, return the next - * matching capability. Always start at the head of the list. - * - * @param dev Pointer to the device structure. - * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. - * @param last Location of the PCI capability register to start from. - * @return The next matching capability. - */ -unsigned pci_find_next_capability(struct device *dev, unsigned cap, - unsigned last) -{ - unsigned pos = 0; - u16 status; - unsigned reps = 48; - - status = pci_read_config16(dev, PCI_STATUS); - if (!(status & PCI_STATUS_CAP_LIST)) - return 0; - - switch (dev->hdr_type & 0x7f) { - case PCI_HEADER_TYPE_NORMAL: - case PCI_HEADER_TYPE_BRIDGE: - pos = PCI_CAPABILITY_LIST; - break; - case PCI_HEADER_TYPE_CARDBUS: - pos = PCI_CB_CAPABILITY_LIST; - break; - default: - return 0; - } - - pos = pci_read_config8(dev, pos); - while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */ - int this_cap; - - pos &= ~3; - this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID); - printk(BIOS_SPEW, "Capability: type 0x%02x @ 0x%02x\n", - this_cap, pos); - if (this_cap == 0xff) - break; - - if (!last && (this_cap == cap)) - return pos; - - if (last == pos) - last = 0; - - pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT); - } - return 0; -} - -/** - * Given a device, and a capability type, return the next matching - * capability. Always start at the head of the list. - * - * @param dev Pointer to the device structure. - * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. - * @return The next matching capability. - */ -unsigned int pci_find_capability(struct device *dev, unsigned int cap) -{ - return pci_find_next_capability(dev, cap, 0); -} - /** * Given a device and register, read the size of the BAR for that register. * diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 5a1fb22681..7c9ea005c6 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -21,54 +21,6 @@ #include #include -unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last) -{ - unsigned pos = 0; - u16 status; - unsigned reps = 48; - - status = pci_read_config16(dev, PCI_STATUS); - if (!(status & PCI_STATUS_CAP_LIST)) - return 0; - - u8 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - switch (hdr_type & 0x7f) { - case PCI_HEADER_TYPE_NORMAL: - case PCI_HEADER_TYPE_BRIDGE: - pos = PCI_CAPABILITY_LIST; - break; - case PCI_HEADER_TYPE_CARDBUS: - pos = PCI_CB_CAPABILITY_LIST; - break; - default: - return 0; - } - - pos = pci_read_config8(dev, pos); - while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */ - int this_cap; - - pos &= ~3; - this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID); - if (this_cap == 0xff) - break; - - if (!last && (this_cap == cap)) - return pos; - - if (last == pos) - last = 0; - - pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT); - } - return 0; -} - -unsigned pci_find_capability(pci_devfn_t dev, unsigned cap) -{ - return pci_find_next_capability(dev, cap, 0); -} - static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge) { u16 reg16; diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 34f9d1e5b5..96133155be 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -11,6 +11,77 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include +#include +#include +#include +#include u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_MMCONF_BASE_ADDRESS; + +/** + * Given a device, a capability type, and a last position, return the next + * matching capability. Always start at the head of the list. + * + * @param dev Pointer to the device structure. + * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. + * @param last Location of the PCI capability register to start from. + * @return The next matching capability. + */ +u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last) +{ + u16 pos = 0; + u16 status; + int reps = 48; + + status = pci_s_read_config16(dev, PCI_STATUS); + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + + u8 hdr_type = pci_s_read_config8(dev, PCI_HEADER_TYPE); + switch (hdr_type & 0x7f) { + case PCI_HEADER_TYPE_NORMAL: + case PCI_HEADER_TYPE_BRIDGE: + pos = PCI_CAPABILITY_LIST; + break; + case PCI_HEADER_TYPE_CARDBUS: + pos = PCI_CB_CAPABILITY_LIST; + break; + default: + return 0; + } + + pos = pci_s_read_config8(dev, pos); + while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */ + int this_cap; + + pos &= ~3; + this_cap = pci_s_read_config8(dev, pos + PCI_CAP_LIST_ID); + if (this_cap == 0xff) + break; + + if (!last && (this_cap == cap)) + return pos; + + if (last == pos) + last = 0; + + pos = pci_s_read_config8(dev, pos + PCI_CAP_LIST_NEXT); + } + return 0; +} + +/** + * Given a device, and a capability type, return the next matching + * capability. Always start at the head of the list. + * + * @param dev Pointer to the device structure. + * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. + * @return The next matching capability. + */ +u16 pci_s_find_capability(pci_devfn_t dev, u16 cap) +{ + return pci_s_find_next_capability(dev, cap, 0); +} diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 5621b37da9..34684cb09a 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -49,7 +49,7 @@ int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset) if (class != PCI_EHCI_CLASSCODE) return -1; - u8 pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM); + u8 pm_cap = pci_s_find_capability(dbg_dev, PCI_CAP_ID_PM); if (pm_cap) { u16 pm_ctrl = pci_read_config16(dev, pm_cap + PCI_PM_CTRL); /* Set to D0 and disable PM events. */ @@ -58,7 +58,7 @@ int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset) pci_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl); } - u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG); + u8 pos = pci_s_find_capability(dbg_dev, PCI_CAP_ID_EHCI_DEBUG); if (!pos) return -1; diff --git a/src/include/device/pci.h b/src/include/device/pci.h index f1de7bffa2..5f72b55cff 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -125,16 +125,6 @@ static inline const struct pci_operations *ops_pci(struct device *dev) pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev); pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus); -#ifdef __SIMPLE_DEVICE__ -unsigned int pci_find_next_capability(pci_devfn_t dev, unsigned int cap, - unsigned int last); -unsigned int pci_find_capability(pci_devfn_t dev, unsigned int cap); -#else /* !__SIMPLE_DEVICE__ */ -unsigned int pci_find_next_capability(struct device *dev, unsigned int cap, - unsigned int last); -unsigned int pci_find_capability(struct device *dev, unsigned int cap); -#endif /* __SIMPLE_DEVICE__ */ - void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 454795f519..9a9c575e3c 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -175,4 +175,21 @@ void pci_update_config32(const struct device *dev, u16 reg, u32 mask, u32 or) pci_write_config32(dev, reg, reg32); } +u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last); +u16 pci_s_find_capability(pci_devfn_t dev, u16 cap); + +#ifndef __SIMPLE_DEVICE__ +static __always_inline +u16 pci_find_next_capability(const struct device *dev, u16 cap, u16 last) +{ + return pci_s_find_next_capability(PCI_BDF(dev), cap, last); +} + +static __always_inline +u16 pci_find_capability(const struct device *dev, u16 cap) +{ + return pci_s_find_capability(PCI_BDF(dev), cap); +} +#endif + #endif /* PCI_OPS_H */ diff --git a/src/soc/cavium/common/ecam.c b/src/soc/cavium/common/ecam.c index ae2a91fe0d..89c69dbc2e 100644 --- a/src/soc/cavium/common/ecam.c +++ b/src/soc/cavium/common/ecam.c @@ -17,6 +17,8 @@ * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ +#define __SIMPLE_DEVICE__ + #include #include #include @@ -27,15 +29,11 @@ * Get PCI BAR address from cavium specific extended capability. * Use regular BAR if not found in extended capability space. * - * @return The pyhsical address of the BAR, zero on error + * @return The physical address of the BAR, zero on error */ -#ifdef __SIMPLE_DEVICE__ uint64_t ecam0_get_bar_val(pci_devfn_t dev, u8 bar) -#else -uint64_t ecam0_get_bar_val(struct device *dev, u8 bar) -#endif { - size_t cap_offset = pci_find_capability(dev, 0x14); + size_t cap_offset = pci_s_find_capability(dev, 0x14); uint64_t h, l, ret = 0; if (cap_offset) { /* Found EA */ From 903b40a8a46b6e8d853f509480661c8174311f17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 3 Jul 2019 07:25:59 +0300 Subject: [PATCH 067/231] soc/intel: Replace uses of dev_find_slot() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To call dev_find_slot(0, xx) in romstage can produce invalid results since PCI bus enumeration has not been progressed yet. Replace this with method that relies on bus topology that walks the root bus only. Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/intel/apollolake/acpi.c | 4 ++-- src/soc/intel/apollolake/chip.c | 6 +++--- src/soc/intel/apollolake/include/soc/pci_devs.h | 4 ++-- src/soc/intel/apollolake/memmap.c | 2 +- src/soc/intel/apollolake/pmutil.c | 2 +- src/soc/intel/apollolake/romstage.c | 6 +++--- src/soc/intel/broadwell/acpi.c | 2 +- src/soc/intel/broadwell/include/soc/pci_devs.h | 4 ++-- src/soc/intel/broadwell/romstage/pch.c | 2 +- src/soc/intel/cannonlake/acpi.c | 4 ++-- src/soc/intel/cannonlake/fsp_params.c | 16 ++++++++-------- src/soc/intel/cannonlake/include/soc/pci_devs.h | 4 ++-- src/soc/intel/cannonlake/memmap.c | 2 +- src/soc/intel/cannonlake/pmutil.c | 2 +- src/soc/intel/cannonlake/romstage/fsp_params.c | 8 ++++---- src/soc/intel/cannonlake/smihandler.c | 2 +- .../intel/denverton_ns/include/soc/pci_devs.h | 4 ++-- src/soc/intel/denverton_ns/soc_util.c | 8 ++++---- src/soc/intel/denverton_ns/uart.c | 2 +- src/soc/intel/icelake/include/soc/pci_devs.h | 4 ++-- src/soc/intel/icelake/memmap.c | 2 +- src/soc/intel/icelake/pmutil.c | 2 +- src/soc/intel/icelake/smihandler.c | 2 +- src/soc/intel/skylake/acpi.c | 8 ++++---- src/soc/intel/skylake/chip.c | 8 ++++---- src/soc/intel/skylake/chip_fsp20.c | 10 +++++----- src/soc/intel/skylake/include/soc/pci_devs.h | 6 +++--- src/soc/intel/skylake/irq.c | 2 +- src/soc/intel/skylake/pmutil.c | 2 +- src/soc/intel/skylake/romstage/romstage.c | 2 +- src/soc/intel/skylake/romstage/romstage_fsp20.c | 4 ++-- src/soc/intel/skylake/romstage/systemagent.c | 4 ++-- 32 files changed, 70 insertions(+), 70 deletions(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 6208c9c739..cec706f5e0 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -186,7 +186,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) static unsigned long soc_fill_dmar(unsigned long current) { - struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); + struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK; bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; @@ -219,7 +219,7 @@ static unsigned long soc_fill_dmar(unsigned long current) * get the info and hide it again when done. */ p2sb_unhide(); - struct device *p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); + struct device *p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); uint16_t hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); p2sb_hide(); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index e9030dc2df..1d5e6d95ba 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -256,7 +256,7 @@ static void pcie_update_device_tree(unsigned int devfn0, int num_funcs) int i; unsigned int inc = PCI_DEVFN(0, 1); - func0 = dev_find_slot(0, devfn0); + func0 = pcidev_path_on_root(devfn0); if (func0 == NULL) return; @@ -272,7 +272,7 @@ static void pcie_update_device_tree(unsigned int devfn0, int num_funcs) * as that port was move to func0. */ for (i = 1; i < num_funcs; i++, devfn += inc) { - struct device *dev = dev_find_slot(0, devfn); + struct device *dev = pcidev_path_on_root(devfn); if (dev == NULL) continue; @@ -760,7 +760,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) apl_fsp_silicon_init_params_cb(cfg, silconfig); /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = dev_find_slot(0, PCH_DEVFN_XDCI); + dev = pcidev_path_on_root(PCH_DEVFN_XDCI); if (!xdci_can_enable()) dev->enabled = 0; silconfig->UsbOtg = dev->enabled; diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 335a485b78..a334f63468 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -22,8 +22,8 @@ #if !defined(__SIMPLE_DEVICE__) #include -#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 6058e34895..3436364b64 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -35,7 +35,7 @@ void *cbmem_top(void) if (!CONFIG(SOC_INTEL_GLK)) return tolum; - dev = dev_find_slot(0, PCH_DEVFN_LPC); + dev = pcidev_path_on_root(PCH_DEVFN_LPC); assert(dev != NULL); config = dev->chip_info; diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 22f53094a1..1bf3202f27 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -149,7 +149,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) DEVTREE_CONST struct soc_intel_apollolake_config *config; /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT); + DEVTREE_CONST struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 5d65a0029e..72a566a763 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -100,7 +100,7 @@ static void soc_early_romstage_init(void) /* Thermal throttle activation offset */ static void configure_thermal_target(void) { - const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT); + const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); if (!dev) { printk(BIOS_ERR, "Could not find SOC devicetree config\n"); return; @@ -320,7 +320,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd) { #if CONFIG(SOC_INTEL_GLK) /* Only for GLK */ - const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; @@ -350,7 +350,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd) static void parse_devicetree_setting(FSPM_UPD *m_upd) { #if CONFIG(SOC_INTEL_GLK) - DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_NPK); + DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK); if (!dev) return; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index e51c9bf7ce..25867c5677 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -580,7 +580,7 @@ void generate_cpu_entries(struct device *device) static unsigned long acpi_fill_dmar(unsigned long current) { - struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); + struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff; const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1; diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h index 03456ca105..522e3eb166 100644 --- a/src/soc/intel/broadwell/include/soc/pci_devs.h +++ b/src/soc/intel/broadwell/include/soc/pci_devs.h @@ -25,8 +25,8 @@ #else #include #include -#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) #endif /* System Agent Devices */ diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index ef97a1e3fa..ea2726bfa5 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -79,7 +79,7 @@ static void pch_enable_lpc(void) const struct device *dev; const config_t *config; - dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); if (!dev || !dev->chip_info) return; config = dev->chip_info; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index ff9da451c8..26c28472e1 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -293,7 +293,7 @@ int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) static unsigned long soc_fill_dmar(unsigned long current) { - struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); + struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; @@ -306,7 +306,7 @@ static unsigned long soc_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } - struct device *const ipu_dev = dev_find_slot(0, SA_DEVFN_IPU); + struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 783ebb7ab3..a58a97c060 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -51,7 +51,7 @@ static uint8_t get_param_value(const config_t *config, uint32_t dev_offset) { struct device *dev; - dev = dev_find_slot(0, serial_io_dev[dev_offset]); + dev = pcidev_path_on_root(serial_io_dev[dev_offset]); if (!dev || !dev->enabled) return PCH_SERIAL_IO_INDEX(PchSerialIoDisabled); @@ -178,7 +178,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchLockDownRtcMemoryLock = 0; /* SATA */ - dev = dev_find_slot(0, PCH_DEVFN_SATA); + dev = pcidev_path_on_root(PCH_DEVFN_SATA); if (!dev) params->SataEnable = 0; else { @@ -192,7 +192,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* Lan */ - dev = dev_find_slot(0, PCH_DEVFN_GBE); + dev = pcidev_path_on_root(PCH_DEVFN_GBE); if (!dev) params->PchLanEnable = 0; else { @@ -275,7 +275,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = dev_find_slot(0, PCH_DEVFN_USBOTG); + dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); if (dev) { if (!xdci_can_enable()) dev->enabled = 0; @@ -287,7 +287,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; /* Enable CNVi Wifi if enabled in device tree */ - dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI); + dev = pcidev_path_on_root(PCH_DEVFN_CNViWIFI); #if CONFIG(SOC_INTEL_COMETLAKE) if (dev) params->CnviMode = dev->enabled; @@ -314,7 +314,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(config->PcieRpHotPlug)); /* eMMC and SD */ - dev = dev_find_slot(0, PCH_DEVFN_EMMC); + dev = pcidev_path_on_root(PCH_DEVFN_EMMC); if (!dev) params->ScsEmmcEnabled = 0; else { @@ -329,7 +329,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } } - dev = dev_find_slot(0, PCH_DEVFN_SDCARD); + dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (!dev) { params->ScsSdCardEnabled = 0; } else { @@ -338,7 +338,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); } - dev = dev_find_slot(0, PCH_DEVFN_UFS); + dev = pcidev_path_on_root(PCH_DEVFN_UFS); if (!dev) params->ScsUfsEnabled = 0; else diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 2c932da162..46bc1bfa20 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -24,8 +24,8 @@ #if !defined(__SIMPLE_DEVICE__) #include -#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 3cae54fadb..355c36bd82 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -219,7 +219,7 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size) uintptr_t dram_base; const struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); + dev = pcidev_on_root(SA_DEV_SLOT_IGD, 0); if (!dev) die_with_post_code(POST_HW_INIT_FAILURE, "ERROR - IGD device not found!"); diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index ab36c70c10..9997d164e4 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -177,7 +177,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) DEVTREE_CONST struct soc_intel_cannonlake_config *config; /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); + DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index a1e3d76b4a..eb71f5dac5 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -30,7 +30,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) { unsigned int i; uint32_t mask = 0; - const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH); + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH); /* Set IGD stolen size to 64MB. */ m_cfg->IgdDvmt50PreAlloc = 2; @@ -85,7 +85,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->PchIshEnable = dev->enabled; /* If HDA is enabled, enable HDA elements */ - dev = dev_find_slot(0, PCH_DEVFN_HDA); + dev = pcidev_path_on_root(PCH_DEVFN_HDA); if (!dev) m_cfg->PchHdaEnable = 0; else @@ -100,8 +100,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); - const struct device *smbus = dev_find_slot(0, PCH_DEVFN_SMBUS); + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const struct device *smbus = pcidev_path_on_root(PCH_DEVFN_SMBUS); assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index e8f0d17833..cc5a7dd8ec 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -78,7 +78,7 @@ static void pch_disable_heci(void) void smihandler_soc_at_finalize(void) { const struct soc_intel_cannonlake_config *config; - const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE); + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index b902097d05..303ba67e65 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -27,8 +27,8 @@ #if ENV_RAMSTAGE #include #include -#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_##slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_##slot, func) diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c index ba7ba0f0b7..ef95f7e562 100644 --- a/src/soc/intel/denverton_ns/soc_util.c +++ b/src/soc/intel/denverton_ns/soc_util.c @@ -37,7 +37,7 @@ pci_devfn_t get_hostbridge_dev(void) #else struct device *get_hostbridge_dev(void) { - return dev_find_slot(0, PCI_DEVFN(SA_DEV, SA_FUNC)); + return pcidev_on_root(SA_DEV, SA_FUNC); } #endif @@ -49,7 +49,7 @@ pci_devfn_t get_lpc_dev(void) #else struct device *get_lpc_dev(void) { - return dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + return pcidev_on_root(LPC_DEV, LPC_FUNC); } #endif @@ -61,7 +61,7 @@ pci_devfn_t get_pmc_dev(void) #else struct device *get_pmc_dev(void) { - return dev_find_slot(0, PCI_DEVFN(PMC_DEV, PMC_FUNC)); + return pcidev_on_root(PMC_DEV, PMC_FUNC); } #endif @@ -73,7 +73,7 @@ pci_devfn_t get_smbus_dev(void) #else struct device *get_smbus_dev(void) { - return dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)); + return pcidev_on_root(SMBUS_DEV, SMBUS_FUNC); } #endif diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index 07e07045f5..50f8a290ae 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -76,7 +76,7 @@ static void hide_hsuarts(void) last one. */ for (i = DENVERTON_UARTS_TO_INI - 1; i >= 0; i--) { struct device *uart_dev; - uart_dev = dev_find_slot(0, PCI_DEVFN(HSUART_DEV, i)); + uart_dev = pcidev_on_root(HSUART_DEV, i); if (uart_dev == NULL) continue; pci_or_config32(uart_dev, PCI_FUNC_RDCFG_HIDE, 1); diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h index 889b5c5dde..b24211311a 100644 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ b/src/soc/intel/icelake/include/soc/pci_devs.h @@ -23,8 +23,8 @@ #if !defined(__SIMPLE_DEVICE__) #include -#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index f4467084ea..49af604c75 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -218,7 +218,7 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size) uintptr_t dram_base; const struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); + dev = pcidev_on_root(SA_DEV_SLOT_IGD, 0); if (!dev) die_with_post_code(POST_HW_INIT_FAILURE, "ERROR - IGD device not found!"); diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index cdb39ad591..0edec4bb1d 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -176,7 +176,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) DEVTREE_CONST struct soc_intel_icelake_config *config; /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); + DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 5fb2480604..a7ea0948ea 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -76,7 +76,7 @@ static void pch_disable_heci(void) void smihandler_soc_at_finalize(void) { const struct soc_intel_icelake_config *config; - const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE); + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index bd944dac16..910db970f6 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -174,7 +174,7 @@ static int get_cores_per_package(void) static void acpi_create_gnvs(global_nvs_t *gnvs) { - const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; /* Set unknown wake source */ @@ -561,7 +561,7 @@ void generate_cpu_entries(struct device *device) static unsigned long acpi_fill_dmar(unsigned long current) { - struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); + struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff; const bool gfxvten = MCHBAR32(GFXVTBAR) & 1; @@ -584,7 +584,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) acpi_dmar_rmrr_fixup(tmp, current); } - struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); + struct device *const p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1; @@ -695,7 +695,7 @@ void southbridge_inject_dsdt(struct device *device) /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { - const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; struct chipset_power_state *ps; static uint32_t gpe0_sts[GPE0_REG_MAX]; diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 6f90178f52..7f28340ba4 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -92,7 +92,7 @@ struct chip_operations soc_intel_skylake_ops = { /* UPD parameters to be initialized before SiliconInit */ void soc_silicon_init_params(SILICON_INIT_UPD *params) { - struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; int i; @@ -152,7 +152,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->ScsSdCardEnabled = config->ScsSdCardEnabled; /* Enable ISH if device is on */ - dev = dev_find_slot(0, PCH_DEVFN_ISH); + dev = pcidev_path_on_root(PCH_DEVFN_ISH); if (dev) params->IshEnable = dev->enabled; else @@ -219,11 +219,11 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) fill_vr_domain_config(params, i, &config->domain_vr_config[i]); /* Show SPI controller if enabled in devicetree.cb */ - dev = dev_find_slot(0, PCH_DEVFN_SPI); + dev = pcidev_path_on_root(PCH_DEVFN_SPI); params->ShowSpiController = dev->enabled; /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = dev_find_slot(0, PCH_DEVFN_USBOTG); + dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); if (!xdci_can_enable()) dev->enabled = 0; params->XdciEnable = dev->enabled; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index d179598699..08f5d79349 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -102,7 +102,7 @@ static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group, for (group = 0; group < pci_groups; group++) { devfn0 = pcie_rp_group[group].devfn; - func0 = dev_find_slot(0, devfn0); + func0 = pcidev_path_on_root(devfn0); if (func0 == NULL) continue; @@ -119,7 +119,7 @@ static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group, */ for (i = 1; i < pcie_rp_group[group].func_count; i++, devfn += inc) { - struct device *dev = dev_find_slot(0, devfn); + struct device *dev = pcidev_path_on_root(devfn); if (dev == NULL || !dev->enabled) continue; @@ -354,7 +354,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* If ISH is enabled, enable ISH elements */ - dev = dev_find_slot(0, PCH_DEVFN_ISH); + dev = pcidev_path_on_root(PCH_DEVFN_ISH); if (dev) params->PchIshEnable = dev->enabled; else @@ -433,11 +433,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) fill_vr_domain_config(params, i, &config->domain_vr_config[i]); /* Show SPI controller if enabled in devicetree.cb */ - dev = dev_find_slot(0, PCH_DEVFN_SPI); + dev = pcidev_path_on_root(PCH_DEVFN_SPI); params->ShowSpiController = dev->enabled; /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = dev_find_slot(0, PCH_DEVFN_USBOTG); + dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); if (!xdci_can_enable()) dev->enabled = 0; params->XdciEnable = dev->enabled; diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index d59c80008b..5acaaebc5a 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -24,8 +24,8 @@ #if !defined(__SIMPLE_DEVICE__) #include -#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) @@ -39,7 +39,7 @@ #define SA_DEV_SLOT_PEG 0x01 #define SA_DEVFN_PEG(func) PCI_DEVFN(SA_DEV_SLOT_PEG, func) -#define SA_DEV_PEG(func) dev_find_slot(0, SA_DEVFN_PEG(func)) +#define SA_DEV_PEG(func) pcidev_path_on_root(SA_DEVFN_PEG(func)) #define SA_DEV_PEG0 SA_DEV_PEG(0) #define SA_DEV_PEG1 SA_DEV_PEG(1) #define SA_DEV_PEG2 SA_DEV_PEG(2) diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index d10ca74f1e..03cdb071ce 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -223,7 +223,7 @@ void soc_irq_settings(FSP_SIL_UPD *params) uint32_t i, intdeventry; u8 irq_config[PCH_MAX_IRQ_CONFIG]; - const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; /* Get Device Int Count */ diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 7d0dc0adb8..9732aa1617 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -178,7 +178,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) DEVTREE_CONST struct soc_intel_skylake_config *config; /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); + DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 29c4774dc1..2bbab475af 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -57,7 +57,7 @@ void soc_memory_init_params(struct romstage_params *params, const struct soc_intel_skylake_config *config; /* Set the parameters for MemoryInit */ - dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); config = dev->chip_info; /* diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index fafa343780..6884a324a8 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -301,7 +301,7 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, { const struct device *dev; - dev = dev_find_slot(0, SA_DEVFN_IGD); + dev = pcidev_path_on_root(SA_DEVFN_IGD); if (!dev || !dev->enabled) { /* * If iGPU is disabled or not defined in the devicetree.cb, @@ -331,7 +331,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; - dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); config = dev->chip_info; soc_memory_init_params(m_cfg, config); diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 71a9bee1e0..00f620ff14 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -26,8 +26,8 @@ static void systemagent_vtd_init(void) { - const struct device *const root_dev = dev_find_slot(0, SA_DEVFN_ROOT); - const struct device *const igd_dev = dev_find_slot(0, SA_DEVFN_IGD); + const struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); const struct soc_intel_skylake_config *config = NULL; if (root_dev) From 7b2a88901f84f5dbdd03d6570262207726ad361a Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Wed, 3 Jul 2019 10:24:15 +0800 Subject: [PATCH 068/231] soc/intel/common: Increase SMM_MODULE_STACK_SIZE to 0x800 While running the s0ix cycling test, we observed SMM Handler caused a stack overflow. This error happens during event log access. This change is to increase the SMM_MODULE_STACK size to 0x800 BUG=b:135551854 TEST=suspend_resume test pass 500+ cycles, originally issue happenes within 150 cycle Change-Id: Ib4686b4d2d4fc3976068779314f4ee15ef4a8ae2 Signed-off-by: Kane Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/33999 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Paul Fagerburg Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index ac2268661f..523d1f56f4 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -68,4 +68,8 @@ config SOC_INTEL_DEBUG_CONSENT Set this option to enable default debug interface of SoC such as DBC or DCI. +config SMM_MODULE_STACK_SIZE + hex + default 0x800 + endif # SOC_INTEL_COMMON From b19946cc627b3c027a527bc51cfe2e08ead46b07 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Wed, 3 Jul 2019 14:40:11 -0600 Subject: [PATCH 069/231] console: Remove support for printing extra bases vtxprintf() can only print numbers in base 8, 10, and 16, so the extra letters in the alphabet aren't needed. Change-Id: I6a51c13f3298a597e801440f86bf698bdd8c736a Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/34028 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber --- src/console/vtxprintf.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 01091c82e8..2d4953d013 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -38,7 +38,7 @@ static int number(void (*tx_byte)(unsigned char byte, void *data), void *data) { char c, sign, tmp[66]; - const char *digits = "0123456789abcdefghijklmnopqrstuvwxyz"; + const char *digits = "0123456789abcdef"; int i; int count = 0; #ifdef SUPPORT_64BIT_INTS @@ -57,11 +57,9 @@ static int number(void (*tx_byte)(unsigned char byte, void *data), #endif if (type & LARGE) - digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; + digits = "0123456789ABCDEF"; if (type & LEFT) type &= ~ZEROPAD; - if (base < 2 || base > 36) - return 0; c = (type & ZEROPAD) ? '0' : ' '; sign = 0; if (type & SIGN) { From c764fb20122e7f6cb88855d4f671611aeb76df76 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Wed, 3 Jul 2019 12:38:46 -0600 Subject: [PATCH 070/231] console: Implement j specifier in vtxprintf() It is occasionally useful to print a uintmax_t or intmax_t, so add support for the j specifier. This also makes defining the PRI* macros in simpler. Change-Id: I656e3992029199b48e62a9df2d56f54c34e4e10f Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/34027 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes --- src/console/vtxprintf.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 2d4953d013..b50f3987a5 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -18,6 +18,7 @@ #include #include #include +#include #define call_tx(x) tx_byte(x, data) @@ -136,7 +137,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte, void *data), int field_width; /* width of output field */ int precision; /* min. # of digits for integers; max number of chars for from string */ - int qualifier; /* 'h', 'H', 'l', or 'L' for integer fields */ + int qualifier; /* 'h', 'H', 'l', 'L', 'z', or 'j' for integer fields */ int count; @@ -190,7 +191,7 @@ repeat: /* get the conversion qualifier */ qualifier = -1; - if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || *fmt == 'z') { + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || *fmt == 'z' || *fmt == 'j') { qualifier = *fmt; ++fmt; if (*fmt == 'l') { @@ -291,6 +292,8 @@ repeat: num = va_arg(args, unsigned long); } else if (qualifier == 'z') { num = va_arg(args, size_t); + } else if (qualifier == 'j') { + num = va_arg(args, uintmax_t); } else if (qualifier == 'h') { num = (unsigned short) va_arg(args, int); if (flags & SIGN) From c32ccb779c56f7a0256fbad0bba3311b5eba2289 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 14 Jun 2019 23:27:26 +0200 Subject: [PATCH 071/231] device/pci_rom.c: Fix indent for 'if' statement Change-Id: Ie9adb60323742d379cc4ad0af069a793b9ddd79b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33330 Reviewed-by: Paul Menzel Reviewed-by: Jacob Garber Tested-by: build bot (Jenkins) --- src/device/pci_rom.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 31fe115c89..34a9a81a52 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -56,9 +56,9 @@ struct rom_header *pci_rom_probe(struct device *dev) printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n", dev_path(dev), rom_header); } else if (!CONFIG(ON_DEVICE_ROM_LOAD)) { - printk(BIOS_DEBUG, "PCI Option ROM loading disabled " - "for %s\n", dev_path(dev)); - return NULL; + printk(BIOS_DEBUG, "PCI Option ROM loading disabled for %s\n", + dev_path(dev)); + return NULL; } else { uintptr_t rom_address; From 65f03b7c42152188fbd5ac13cea05aaeb953df31 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Mon, 1 Jul 2019 08:14:39 -0600 Subject: [PATCH 072/231] soc/intel/cannonlake: Fix PMC and GPIO block values for PCH-H MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some of the values used for GPIO_CFG and MISCCFG were not correct, causing GPEs to not work correctly. This adjusts them according to the values found in the original ACPI tables for the System76 Gazelle. Unfortunately, the Intel documentation[1] mentioned below is also incorrect. I have mentioned this to Intel already. The source for the Intel CoffeeLake FSP also confirms these new numbers. This was tested on a System76 Gazelle (gaze14). The EC uses GPP_K3 for its GPE and GPP_K6 is used for the lid switch GPE. Both function correctly after applying this change. [1] Intel Document #572235: Intel ® 300 Series Chipset Families Platform Controller Hub External Design Specification (EDS) - Volume 2 of 2 Change-Id: I4ecc9552468037598ef5d4e10122d660dcbfe71d Signed-off-by: Jeremy Soller Reviewed-on: https://review.coreboot.org/c/coreboot/+/33941 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Felix Held --- .../include/soc/gpio_soc_defs_cnp_h.h | 24 +++++++++---------- src/soc/intel/cannonlake/include/soc/pmc.h | 19 +++++++++------ 2 files changed, 24 insertions(+), 19 deletions(-) diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h index 5176ac734a..23953142d7 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h @@ -22,18 +22,18 @@ * communities. */ -#define GPP_A 0 -#define GPP_B 1 -#define GPP_C 2 -#define GPP_D 3 -#define GPP_G 4 -#define GPP_K 5 -#define GPP_H 6 -#define GPP_E 7 -#define GPP_F 8 -#define GPP_I 9 -#define GPP_J 0xA -#define GPD 0xC +#define GPP_A 0x0 +#define GPP_B 0x1 +#define GPP_C 0x2 +#define GPP_D 0x3 +#define GPP_G 0x4 +#define GPD 0x5 +#define GPP_E 0x6 +#define GPP_F 0x7 +#define GPP_H 0x8 +#define GPP_K 0x9 +#define GPP_I 0xA +#define GPP_J 0xB #define GPIO_NUM_GROUPS 12 #define GPIO_MAX_NUM_PER_GROUP 24 diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 67854d4cbd..e0d2614e8e 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -117,18 +117,23 @@ #define GPE0_DW_SHIFT(x) (4*(x)) #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) +/* + * The values for GPIO_CFG in Intel Document #572235 are incorrect. + * These values now match what is used by the Intel CoffeeLake FSP, + * please do not modify them. + */ #define PMC_GPP_A 0x0 #define PMC_GPP_B 0x1 #define PMC_GPP_C 0x2 #define PMC_GPP_D 0x3 -#define PMC_GPP_E 0x7 -#define PMC_GPP_F 0x8 +#define PMC_GPP_E 0xA +#define PMC_GPP_F 0xB #define PMC_GPP_G 0x4 -#define PMC_GPP_H 0x6 -#define PMC_GPP_I 0x9 -#define PMC_GPP_J 0xA -#define PMC_GPP_K 0x5 -#define PMC_GPD 0xC +#define PMC_GPP_H 0x9 +#define PMC_GPP_I 0xC +#define PMC_GPP_J 0xD +#define PMC_GPP_K 0x8 +#define PMC_GPD 0x7 #else #define PMC_GPP_A 0x0 #define PMC_GPP_B 0x1 From 4f61f56be101d472990d631ab592f328117d5dbc Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 4 Jul 2019 16:26:58 +0530 Subject: [PATCH 073/231] soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE width As per EDS Sata port implemented register is byte width (bits[3:0]) hence converting required DWORD based read/write to BYTE width read/write. TEST=Able to boot from SATA device on CML hatch. Change-Id: I545b823318bae461137d41a4490117eba7c87330 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/34070 Reviewed-by: Aamir Bohra Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/sata/sata.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 0801cb77c4..7dacc6ed92 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -43,14 +43,14 @@ static void *sata_get_ahci_bar(struct device *dev) static void sata_final(struct device *dev) { void *ahcibar = sata_get_ahci_bar(dev); - u32 port_impl, temp; + u8 port_impl, temp; /* Set Bus Master */ temp = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER); /* Read Ports Implemented (GHC_PI) */ - port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED); + port_impl = read8(ahcibar + SATA_ABAR_PORT_IMPLEMENTED); if (CONFIG(SOC_AHCI_PORT_IMPLEMENTED_INVERT)) port_impl = ~port_impl; @@ -58,9 +58,9 @@ static void sata_final(struct device *dev) port_impl &= 0x07; /* bit 0-2 */ /* Port enable */ - temp = pci_read_config32(dev, SATA_PCI_CFG_PORT_CTL_STS); + temp = pci_read_config8(dev, SATA_PCI_CFG_PORT_CTL_STS); temp |= port_impl; - pci_write_config32(dev, SATA_PCI_CFG_PORT_CTL_STS, temp); + pci_write_config8(dev, SATA_PCI_CFG_PORT_CTL_STS, temp); } static struct device_operations sata_ops = { From 5ee4c12ebb8ad82a62ab2325a9e972757534962e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 5 Jul 2019 06:43:46 +0530 Subject: [PATCH 074/231] soc/intel/cannonlake: Override PRERAM_CBMEM_CONSOLE_SIZE default value This patch increases PRERAM_CBMEM_CONSOLE_SIZE to fix *** Pre-CBMEM romstage console overflowed, log truncated! *** issue. TEST=Verified on Hatch CML platform. Change-Id: I2de4ca2f2001b304850c27df1b3c3b2c827fe25a Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/34006 Tested-by: build bot (Jenkins) Reviewed-by: V Sowmya Reviewed-by: Spoorthi K Reviewed-by: Nico Huber --- src/soc/intel/cannonlake/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d697620725..5e405db4d8 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -326,4 +326,8 @@ config USE_LEGACY_8254_TIMER This sets the Enable8254ClockGating UPD, which according to the FSP Integration guide needs to be disabled in order to boot SeaBIOS, but should otherwise be enabled. +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xe00 + endif From e458bcd099b5fd97c39a424bcc47e99818942487 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Mon, 1 Jul 2019 07:52:19 -0600 Subject: [PATCH 075/231] soc/intel/cannonlake: Fix outb order outb accepts a value followed by a port Change-Id: I6fe3961b4f8cb2454e3b2564c3eae6af06c9e69d Signed-off-by: Jeremy Soller Reviewed-on: https://review.coreboot.org/c/coreboot/+/33940 Reviewed-by: Paul Menzel Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/lpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 6cc34515d7..1fe04169c1 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -201,10 +201,10 @@ static void pch_misc_init(void) /* Setup NMI on errors, disable SERR */ reg8 = (inb(0x61)) & 0xf0; - outb(0x61, (reg8 | (1 << 2))); + outb((reg8 | (1 << 2)), 0x61); /* Disable NMI sources */ - outb(0x70, (1 << 7)); + outb((1 << 7), 0x70); }; void lpc_soc_init(struct device *dev) From fcfa35670a191d2313324fb313bac237e7a3d0c6 Mon Sep 17 00:00:00 2001 From: Ran Bi Date: Wed, 17 Apr 2019 15:43:14 +0800 Subject: [PATCH 076/231] mediatek/mt8183: Enable RTC eosc calibration feature to save power When system shuts down, RTC enable eosc calibration feature to save power. Then coreboot RTC driver needs to call rtc_enable_dcxo function at every boot to switch RTC clock source to dcxo. BUG=b:128467245 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748 Signed-off-by: Ran Bi Reviewed-on: https://review.coreboot.org/c/coreboot/+/32339 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/mediatek/common/rtc.c | 9 +++++--- src/soc/mediatek/mt8183/include/soc/rtc.h | 25 +++++++++++++++-------- src/soc/mediatek/mt8183/rtc.c | 25 ++++++++++------------- 3 files changed, 33 insertions(+), 26 deletions(-) diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index a9142b612d..fe252b5d64 100644 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -91,12 +91,15 @@ int rtc_xosc_write(u16 val) u16 bbpu; rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1); - udelay(200); + if (!rtc_busy_wait()) + return 0; rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2); - udelay(200); + if (!rtc_busy_wait()) + return 0; rtc_write(RTC_OSC32CON, val); - udelay(200); + if (!rtc_busy_wait()) + return 0; rtc_read(RTC_BBPU, &bbpu); bbpu |= RTC_BBPU_KEY | RTC_BBPU_RELOAD; diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 3d115fec41..841a202519 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -100,18 +100,25 @@ enum { }; enum { - RTC_EMBCK_SRC_SEL = 1 << 8, - RTC_EMBCK_SEL_MODE = 3 << 6, - RTC_XOSC32_ENB = 1 << 5, - RTC_REG_XOSC32_ENB = 1 << 15 + RTC_XOSCCALI_MASK = 0x1F << 0, + RTC_XOSC32_ENB = 1U << 5, + RTC_EMB_HW_MODE = 0U << 6, + RTC_EMB_K_EOSC32_MODE = 1U << 6, + RTC_EMB_SW_DCXO_MODE = 2U << 6, + RTC_EMB_SW_EOSC32_MODE = 3U << 6, + RTC_EMBCK_SEL_MODE_MASK = 3U << 6, + RTC_EMBCK_SRC_SEL = 1U << 8, + RTC_EMBCK_SEL_OPTION = 1U << 9, + RTC_GPS_CKOUT_EN = 1U << 10, + RTC_REG_XOSC32_ENB = 1U << 15 }; enum { - RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0 << 13, - RTC_LPD_OPT_EOSC_LPD = 1 << 13, - RTC_LPD_OPT_XOSC_LPD = 2 << 13, - RTC_LPD_OPT_F32K_CK_ALIVE = 3 << 13, - RTC_LPD_OPT_MASK = 3 << 13 + RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13, + RTC_LPD_OPT_EOSC_LPD = 1U << 13, + RTC_LPD_OPT_XOSC_LPD = 2U << 13, + RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13, + RTC_LPD_OPT_MASK = 3U << 13 }; /* PMIC TOP Register Definition */ diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 62256ebc1b..5879088434 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -33,20 +33,19 @@ static int rtc_enable_dcxo(void) mdelay(1); if (!rtc_writeif_unlock()) { /* Unlock for reload */ - rtc_info("rtc_writeif_unlock() fail\n"); + rtc_info("rtc_writeif_unlock() failed\n"); return 0; } rtc_read(RTC_OSC32CON, &osc32con); - osc32con &= ~RTC_EMBCK_SRC_SEL; - osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB; + osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK + | RTC_GPS_CKOUT_EN); + osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB + | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION; if (!rtc_xosc_write(osc32con)) { - rtc_info("rtc_xosc_write() fail\n"); + rtc_info("rtc_xosc_write() failed\n"); return 0; } - rtc_read(RTC_BBPU, &bbpu); - rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); - rtc_write_trigger(); rtc_read(RTC_CON, &con); rtc_read(RTC_OSC32CON, &osc32con); @@ -197,12 +196,6 @@ int rtc_init(u8 recover) goto err; } - /* using dcxo 32K clock */ - if (!rtc_enable_dcxo()) { - ret = -RTC_STATUS_OSC_SETTING_FAIL; - goto err; - } - if (recover) mdelay(20); @@ -264,7 +257,7 @@ void poweroff(void) u16 bbpu; if (!rtc_writeif_unlock()) - rtc_info("rtc_writeif_unlock() fail\n"); + rtc_info("rtc_writeif_unlock() failed\n"); /* pull PWRBB low */ bbpu = RTC_BBPU_KEY | RTC_BBPU_RELOAD | RTC_BBPU_PWREN; rtc_write(RTC_BBPU, bbpu); @@ -311,6 +304,10 @@ void rtc_boot(void) pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0); pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0); + /* use dcxo 32K clock */ + if (!rtc_enable_dcxo()) + rtc_info("rtc_enable_dcxo() failed\n"); + rtc_boot_common(); rtc_bbpu_power_on(); } From 78025f6c5c8a65d662c3af7d8de2ad5a59752419 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 13 Jun 2019 16:03:47 -0600 Subject: [PATCH 077/231] soc/amd/picasso: Remove all AGESA references Family 17h will not use the Arch2008 (a.k.a. v5) wrapper. Remove all source, support functions, and comments related to AGESA. Family 17h requires v9 which has no similarities to v5 for integration into a host firmware. AGESA v9 support will be added via subsequent patches into the appropriate locations. Change-Id: Iea1a41941a0ba364a6abaaf31cc8e1145db4a236 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/33755 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Martin Roth --- src/soc/amd/picasso/Kconfig | 17 +- src/soc/amd/picasso/chip.c | 21 --- src/soc/amd/picasso/chip.h | 36 ----- src/soc/amd/picasso/include/soc/cpu.h | 10 +- src/soc/amd/picasso/include/soc/northbridge.h | 2 + src/soc/amd/picasso/include/soc/southbridge.h | 4 +- src/soc/amd/picasso/northbridge.c | 147 +----------------- src/soc/amd/picasso/romstage.c | 117 -------------- src/soc/amd/picasso/southbridge.c | 56 ------- 9 files changed, 7 insertions(+), 403 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 33aae2655f..a930f60d27 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -49,8 +49,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA - select SOC_AMD_COMMON_BLOCK_PI - select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH @@ -106,18 +104,6 @@ config CPU_ADDR_BITS int default 48 -config BOTTOMIO_POSITION - hex "Bottom of 32-bit IO space" - default 0xD0000000 - help - If PCI peripherals with big BARs are connected to the system - the bottom of the IO must be decreased to allocate such - devices. - - Declare the beginning of the 128MB-aligned MMIO region. This - option is useful when PCI peripherals requesting large address - ranges are present. - config MMCONF_BASE_ADDRESS hex default 0xF8000000 @@ -199,7 +185,7 @@ config PICASSO_LEGACY_FREE bool "System is legacy free" help Select y if there is no keyboard controller in the system. - This sets variables in AGESA and ACPI. + This sets a variable in ACPI. config SERIRQ_CONTINUOUS_MODE bool @@ -213,7 +199,6 @@ config PICASSO_ACPI_IO_BASE default 0x400 help Base address for the ACPI registers. - This value must match the hardcoded value of AGESA. config PICASSO_UART bool "UART controller on Picasso" diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index b9e98c538c..65d98b127d 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -25,9 +25,6 @@ #include #include #include -#include -#include - #include "chip.h" /* Supplied by i2c.c */ @@ -113,7 +110,6 @@ const char *soc_acpi_name(const struct device *dev) struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .scan_bus = pci_domain_scan_bus, .acpi_name = soc_acpi_name, }; @@ -141,7 +137,6 @@ static void soc_init(void *chip_info) static void soc_final(void *chip_info) { southbridge_final(chip_info); - fam15_finalize(chip_info); } struct chip_operations soc_amd_picasso_ops = { @@ -150,19 +145,3 @@ struct chip_operations soc_amd_picasso_ops = { .init = soc_init, .final = soc_final }; - -static void earliest_ramstage(void *unused) -{ - int s3_resume = acpi_s3_resume_allowed() && - romstage_handoff_is_resume(); - if (!s3_resume) { - post_code(0x47); - do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); - } else { - /* Complete the initial system restoration */ - post_code(0x46); - do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); - } -} - -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, earliest_ramstage, NULL); diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index ff9c845898..39c70269da 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -23,33 +23,9 @@ #include #include -#define MAX_NODES 1 -#define MAX_DRAM_CH 1 -#define MAX_DIMMS_PER_CH 2 - #define PICASSO_I2C_DEV_MAX 4 struct soc_amd_picasso_config { - u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH]; - enum { - DRAM_CONTENTS_KEEP, - DRAM_CONTENTS_CLEAR - } dram_clear_on_reset; - - enum { - /* Do not enable UMA in the system. */ - UMAMODE_NONE, - /* Enable UMA with a specific size. */ - UMAMODE_SPECIFIED_SIZE, - /* Let AGESA determine the proper size. Non-legacy requires - * the resolution to be specified PLATFORM_CONFIGURATION */ - UMAMODE_AUTO_LEGACY, - UMAMODE_AUTO_NON_LEGACY, - } uma_mode; - - /* Used if UMAMODE_SPECIFIED_SIZE is set. */ - size_t uma_size; - /* * If sb_reset_i2c_slaves() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. @@ -60,18 +36,6 @@ struct soc_amd_picasso_config { */ u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[PICASSO_I2C_DEV_MAX]; - u8 stapm_percent; - u32 stapm_time_ms; - u32 stapm_power_mw; - /* - * This specifies the LVDS/eDP power-up sequence time for the delay - * between VaryBL and BLON. - * 0 - Use the VBIOS default (default). The video BIOS default is 32ms. - * n - Values other than zero specify a setting of (4 * n) milliseconds - * time delay. - */ - u8 lvds_poseq_varybl_to_blon; - u8 lvds_poseq_blon_to_varybl; }; typedef struct soc_amd_picasso_config config_t; diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 7d4764567a..7bc1810dba 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -18,16 +18,8 @@ #include -/* - * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest - * numbered registers. Any values defined below are subtracted from the - * highest numbered registers. - * - * todo: Revisit this once AGESA no longer programs MTRRs. - */ #define SOC_EARLY_VMTRR_FLASH 1 -#define SOC_EARLY_VMTRR_CAR_HEAP 2 -#define SOC_EARLY_VMTRR_TEMPRAM 3 +#define SOC_EARLY_VMTRR_TEMPRAM 2 void picasso_init_cpus(struct device *dev); void check_mca(void); diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index f7df2772c5..65705b93f3 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -110,6 +110,8 @@ enum { SMM_SUBREGION_NUM, }; +void amd_initcpuio(void); + /* * Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index b28522e60f..565ab3084d 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -322,7 +322,7 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); void bootblock_fch_early_init(void); void bootblock_fch_init(void); /** - * @brief Save the UMA bize returned by AGESA + * @brief Save the UMA bize * * @param size = in bytes * @@ -330,7 +330,7 @@ void bootblock_fch_init(void); */ void save_uma_size(uint32_t size); /** - * @brief Save the UMA base address returned by AGESA + * @brief Save the UMA base address * * @param base = 64bit base address * diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 5985832c81..627ce03833 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -27,9 +27,6 @@ #include #include #include -#include -#include -#include #include #include #include @@ -188,26 +185,6 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static unsigned long acpi_fill_hest(acpi_hest_t *hest) -{ - void *addr, *current; - - /* Skip the HEST header. */ - current = (void *)(hest + 1); - - addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); - if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, - (void *)((u32)addr + 2), *(uint16_t *)addr - 2); - - addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); - if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, - (void *)((u32)addr + 2), *(uint16_t *)addr - 2); - - return (unsigned long)current; -} - static void northbridge_fill_ssdt_generator(struct device *device) { msr_t msr; @@ -233,106 +210,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *alib; - acpi_header_t *ivrs; - acpi_hest_t *hest; - acpi_bert_t *bert; - - /* HEST */ - current = ALIGN(current, 8); - hest = (acpi_hest_t *)current; - acpi_write_hest(hest, acpi_fill_hest); - acpi_add_table(rsdp, (void *)current); - current += hest->header.length; - - /* BERT */ - if (CONFIG(ACPI_BERT) && bert_errors_present()) { - /* Skip the table if no errors are present. ACPI driver reports - * a table with a 0-length region: - * BERT: [Firmware Bug]: table invalid. - */ - void *rgn; - size_t size; - bert_errors_region(&rgn, &size); - if (!rgn) { - printk(BIOS_ERR, "Error: Can't find BERT storage area\n"); - } else { - current = ALIGN(current, 8); - bert = (acpi_bert_t *)current; - acpi_write_bert(bert, (uintptr_t)rgn, size); - acpi_add_table(rsdp, (void *)current); - current += bert->header.length; - } - } - - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); - ivrs = agesawrapper_getlateinitptr(PICK_IVRS); - if (ivrs != NULL) { - memcpy((void *)current, ivrs, ivrs->length); - ivrs = (acpi_header_t *)current; - current += ivrs->length; - acpi_add_table(rsdp, ivrs); - } else { - printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); - } - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); - if (srat != NULL) { - memcpy((void *)current, srat, srat->header.length); - srat = (acpi_srat_t *)current; - current += srat->header.length; - acpi_add_table(rsdp, srat); - } else { - printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); - } - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); - if (slit != NULL) { - memcpy((void *)current, slit, slit->header.length); - slit = (acpi_slit_t *)current; - current += slit->header.length; - acpi_add_table(rsdp, slit); - } else { - printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); - } - - /* ALIB */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); - alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); - if (alib != NULL) { - memcpy((void *)current, alib, alib->length); - alib = (acpi_header_t *)current; - current += alib->length; - acpi_add_table(rsdp, (void *)alib); - } else { - printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL." - " Skipping.\n"); - } - - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); - if (ssdt != NULL) { - memcpy((void *)current, ssdt, ssdt->length); - ssdt = (acpi_header_t *)current; - current += ssdt->length; - } else { - printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); - } - acpi_add_table(rsdp, ssdt); - - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + /* TODO - different mechanism to collect this info for Family 17h */ return current; } @@ -399,13 +277,6 @@ void fam15_finalize(void *chip_info) pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value); } -void domain_enable_resources(struct device *dev) -{ - /* Must be called after PCI enumeration and resource allocation */ - if (!romstage_handoff_is_resume()) - do_agesawrapper(AMD_INIT_MID, "amdinitmid"); -} - void domain_set_resources(struct device *dev) { uint64_t uma_base = get_uma_base(); @@ -474,19 +345,3 @@ u32 map_oprom_vendev(u32 vendev) return new_vendev; } - -__weak void set_board_env_params(GNB_ENV_CONFIGURATION *params) { } - -void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) -{ - const struct device *dev = SOC_IOMMU_DEV; - params->IommuSupport = dev && dev->enabled; - set_board_env_params(params); -} - -void SetNbMidParams(GNB_MID_CONFIGURATION *params) -{ - /* 0=Primary and decode all VGA resources, 1=Secondary - decode none */ - params->iGpuVgaMode = 0; - params->GnbIoapicAddress = IO_APIC2_ADDR; -} diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 904f556202..950b41f5a3 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -27,8 +27,6 @@ #include #include #include -#include -#include #include #include #include @@ -40,22 +38,6 @@ void __weak mainboard_romstage_entry(int s3_resume) /* By default, don't do anything */ } -static void agesa_call(void) -{ - post_code(0x37); - do_agesawrapper(AMD_INIT_RESET, "amdinitreset"); - - post_code(0x38); - /* APs will not exit amdinitearly */ - do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); -} - -static void bsp_agesa_call(void) -{ - set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */ - agesa_call(); -} - asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -63,58 +45,20 @@ asmlinkage void car_stage_entry(void) void *smm_base; size_t smm_size; uintptr_t tseg_base; - msr_t base, mask; - msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); - int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); - int i; console_init(); mainboard_romstage_entry(s3_resume); - bsp_agesa_call(); - if (!s3_resume) { post_code(0x40); - do_agesawrapper(AMD_INIT_POST, "amdinitpost"); - post_code(0x41); - /* - * TODO: This is a hack to work around current AGESA behavior. - * AGESA needs to change to reflect that coreboot owns - * the MTRRs. - * - * After setting up DRAM, AGESA also completes the configuration - * of the MTRRs, setting regions to WB. Anything written to - * memory between now and and when CAR is dismantled will be - * in cache and lost. For now, set the regions UC to ensure - * the writes get to DRAM. - */ - for (i = 0 ; i < vmtrrs ; i++) { - base = rdmsr(MTRR_PHYS_BASE(i)); - mask = rdmsr(MTRR_PHYS_MASK(i)); - if (!(mask.lo & MTRR_PHYS_MASK_VALID)) - continue; - - if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) { - base.lo &= ~0x7; - base.lo |= MTRR_TYPE_UNCACHEABLE; - wrmsr(MTRR_PHYS_BASE(i), base); - } - } - /* Disable WB from to region 4GB-TOM2. */ - msr_t sys_cfg = rdmsr(SYSCFG_MSR); - sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; - wrmsr(SYSCFG_MSR, sys_cfg); if (CONFIG(ELOG_BOOT_COUNT)) boot_count_increment(); } else { printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); - - post_code(0x61); } post_code(0x43); @@ -155,64 +99,3 @@ asmlinkage void car_stage_entry(void) post_code(0x50); /* Should never see this post code. */ } - -void SetMemParams(AMD_POST_PARAMS *PostParams) -{ - const struct soc_amd_picasso_config *cfg; - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n"); - /* In case of a BIOS error, only attempt to set UMA. */ - PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? - UMA_AUTO : UMA_NONE; - return; - } - - cfg = dev->chip_info; - - PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset; - - switch (cfg->uma_mode) { - case UMAMODE_NONE: - PostParams->MemConfig.UmaMode = UMA_NONE; - break; - case UMAMODE_SPECIFIED_SIZE: - PostParams->MemConfig.UmaMode = UMA_SPECIFIED; - /* 64 KiB blocks. */ - PostParams->MemConfig.UmaSize = cfg->uma_size / (64 * KiB); - break; - case UMAMODE_AUTO_LEGACY: - PostParams->MemConfig.UmaMode = UMA_AUTO; - PostParams->MemConfig.UmaVersion = UMA_LEGACY; - break; - case UMAMODE_AUTO_NON_LEGACY: - PostParams->MemConfig.UmaMode = UMA_AUTO; - PostParams->MemConfig.UmaVersion = UMA_NON_LEGACY; - break; - } -} - -void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) -{ - const struct soc_amd_picasso_config *cfg; - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - struct _PLATFORM_CONFIGURATION *platform; - - if (!dev || !dev->chip_info) { - printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree" - " config, STAPM unchanged\n"); - return; - } - cfg = dev->chip_info; - platform = &InitEarly->PlatformConfig; - if ((cfg->stapm_percent) && (cfg->stapm_time_ms) && - (cfg->stapm_power_mw)) { - platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent; - platform->PlatStapmConfig.CfgStapmTimeConstant = - cfg->stapm_time_ms; - platform->PkgPwrLimitDC = cfg->stapm_power_mw; - platform->PkgPwrLimitAC = cfg->stapm_power_mw; - platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled; - } -} diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 87b933e119..84c15a7595 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -34,7 +33,6 @@ #include #include #include -#include #include #include @@ -54,60 +52,6 @@ const static struct picasso_aoac aoac_devs[] = { { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } }; -static int is_sata_config(void) -{ - return !((SataNativeIde == CONFIG_PICASSO_SATA_MODE) - || (SataLegacyIde == CONFIG_PICASSO_SATA_MODE)); -} - -static inline int sb_sata_enable(void) -{ - /* True if IDE or AHCI. */ - return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) || - (SataAhci == CONFIG_PICASSO_SATA_MODE); -} - -static inline int sb_ide_enable(void) -{ - /* True if IDE or LEGACY IDE. */ - return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) || - (SataLegacyIde == CONFIG_PICASSO_SATA_MODE); -} - -void SetFchResetParams(FCH_RESET_INTERFACE *params) -{ - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - if (dev && dev->enabled) { - params->SataEnable = sb_sata_enable(); - params->IdeEnable = sb_ide_enable(); - } else { - params->SataEnable = FALSE; - params->IdeEnable = FALSE; - } -} - -void SetFchEnvParams(FCH_INTERFACE *params) -{ - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - params->AzaliaController = AzEnable; - params->SataClass = CONFIG_PICASSO_SATA_MODE; - if (dev && dev->enabled) { - params->SataEnable = is_sata_config(); - params->IdeEnable = !params->SataEnable; - params->SataIdeMode = (CONFIG_PICASSO_SATA_MODE == - SataLegacyIde); - } else { - params->SataEnable = FALSE; - params->IdeEnable = FALSE; - params->SataIdeMode = FALSE; - } -} - -void SetFchMidParams(FCH_INTERFACE *params) -{ - SetFchEnvParams(params); -} - /* * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME * provides a visible association with the index, therefore helping From 490b1d3b945b125627498cb3d695e4a0be699337 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 2 Jul 2019 23:22:36 +0800 Subject: [PATCH 078/231] soc/intel/icelake: Fix outb order Similar to CB:33940, fix outb orders. Change-Id: I1d35235abc7e02e6058f07809b738635861cc9e4 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/33960 Tested-by: build bot (Jenkins) Reviewed-by: Jeremy Soller Reviewed-by: Subrata Banik --- src/soc/intel/icelake/espi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 9ca0c7c295..8ab909d861 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -194,10 +194,10 @@ static void pch_misc_init(void) /* Setup NMI on errors, disable SERR */ reg8 = (inb(0x61)) & 0xf0; - outb(0x61, (reg8 | (1 << 2))); + outb((reg8 | (1 << 2)), 0x61); /* Disable NMI sources */ - outb(0x70, (1 << 7)); + outb((1 << 7), 0x70); }; static void clock_gate_8254(const struct device *dev) From 8d7d98166e87cd5ac68d038110e9407b1730b1bb Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 17 Oct 2018 10:20:34 +0200 Subject: [PATCH 079/231] mb/lenovo/t60: Align ACPI C-state across the similar boards We have 3 similar Lenovo mainboards - x60 (oldest), t60, and z61t (most recent addition). The only one with two consequent 2s as the C-types is t60: static acpi_cstate_t cst_entries[] = { { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } }, { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } }, { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } }, }; It seems that 3 could be a better choice for the last line here. UNTESTED on a real hardware. Change-Id: I090e82d5f4ae25c768ff45a01a8dd76ff8a96a90 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/29160 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/lenovo/t60/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index b78d862d41..5f599465a1 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -31,7 +31,7 @@ static acpi_cstate_t cst_entries[] = { { 1, 1, 1000, { 0x7f, 1, 2, 0, 1, 0 } }, { 2, 1, 500, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 0 } }, - { 2, 17, 250, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 0 } }, + { 3, 17, 250, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 0 } }, }; int get_cst_entries(acpi_cstate_t **entries) From db6c3f25f0d4b7fc0fd7aefb0b2442584a7f2c99 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 26 Jun 2019 21:05:17 +0200 Subject: [PATCH 080/231] include/cpu/x86/mtrr: Fix return type MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fms() and fls() returns an 'unsigned int'. Change-Id: Ia328e1e5a79c2e7606961bb1b68c01db6b77da21 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33817 Reviewed-by: Nico Huber Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/include/cpu/x86/mtrr.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 49ed462952..29256c8d46 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -120,7 +120,7 @@ asmlinkage void soc_enable_mtrrs(void); /* fms: find most significant bit set, stolen from Linux Kernel Source. */ static inline unsigned int fms(unsigned int x) { - int r; + unsigned int r; __asm__("bsrl %1,%0\n\t" "jnz 1f\n\t" @@ -132,7 +132,7 @@ static inline unsigned int fms(unsigned int x) /* fls: find least significant bit set */ static inline unsigned int fls(unsigned int x) { - int r; + unsigned int r; __asm__("bsfl %1,%0\n\t" "jnz 1f\n\t" From a913b3df90da925246936cb421afe01901172211 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 6 Jul 2019 22:09:28 -0700 Subject: [PATCH 081/231] soc/intel/cannonlake: Use SA_DEV_ROOT instead of PCH_DEV_PMC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PMC device gets hidden from PCI bus after FSP-S call. Thus, it gets removed from the root bus as leftover unused device. With change 903b40a8a46 ("soc/intel: Replace uses of dev_find_slot()"), all uses of dev_find_slot() were replaced by pcidev_path_on_root() which relies on scanning of root bus to find the requested device. Since PMC device is removed from the root bus, pcidev_path_on_root() returns NULL for it thus resulting in configuration being skipped for the PMC ultimately resulting in S3 failures. Since the PCH_DEV_PMC was just used to get to chip config, this change replaces the use of PCH_DEV_PMC with SA_DEV_ROOT. BUG=b:136861224 TEST=Verified that S3 works fine on hatch. Change-Id: Ie5ade00ac2aca697608f1bdea9764b71c26e2112 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/34116 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Subrata Banik --- src/soc/intel/cannonlake/finalize.c | 7 ++++++- src/soc/intel/cannonlake/pmc.c | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 4dfd15bc4a..d099d7779a 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -68,8 +68,13 @@ static void pch_finalize(void) * * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. * Disabling ACPI PM timer also switches off TCO + * + * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is + * just required to get to chip config. PCH_DEV_PMC is hidden by this + * point and hence removed from the root bus. pcidev_path_on_root thus + * returns NULL for PCH_DEV_PMC device. */ - dev = PCH_DEV_PMC; + dev = SA_DEV_ROOT; config = dev->chip_info; pmcbase = pmc_mmio_regs(); if (config->PmTimerDisabled) { diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index 6834aa2d17..0b2356857d 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -153,7 +153,7 @@ static void pch_power_options(struct device *dev) static void pmc_init(void *unused) { - struct device *dev = PCH_DEV_PMC; + struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info; rtc_init(); From 9eac4c9ddac863344bbe6eab5323e95a266a21e4 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 6 Jul 2019 22:54:53 -0700 Subject: [PATCH 082/231] soc/intel/cannonlake, mb/google/sarien: Get rid of unused dev param MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change gets rid of unused dev param to pmc_set_afterg3. BUG=b:136861224 Change-Id: Ic197d6fb8618db15601096f5815e82efc2b539c1 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/34117 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Subrata Banik --- src/mainboard/google/sarien/chromeos.c | 2 +- src/soc/intel/cannonlake/include/soc/pmc.h | 3 +-- src/soc/intel/cannonlake/pmc.c | 10 +++++----- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index fafc469270..7aaf4015b5 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -122,6 +122,6 @@ void mainboard_prepare_cr50_reset(void) { #if ENV_RAMSTAGE /* Ensure system powers up after CR50 reset */ - pmc_set_afterg3(PCH_DEV_PMC, MAINBOARD_POWER_STATE_ON); + pmc_set_afterg3(MAINBOARD_POWER_STATE_ON); #endif } diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index e0d2614e8e..252c719925 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -171,7 +171,6 @@ #define SCIS_IRQ22 6 #define SCIS_IRQ23 7 -struct device; -void pmc_set_afterg3(struct device *dev, int s5pwr); +void pmc_set_afterg3(int s5pwr); #endif diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index 0b2356857d..8eb81b0b40 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -32,7 +32,7 @@ * Set which power state system will be after reapplying * the power (from G3 State) */ -void pmc_set_afterg3(struct device *dev, int s5pwr) +void pmc_set_afterg3(int s5pwr) { uint8_t reg8; uint8_t *pmcbase = pmc_mmio_regs(); @@ -60,7 +60,7 @@ void pmc_set_afterg3(struct device *dev, int s5pwr) */ void pmc_soc_restore_power_failure(void) { - pmc_set_afterg3(PCH_DEV_PMC, CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pmc_set_afterg3(CONFIG_MAINBOARD_POWER_FAILURE_STATE); } static void pm1_enable_pwrbtn_smi(void *unused) @@ -119,7 +119,7 @@ static void config_deep_sx(uint32_t deepsx_config) write32(pmcbase + DSX_CFG, reg); } -static void pch_power_options(struct device *dev) +static void pch_power_options(void) { const char *state; @@ -144,7 +144,7 @@ static void pch_power_options(struct device *dev) default: state = "undefined"; } - pmc_set_afterg3(dev, pwr_on); + pmc_set_afterg3(pwr_on); printk(BIOS_INFO, "Set power %s after power failure.\n", state); /* Set up GPE configuration. */ @@ -159,7 +159,7 @@ static void pmc_init(void *unused) rtc_init(); /* Initialize power management */ - pch_power_options(dev); + pch_power_options(); config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); From 0478037e1106240928fa5889ee0e620b859d3cfc Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 6 Jul 2019 22:58:31 -0700 Subject: [PATCH 083/231] soc/intel/icelake: Use SA_DEV_ROOT instead of PCH_DEV_PMC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PMC device gets hidden from PCI bus after FSP-S call. Thus, it gets removed from the root bus as leftover unused device. With change 903b40a8a46 ("soc/intel: Replace uses of dev_find_slot()"), all uses of dev_find_slot() were replaced by pcidev_path_on_root() which relies on scanning of root bus to find the requested device. Since PMC device is removed from the root bus, pcidev_path_on_root() returns NULL for it thus resulting in configuration being skipped for the PMC ultimately resulting in S3 failures. Since the PCH_DEV_PMC was just used to get to chip config, this change replaces the use of PCH_DEV_PMC with SA_DEV_ROOT. BUG=b:136861224 Change-Id: Id68db8382b7b98e8e2e4a65ded1a6fb3bd057051 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/34118 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Subrata Banik --- src/soc/intel/icelake/finalize.c | 7 ++++++- src/soc/intel/icelake/pmc.c | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index e061cda2f0..b838c199e7 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -69,8 +69,13 @@ static void pch_finalize(void) * * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. * Disabling ACPI PM timer also switches off TCO + * + * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is + * just required to get to chip config. PCH_DEV_PMC is hidden by this + * point and hence removed from the root bus. pcidev_path_on_root thus + * returns NULL for PCH_DEV_PMC device. */ - dev = PCH_DEV_PMC; + dev = SA_DEV_ROOT; config = dev->chip_info; pmcbase = pmc_mmio_regs(); if (config->PmTimerDisabled) { diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 8f61d70955..25913a8904 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -136,7 +136,7 @@ static void pch_power_options(struct device *dev) static void pmc_init(void *unused) { - struct device *dev = PCH_DEV_PMC; + struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info; rtc_init(); From 451ef598e6d4caff5cb8d9d798bfbb2b6874f627 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 6 Jul 2019 23:01:15 -0700 Subject: [PATCH 084/231] soc/intel/icelake: Get rid of unused dev param MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change gets rid of unused dev param to pmc_set_afterg3. BUG=b:136861224 Change-Id: I861bb132acf113c9d306175b670bf4a1ff742c28 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/34119 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Subrata Banik --- src/soc/intel/icelake/pmc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 25913a8904..053d7e8e46 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -30,7 +30,7 @@ * Set which power state system will be after reapplying * the power (from G3 State) */ -static void pmc_set_afterg3(struct device *dev, int s5pwr) +static void pmc_set_afterg3(int s5pwr) { uint8_t reg8; uint8_t *pmcbase = pmc_mmio_regs(); @@ -58,7 +58,7 @@ static void pmc_set_afterg3(struct device *dev, int s5pwr) */ void pmc_soc_restore_power_failure(void) { - pmc_set_afterg3(PCH_DEV_PMC, CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pmc_set_afterg3(CONFIG_MAINBOARD_POWER_FAILURE_STATE); } static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) @@ -102,7 +102,7 @@ static void config_deep_sx(uint32_t deepsx_config) write32(pmcbase + DSX_CFG, reg); } -static void pch_power_options(struct device *dev) +static void pch_power_options(void) { const char *state; @@ -127,7 +127,7 @@ static void pch_power_options(struct device *dev) default: state = "undefined"; } - pmc_set_afterg3(dev, pwr_on); + pmc_set_afterg3(pwr_on); printk(BIOS_INFO, "Set power %s after power failure.\n", state); /* Set up GPE configuration. */ @@ -142,7 +142,7 @@ static void pmc_init(void *unused) rtc_init(); /* Initialize power management */ - pch_power_options(dev); + pch_power_options(); pmc_set_acpi_mode(); From b29da7f79e7cfb16f5d8b23057bd91df760f79d3 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 6 Jul 2019 23:05:23 -0700 Subject: [PATCH 085/231] soc/intel/{cannonlake,icelake}: Do not define PCH_DEV_PMC in ramstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change intentionally removes the definition of PCH_DEV_PMC from ramstage to avoid silent errors. This device gets hidden from PCI bus in FSP-S and hence dropped from the root bus by the resource allocator. In order to avoid incorrect references to the device, avoid defining it in ramstage where it known to return NULL. BUG=b:136861224 Change-Id: I4f69470ec80c7127a2b604ed2b1f794f5a63e126 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/34120 Reviewed-by: Subrata Banik Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/include/soc/pci_devs.h | 12 ++++++++++++ src/soc/intel/icelake/include/soc/pci_devs.h | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 46bc1bfa20..1bc028f194 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -187,7 +187,19 @@ #define PCH_DEVFN_TRACEHUB _PCH_DEVFN(LPC, 7) #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_P2SB _PCH_DEV(LPC, 1) + +#if !ENV_RAMSTAGE +/* + * PCH_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets + * hidden from PCI bus after call to FSP-S. This leads to resource allocator + * dropping it from the root bus as unused device. All references to PCH_DEV_PMC + * would then return NULL and can go unnoticed if not handled properly. Since, + * this device does not have any special chip config associated with it, it is + * okay to not provide the definition for it in ramstage. + */ #define PCH_DEV_PMC _PCH_DEV(LPC, 2) +#endif + #define PCH_DEV_HDA _PCH_DEV(LPC, 3) #define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h index b24211311a..1348f23b78 100644 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ b/src/soc/intel/icelake/include/soc/pci_devs.h @@ -184,7 +184,19 @@ #define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) #define PCH_DEV_LPC PCH_DEV_ESPI #define PCH_DEV_P2SB _PCH_DEV(ESPI, 1) + +#if !ENV_RAMSTAGE +/* + * PCH_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets + * hidden from PCI bus after call to FSP-S. This leads to resource allocator + * dropping it from the root bus as unused device. All references to PCH_DEV_PMC + * would then return NULL and can go unnoticed if not handled properly. Since, + * this device does not have any special chip config associated with it, it is + * okay to not provide the definition for it in ramstage. + */ #define PCH_DEV_PMC _PCH_DEV(ESPI, 2) +#endif + #define PCH_DEV_HDA _PCH_DEV(ESPI, 3) #define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) #define PCH_DEV_SPI _PCH_DEV(ESPI, 5) From 142b10ee1fa1c68f0c147665ff55b43eb8f0317d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 1 Jul 2019 08:54:56 +0300 Subject: [PATCH 086/231] cpu/x86: Fix MSR_PLATFORM_INFO definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While common to many Intel CPUs, this is not an architectural MSR that should be globally defined for all x86. Change-Id: Ibeed022dc2ba2e90f71511f9bd2640a7cafa5292 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34090 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: David Guckian --- src/include/cpu/x86/tsc.h | 2 -- src/northbridge/intel/fsp_rangeley/udelay.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 8dd9b7519c..dd333e8930 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -11,8 +11,6 @@ #define TSC_SYNC #endif -#define MSR_PLATFORM_INFO 0xce - struct tsc_struct { unsigned int lo; unsigned int hi; diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c index 01989abb37..08301a37f6 100644 --- a/src/northbridge/intel/fsp_rangeley/udelay.c +++ b/src/northbridge/intel/fsp_rangeley/udelay.c @@ -18,6 +18,8 @@ #include #include +#define MSR_PLATFORM_INFO 0xce + /** * Intel Rangeley CPUs always run the TSC at BCLK = 100MHz */ From 87fe4181727f97fa95b9f853981e06c156ee48b8 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Sat, 29 Jun 2019 16:18:41 +0300 Subject: [PATCH 087/231] mb/lenovo/g505s: Disable SeaBIOS options unsupported by hardware G505S doesn't have any SAS or NVMe controllers and couldn't have a TPM, so it makes sense to disable the related SeaBIOS options for this board. This reduces the size of compiled SeaBIOS by 129344-110048=19296 bytes. Signed-off-by: Mike Banon Change-Id: Ib0183b7786ecd77bb0df923bc84908275f2fe14c Reviewed-on: https://review.coreboot.org/c/coreboot/+/33870 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/g505s/Kconfig | 4 ++++ src/mainboard/lenovo/g505s/config_seabios | 7 +++++++ 2 files changed, 11 insertions(+) create mode 100644 src/mainboard/lenovo/g505s/config_seabios diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 883ef27286..b80019ecf4 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -55,4 +55,8 @@ config VGA_BIOS_ID string default "1002,990b" +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS + endif # BOARD_LENOVO_G505S diff --git a/src/mainboard/lenovo/g505s/config_seabios b/src/mainboard/lenovo/g505s/config_seabios new file mode 100644 index 0000000000..1959fa35c2 --- /dev/null +++ b/src/mainboard/lenovo/g505s/config_seabios @@ -0,0 +1,7 @@ +### +### SeaBIOS custom configuration for Lenovo G505S +### +# CONFIG_MEGASAS is not set +# CONFIG_NVME is not set +# CONFIG_TCGBIOS is not set +# From ebdafdb1a72f804675da3119c51c3363e3b830d5 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 5 Jul 2019 18:15:45 +0530 Subject: [PATCH 088/231] soc/intel/icelake: Remove redundant gpio.c from Makefile.inc Change-Id: Ibddc2363e9bfea9ae41e4807435acb2e788dcb93 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/34088 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Angel Pons --- src/soc/intel/icelake/Makefile.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 0d4e32d131..cd029343bf 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -42,7 +42,6 @@ ramstage-y += fsp_params.c ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += gspi.c -ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += lockdown.c ramstage-y += memmap.c From 21f1ccce9cc63ef27f677d851450e943f86874fb Mon Sep 17 00:00:00 2001 From: David Wu Date: Wed, 19 Jun 2019 20:09:17 +0800 Subject: [PATCH 089/231] mb/google/hatch/variants/kindred: Enable eMMC support Enable eMMC support for kindred. Cq-Depend: chromium:1666982 BUG=b:135464155 BRANCH=none TEST=Boot kindred onboard eMMC. Change-Id: I040af6da30313f8dd59e3ef910b290922e090cdc Signed-off-by: David Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/33618 Reviewed-by: Paul Menzel Reviewed-by: Paul Fagerburg Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../google/hatch/variants/kindred/gpio.c | 24 +++++++++++++++++++ .../hatch/variants/kindred/overridetree.cb | 4 ++++ 2 files changed, 28 insertions(+) diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index 43948a35f8..f6aeb690c5 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -23,6 +23,30 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RESET# ==> EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index 562bb8b229..cc068bb696 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -47,6 +47,9 @@ chip soc/intel/cannonlake # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + device domain 0 on device pci 15.0 on chip drivers/i2c/generic @@ -143,6 +146,7 @@ chip soc/intel/cannonlake device i2c 1a on end end end #I2C #4 + device pci 1a.0 on end # eMMC device pci 1e.3 on chip drivers/spi/acpi register "name" = ""CRFP"" From 5526e68f152ed7ecbaabfb1b2fa86bfea1f47f01 Mon Sep 17 00:00:00 2001 From: David Wu Date: Fri, 21 Jun 2019 15:33:52 +0800 Subject: [PATCH 090/231] mb/google/hatch/var/kindred: Update ELAN GPIO/IRQ and add Synaptics Touchpad Update ELAN GPIO and IRQ setting and add Synaptics Touchpad BUG=b:132708463 BRANCH=None TEST=Verify ELAN/Synaptics touchpad is working fine. Change-Id: I883ce2e50ca5c6bd2b1ca76cbe24177055cc5d60 Signed-off-by: David Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/33660 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../google/hatch/variants/kindred/overridetree.cb | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index cc068bb696..5c812cbcac 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -55,10 +55,20 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" + register "probed" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)" + register "generic.wake" = "GPE0_DW0_21" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end end # I2C #0 device pci 15.1 on chip drivers/i2c/generic From 3a2660e489d44d29b647e8594e8134e6ee8fc03b Mon Sep 17 00:00:00 2001 From: David Wu Date: Fri, 28 Jun 2019 09:23:48 +0800 Subject: [PATCH 091/231] mb/google/hatch/var/kindred: Add Raydium touchscreen support Add Raydium controller BUG=b:135728282 BRANCH=master TEST= 1. FW_NAME="kindred" emerge-hatch coreboot chromeos-bootimage 2. boot up on kindred DUT to check touchscreen device by evtest /dev/input/event3: Raydium Touchscreen 3. Raydium TS is working Change-Id: Id963300ab0dadcb78786c5a1328c2a4098a48a05 Signed-off-by: David Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/33857 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../google/hatch/variants/kindred/overridetree.cb | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index 5c812cbcac..89937068d5 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -84,6 +84,17 @@ chip soc/intel/cannonlake register "stop_off_delay_ms" = "5" device i2c 49 on end end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "1" + register "reset_off_delay_ms" = "2" + register "has_power_resource" = "1" + device i2c 39 on end + end chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" From b72b5d95286a2290554399e0803d4ba5e7b87f8d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 4 Jul 2019 21:08:17 +0300 Subject: [PATCH 092/231] arch/x86: Clean up PIRQ_ROUTE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This code is currently only used by via/epia-m850, it is also somewhat buggy. Change-Id: I140e15d584d3f60f7824bcb71ce63724c11e3f46 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34078 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/Kconfig | 15 --------------- src/arch/x86/Kconfig | 16 ++++++++++++++++ src/arch/x86/pirq_routing.c | 12 +++++------- 3 files changed, 21 insertions(+), 22 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 919d257c62..778f1694b6 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -543,10 +543,6 @@ config HAVE_OPTION_TABLE file containing NVRAM/CMOS bit definitions. It defaults to 'n' but can be selected in mainboard/*/Kconfig. -config PIRQ_ROUTE - bool - default n - config HAVE_SMI_HANDLER bool default n @@ -591,17 +587,6 @@ config HAVE_PIRQ_TABLE Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE. -config MAX_PIRQ_LINKS - int - default 4 - help - This variable specifies the number of PIRQ interrupt links which are - routable. On most chipsets, this is 4, INTA through INTD. Some - chipsets offer more than four links, commonly up to INTH. They may - also have a separate link for ATA or IOAPIC interrupts. When the PIRQ - table specifies links greater than 4, pirq_route_irqs will not - function properly, unless this variable is correctly set. - config COMMON_FADT bool default n diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 06aadedae6..631d981e45 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -329,3 +329,19 @@ config HAVE_CF9_RESET config HAVE_CF9_RESET_PREPARE bool depends on HAVE_CF9_RESET + +config PIRQ_ROUTE + bool + default n + +config MAX_PIRQ_LINKS + int + default 4 + depends on PIRQ_ROUTE + help + This variable specifies the number of PIRQ interrupt links which are + routable. On most chipsets, this is 4, INTA through INTD. Some + chipsets offer more than four links, commonly up to INTH. They may + also have a separate link for ATA or IOAPIC interrupts. When the PIRQ + table specifies links greater than 4, pirq_route_irqs will not + function properly, unless this variable is correctly set. diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 15d7411b3f..5f80c9d56c 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -20,10 +20,6 @@ #include #include -void __weak pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]) -{ -} - static void check_pirq_routing_table(struct irq_routing_table *rt) { uint8_t *addr = (uint8_t *)rt; @@ -146,8 +142,11 @@ static void pirq_route_irqs(unsigned long addr) /* Set PCI IRQs. */ for (i = 0; i < num_entries; i++) { + u8 bus = pirq_tbl->slots[i].bus; + u8 devfn = pirq_tbl->slots[i].devfn; + printk(BIOS_DEBUG, "PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i, - pirq_tbl->slots[i].devfn >> 3, pirq_tbl->slots[i].slot); + devfn >> 3, pirq_tbl->slots[i].slot); for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) { @@ -178,8 +177,7 @@ static void pirq_route_irqs(unsigned long addr) } /* Bus, device, slots IRQs for {A,B,C,D}. */ - pci_assign_irqs(pirq_tbl->slots[i].bus, - pirq_tbl->slots[i].devfn >> 3, irq_slot); + pci_assign_irqs(bus, devfn >> 3, irq_slot); } for (i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) From fffc9f3b9d9de4909d35da0fb4006d5080bb8e27 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 3 Jul 2019 09:55:01 +0300 Subject: [PATCH 093/231] device/pci: Declare pci_root_bus() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is used a lot, cache the result so search of domain from devicetree is only done once. Improvement only applies when MAYBE_STATIC evaluates to static. Change-Id: If675abb632fe68acd59ba0bdfef854da3e0839a9 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34004 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/device/device_const.c | 22 ++++++++++++++++------ src/include/device/device.h | 1 + 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/src/device/device_const.c b/src/device/device_const.c index 6ce1d18c93..1853b4c4d2 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -183,10 +183,24 @@ DEVTREE_CONST struct device *pcidev_path_behind( return find_dev_path(parent, &path); } -DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn) +DEVTREE_CONST struct bus *pci_root_bus(void) { DEVTREE_CONST struct device *pci_domain; + MAYBE_STATIC DEVTREE_CONST struct bus *pci_root = NULL; + if (pci_root) + return pci_root; + + pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN); + if (!pci_domain) + return NULL; + + pci_root = pci_domain->link_list; + return pci_root; +} + +DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn) +{ /* Work around pcidev_path_behind() below failing * due tue complicated devicetree with topology * being manipulated on-the-fly. @@ -194,11 +208,7 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn) if (CONFIG(NORTHBRIDGE_AMD_AMDFAM10)) return dev_find_slot(0, devfn); - pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN); - if (!pci_domain) - return NULL; - - return pcidev_path_behind(pci_domain->link_list, devfn); + return pcidev_path_behind(pci_root_bus(), devfn); } DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn) diff --git a/src/include/device/device.h b/src/include/device/device.h index 8e9454c4e1..a200de0876 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -289,6 +289,7 @@ DEVTREE_CONST struct device *pcidev_path_behind(const struct bus *parent, pci_devfn_t devfn); DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn); DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn); +DEVTREE_CONST struct bus *pci_root_bus(void); void scan_smbus(struct device *bus); void scan_generic_bus(struct device *bus); From 598af2e2c2785c00eb4290cdcefe1082b2a6f858 Mon Sep 17 00:00:00 2001 From: "Sukerkar, Amol N" Date: Tue, 25 Jun 2019 14:59:00 -0700 Subject: [PATCH 094/231] src/security/vboot: Add option to skip display init with vboot 2.0 This config option, when set, will allow the platform to skip display initialization in normal (non-developer, non-recovery) mode. This allows platforms that do not implement firmware UI in normal mode to skip the display init in firmware. TEST=Set option CONFIG_VBOOT and clear CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT and the display should initialize in ramstage when platform boots. Set CONFIG_VBOOT and set CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT and the display initialization should be skipped in coreboot. Signed-off-by: Sukerkar, Amol N Change-Id: Icadad6da34dcb817af02868e89a94ea62dbfa7b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33844 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/lib/bootmode.c | 4 ++-- src/security/vboot/Kconfig | 11 +++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 737dcf93d0..51bbbe5dc0 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2019 Intel Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,8 +34,7 @@ void gfx_set_init_done(int done) int display_init_required(void) { - /* For vboot, always honor VBOOT_WD_FLAG_DISPLAY_INIT. */ - if (CONFIG(VBOOT)) { + if (CONFIG(VBOOT_MAY_SKIP_DISPLAY_INIT)) { /* Must always select MUST_REQUEST_DISPLAY when using this function. */ if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index ea1f73889a..fa9893520a 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -154,10 +154,21 @@ config VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT reboots caused after vboot verification is run. e.g. reboots caused by FSP components on Intel platforms. +config VBOOT_MAY_SKIP_DISPLAY_INIT + bool "Skip display initialization in normal mode" + default y if CHROMEOS + default n + help + Set this option to indicate that coreboot should skip display + initialization on a normal (non-recovery, non-developer) boot. + This is useful for platforms that do not support firmware + user-interface in normal mode. + config VBOOT_MUST_REQUEST_DISPLAY bool default y if VGA_ROM_RUN default n + depends on VBOOT_MAY_SKIP_DISPLAY_INIT help Set this option to indicate to vboot that this platform will skip its display initialization on a normal (non-recovery, non-developer) boot. From 37bec0b3971efa18f6fcc405edfb4272d215752d Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Fri, 28 Jun 2019 10:10:37 -0600 Subject: [PATCH 095/231] payloads/coreinfo: Use fixed-width integers for cpuid This function executes the cpuid instruction, which takes a 32 bit input value (idx), and then stores output in eax, ebx, ecx, and edx, which are all 32 bit registers. Update the prototype to use fixed-width integers, and update all usage calls appropriately. Change-Id: I15876fa35628d3a505864fb49be4fdab1fd19f4a Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33862 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- payloads/coreinfo/coreinfo.h | 3 +-- payloads/coreinfo/cpuinfo_module.c | 12 ++++++------ 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/payloads/coreinfo/coreinfo.h b/payloads/coreinfo/coreinfo.h index 073c5f9a87..03e59c9bb1 100644 --- a/payloads/coreinfo/coreinfo.h +++ b/payloads/coreinfo/coreinfo.h @@ -27,8 +27,7 @@ struct coreinfo_module { int (*handle) (int); }; -extern void docpuid(int, unsigned long *, unsigned long *, unsigned long *, - unsigned long *); +extern void docpuid(uint32_t idx, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); void print_module_title(WINDOW *win, const char *title); diff --git a/payloads/coreinfo/cpuinfo_module.c b/payloads/coreinfo/cpuinfo_module.c index 0ea2dfce46..94379f3077 100644 --- a/payloads/coreinfo/cpuinfo_module.c +++ b/payloads/coreinfo/cpuinfo_module.c @@ -85,7 +85,7 @@ static const char *amd_cap_extended_ecx_flags[] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; -static unsigned long vendor; +static uint32_t vendor; static unsigned int cpu_khz; static void decode_flags(WINDOW *win, unsigned long reg, const char **flags, @@ -114,7 +114,7 @@ static void decode_flags(WINDOW *win, unsigned long reg, const char **flags, static void get_features(WINDOW *win, int *row) { - unsigned long eax, ebx, ecx, edx; + uint32_t eax, ebx, ecx, edx; int lrow = *row; wmove(win, lrow++, 1); @@ -150,12 +150,12 @@ static void get_features(WINDOW *win, int *row) static void do_name(WINDOW *win, int row) { char name[49], *p; - unsigned long eax, ebx, ecx, edx; - int i, t; + uint32_t eax, ebx, ecx, edx; + int t; p = name; - for (i = 0x80000002; i <= 0x80000004; i++) { + for (uint32_t i = 0x80000002; i <= 0x80000004; i++) { docpuid(i, &eax, &ebx, &ecx, &edx); if (eax == 0) @@ -176,7 +176,7 @@ static void do_name(WINDOW *win, int row) static int cpuinfo_module_redraw(WINDOW *win) { - unsigned long eax, ebx, ecx, edx; + uint32_t eax, ebx, ecx, edx; unsigned int brand; char *vstr; int row = 2; From a711e9c44dfc0c50dd1a05a8cf34d393093300b4 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Fri, 28 Jun 2019 10:58:56 -0600 Subject: [PATCH 096/231] payloads/coreinfo: Use correct integer types for loop indices Make sure that the type of the loop index matches the type of the upper bound. This fixes several -Wsign-compare warnings. Change-Id: I73a88355d86288609e03f7a6fcaec14dfedac203 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33863 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- payloads/coreinfo/coreboot_module.c | 2 +- payloads/coreinfo/coreinfo.c | 20 +++++++++----------- payloads/coreinfo/pci_module.c | 2 +- payloads/coreinfo/timestamps_module.c | 6 ++---- 4 files changed, 13 insertions(+), 17 deletions(-) diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index d294288cf7..66c258249c 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -195,7 +195,7 @@ static int parse_header(void *addr, int len) /* Now, walk the tables. */ ptr += header->header_bytes; - for (i = 0; i < header->table_entries; i++) { + for (u32 j = 0; j < header->table_entries; j++) { struct cb_record *rec = (struct cb_record *)ptr; switch (rec->tag) { diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 649bfde837..b731abfbf5 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -132,7 +132,7 @@ static void print_time_and_date(void) static void print_menu(void) { - int i, j; + int j; char menu[80]; char *ptr = menu; @@ -140,11 +140,11 @@ static void print_menu(void) for (j = 0; j < SCREEN_X; j++) waddch(menuwin, ' '); - for (i = 0; i < ARRAY_SIZE(categories); i++) { + for (size_t i = 0; i < ARRAY_SIZE(categories); i++) { if (categories[i].count == 0) continue; - ptr += sprintf(ptr, "F%d: %s ", i + 1, categories[i].name); + ptr += sprintf(ptr, "F%zu: %s ", i + 1, categories[i].name); } mvwprintw(menuwin, 1, 0, menu); @@ -215,9 +215,9 @@ static void handle_category_key(struct coreinfo_cat *cat, int key) static void print_no_modules_selected(void) { - int height = getmaxy(stdscr), i; + int height = getmaxy(stdscr); - for (i = 0; i < ARRAY_SIZE(categories); i++) + for (size_t i = 0; i < ARRAY_SIZE(categories); i++) if (categories[i].count > 0) return; @@ -227,9 +227,7 @@ static void print_no_modules_selected(void) static int first_nonempty_category(void) { - int i; - - for (i = 0; i < ARRAY_SIZE(categories); i++) + for (size_t i = 0; i < ARRAY_SIZE(categories); i++) if (categories[i].count > 0) return i; return 0; @@ -268,7 +266,7 @@ static void loop(void) if (key >= '1' && key <= '9') ch = key - '1'; - if (ch >= 0 && ch <= ARRAY_SIZE(categories)) { + if (ch >= 0 && (unsigned int)ch <= ARRAY_SIZE(categories)) { if (ch == ARRAY_SIZE(categories)) continue; if (categories[ch].count == 0) @@ -289,7 +287,7 @@ static void loop(void) int main(void) { - int i, j; + int j; if (CONFIG(LP_USB)) usb_initialize(); @@ -310,7 +308,7 @@ int main(void) werase(modwin); - for (i = 0; i < ARRAY_SIZE(categories); i++) { + for (size_t i = 0; i < ARRAY_SIZE(categories); i++) { for (j = 0; j < categories[i].count; j++) categories[i].modules[j]->init(); } diff --git a/payloads/coreinfo/pci_module.c b/payloads/coreinfo/pci_module.c index 3060161fe0..cb53ed69f7 100644 --- a/payloads/coreinfo/pci_module.c +++ b/payloads/coreinfo/pci_module.c @@ -51,7 +51,7 @@ static void swap(struct pci_devices *a, struct pci_devices *b) static int partition(struct pci_devices *list, int len) { - int val = list[len / 2].device; + pcidev_t val = list[len / 2].device; int index = 0; int i; diff --git a/payloads/coreinfo/timestamps_module.c b/payloads/coreinfo/timestamps_module.c index fe2d2b5c6b..5468844f89 100644 --- a/payloads/coreinfo/timestamps_module.c +++ b/payloads/coreinfo/timestamps_module.c @@ -29,9 +29,7 @@ static unsigned long tick_freq_mhz; static const char *timestamp_name(uint32_t id) { - int i; - - for (i = 0; i < ARRAY_SIZE(timestamp_ids); i++) { + for (size_t i = 0; i < ARRAY_SIZE(timestamp_ids); i++) { if (timestamp_ids[i].id == id) return timestamp_ids[i].name; } @@ -184,7 +182,7 @@ static int timestamps_module_init(void) prev_stamp = base_time; total_time = 0; - for (int i = 0; i < n_entries; i++) { + for (u32 i = 0; i < n_entries; i++) { uint64_t stamp; const struct timestamp_entry *tse = ×tamps->entries[i]; From 729d5971d23bf63873908760c39b7da36a7646fa Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Fri, 28 Jun 2019 11:01:04 -0600 Subject: [PATCH 097/231] payloads/coreinfo: Enable -Wextra This enables extra useful warnings. Change-Id: I3d54988935c7df9ac0dc2f7aceb56fb720c9c4d1 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33864 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- payloads/coreinfo/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 50659d3c0b..a98342fc2e 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -83,7 +83,7 @@ OBJCOPY := $(OBJCOPY_$(ARCH-y)) LPCC := CC="$(CC)" $(LIBPAYLOAD_OBJ)/bin/lpgcc LPAS := AS="$(AS)" $(LIBPAYLOAD_OBJ)/bin/lpas -CFLAGS += -Wall -Werror -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES) +CFLAGS += -Wall -Wextra -Werror -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES) ifneq ($(strip $(HAVE_DOTCONFIG)),) include $(src)/.config From 609305fa764470b114237cfcfb0d2a795c5e6abb Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Fri, 28 Jun 2019 11:03:31 -0600 Subject: [PATCH 098/231] payloads/coreinfo: Make internal functions static These functions are only used in the files they are defined in, so they can be made static. Change-Id: Ic7f78912803cbdd1cb3a75f7f69f526739dab6e7 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33865 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- payloads/coreinfo/coreboot_module.c | 2 +- payloads/coreinfo/multiboot_module.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index 66c258249c..e56ce68ed6 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -37,7 +37,7 @@ static struct { static int tables_good = 0; -int coreboot_module_redraw(WINDOW *win) +static int coreboot_module_redraw(WINDOW *win) { int row = 2; int i; diff --git a/payloads/coreinfo/multiboot_module.c b/payloads/coreinfo/multiboot_module.c index e394dbd732..865561d973 100644 --- a/payloads/coreinfo/multiboot_module.c +++ b/payloads/coreinfo/multiboot_module.c @@ -32,7 +32,7 @@ static struct { static int tables_good = 0; -int multiboot_module_redraw(WINDOW *win) +static int multiboot_module_redraw(WINDOW *win) { int row = 2; int i; From e2e8ccefd7aa74add617f67b62977c946c20d759 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Sat, 29 Jun 2019 11:04:42 -0600 Subject: [PATCH 099/231] payloads/coreinfo: Enable -Wmissing-prototypes Change-Id: I7ee9436ba71ceea35a35272291ea245c0b7c37c5 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33866 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- payloads/coreinfo/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index a98342fc2e..1e9eb80d20 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -83,7 +83,8 @@ OBJCOPY := $(OBJCOPY_$(ARCH-y)) LPCC := CC="$(CC)" $(LIBPAYLOAD_OBJ)/bin/lpgcc LPAS := AS="$(AS)" $(LIBPAYLOAD_OBJ)/bin/lpas -CFLAGS += -Wall -Wextra -Werror -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES) +CFLAGS += -Wall -Wextra -Wmissing-prototypes -Werror +CFLAGS += -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES) ifneq ($(strip $(HAVE_DOTCONFIG)),) include $(src)/.config From 6faccd1f00a3606b720fc3a233c2de5cd97bb176 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 1 Jul 2019 11:21:55 -0600 Subject: [PATCH 100/231] util/inteltool: Make internal functions static None of these functions are used outside of the files they are defined in, so they can all be static. Change-Id: Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33945 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- util/inteltool/cpu.c | 12 ++++++------ util/inteltool/inteltool.c | 4 ++-- util/inteltool/spi.c | 4 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index ef2df3cd00..ff69b8cf69 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -78,7 +78,7 @@ inline cpuid_result_t cpuid_ext(int op, unsigned int ecx) #ifndef __DARWIN__ int msr_readerror = 0; -msr_t rdmsr(int addr) +static msr_t rdmsr(int addr) { uint32_t buf[2]; msr_t msr = { 0xffffffff, 0xffffffff }; @@ -132,7 +132,7 @@ static int open_and_seek(int cpu, unsigned long msr, int mode, int *fd) return 0; } -msr_t rdmsr_from_cpu(int cpu, unsigned long addr) +static msr_t rdmsr_from_cpu(int cpu, unsigned long addr) { int fd; msr_t msr = { 0xffffffff, 0xffffffff }; @@ -155,12 +155,12 @@ msr_t rdmsr_from_cpu(int cpu, unsigned long addr) return msr; } -int get_number_of_cpus(void) +static int get_number_of_cpus(void) { return sysconf(_SC_NPROCESSORS_ONLN); } -int is_sgx_supported(int cpunum) +static int is_sgx_supported(int cpunum) { cpuid_result_t cpuid_regs; msr_t msr; @@ -172,14 +172,14 @@ int is_sgx_supported(int cpunum) return ((cpuid_regs.ebx & SGX_SUPPORTED) && (msr.lo & PRMRR_SUPPORTED)); } -int is_sgx_enabled(int cpunum) +static int is_sgx_enabled(int cpunum) { msr_t data; data = rdmsr_from_cpu(cpunum, IA32_FEATURE_CONTROL); return (data.lo & SGX_GLOBAL_ENABLED); } -int is_sgx_locked(int cpunum) +static int is_sgx_locked(int cpunum) { msr_t data; data = rdmsr_from_cpu(cpunum, IA32_FEATURE_CONTROL); diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 7e02510752..76b1abed9c 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -443,7 +443,7 @@ void unmap_physical(void *virt_addr, size_t len) } #endif -void print_version(void) +static void print_version(void) { printf("inteltool v%s -- ", INTELTOOL_VERSION); printf("Copyright (C) 2008 coresystems GmbH\n\n"); @@ -457,7 +457,7 @@ void print_version(void) "GNU General Public License for more details.\n\n"); } -void print_usage(const char *name) +static void print_usage(const char *name) { printf("usage: %s [-vh?gGrpmedPMaAsfSRx]\n", name); printf("\n" diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index da5533deaa..22ba3d42f2 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -79,7 +79,7 @@ static const io_register_t ich7_spi_bar_registers[] = { { 0x68, 4, "PBR2 Protected BIOS Range 2" }, }; -int print_bioscntl(struct pci_dev *sb) +static int print_bioscntl(struct pci_dev *sb) { int i, size = 0; unsigned char bios_cntl = 0xff; @@ -207,7 +207,7 @@ int print_bioscntl(struct pci_dev *sb) return 0; } -int print_spibar(struct pci_dev *sb) { +static int print_spibar(struct pci_dev *sb) { int i, size = 0, rcba_size = 0x4000; volatile uint8_t *rcba; uint32_t rcba_phys; From 57f2188d8610bb7fd57e30b562cdb672691f18da Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 1 Jul 2019 11:24:03 -0600 Subject: [PATCH 101/231] util/inteltool: Enable -Wmissing-prototypes Change-Id: I6bf041d089498780ea2b7c52402d7452d44d3f87 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33946 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- util/inteltool/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index d88063be75..0f74a7c257 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -22,7 +22,7 @@ top ?= $(abspath ../..) CC ?= gcc INSTALL ?= /usr/bin/env install PREFIX ?= /usr/local -CFLAGS ?= -O2 -g -Wall -W +CFLAGS ?= -O2 -g -Wall -W -Wmissing-prototypes LDFLAGS += -lpci -lz CPPFLAGS += -I$(top)/src/commonlib/include From 3c2305f162d24cf07fa6079bd20fd2839e5d672c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 2 Jul 2019 13:54:52 +0300 Subject: [PATCH 102/231] drivers/amd/agesa: Drop redundant stack allocation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The removed call was there to support case LATE_CBMEM_INIT=y, HAVE_ACPI_RESUME=y. Same stack space is already allocated with postcar_frame_init() call. Change-Id: I03a44bc3252f553b1769d362b2f442d3e6ab73f4 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/33956 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Mike Banon Reviewed-by: Angel Pons --- src/drivers/amd/agesa/oem_s3.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c index acd34b8edf..9514bcdf5e 100644 --- a/src/drivers/amd/agesa/oem_s3.c +++ b/src/drivers/amd/agesa/oem_s3.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -122,8 +121,6 @@ AGESA_STATUS OemS3Save(AMD_S3_PARAMS *dataBlock) u32 MTRRStorageSize = 0; uintptr_t pos, size; - romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, ROMSTAGE_STACK_CBMEM); - /* To be consumed in AmdInitResume. */ get_s3nv_data(S3DataTypeNonVolatile, &pos, &size); if (size && dataBlock->NvStorageSize) From f2ba2d9421744eb31e4001f448ad02593dd82883 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 2 Jul 2019 10:50:10 -0600 Subject: [PATCH 103/231] arch/x86: Use ssize_t to store length size_t is the wrong type to store the return value of acpi_device_path_fill(), since any negative error values will be converted to a very large unsigned integer and potentially cause buffer overflow. Change-Id: Ia8ed62ecfac8eaa18a61545bd203b3c7a7cd9ca5 Signed-off-by: Jacob Garber Found-by: Coverity CID 1402095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33962 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel --- src/arch/x86/acpi_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 57fbc89064..0fb8f3b000 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -148,7 +148,7 @@ const char *acpi_device_scope(struct device *dev) const char *acpi_device_path_join(struct device *dev, const char *name) { static char buf[DEVICE_PATH_MAX] = {}; - size_t len; + ssize_t len; if (!dev) return NULL; From 4177bedd65f0f19400acf8f21aedd2abf3c837bf Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 1 Jul 2019 12:05:00 -0600 Subject: [PATCH 104/231] util/nvramtool: Include missing header The prototype for is_ident() is in this header, so include it. Change-Id: I45e0d58d1b891b18b3eb7741897ab691188a2bd9 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33947 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- util/nvramtool/accessors/layout-common.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/nvramtool/accessors/layout-common.c b/util/nvramtool/accessors/layout-common.c index 7dcfd3ebed..33522f4088 100644 --- a/util/nvramtool/accessors/layout-common.c +++ b/util/nvramtool/accessors/layout-common.c @@ -26,6 +26,8 @@ #include +#include "layout-text.h" + static int is_ident_nondigit(int c) { int result; From f2a2137ae2125c6b2e67c8d73d85fa5dd9ee7c4b Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 1 Jul 2019 12:10:28 -0600 Subject: [PATCH 105/231] util/nvramtool: Make internal function static This function is only used in this file, so it can be made static. Change-Id: I90e673da91eb926424d1730c268860da7fa1627b Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33948 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- util/nvramtool/accessors/layout-bin.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/nvramtool/accessors/layout-bin.c b/util/nvramtool/accessors/layout-bin.c index 8cf29d8fa7..baada2706a 100644 --- a/util/nvramtool/accessors/layout-bin.c +++ b/util/nvramtool/accessors/layout-bin.c @@ -89,7 +89,7 @@ void get_layout_from_cbfs_file(void) process_layout(); } -int write_cmos_layout_bin(FILE *f) +static int write_cmos_layout_bin(FILE *f) { const cmos_entry_t *cmos_entry; const cmos_enum_t *cmos_enum; From b592917dcf395183fbf8070c74e8344880f9b450 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 1 Jul 2019 12:12:24 -0600 Subject: [PATCH 106/231] util/nvramtool: Enable -Wmissing-prototypes Change-Id: Id751250b07a495dc25293ff703602bfefa9011bd Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33949 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- util/nvramtool/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/nvramtool/Makefile b/util/nvramtool/Makefile index f5a4fd5d70..46297a2de9 100644 --- a/util/nvramtool/Makefile +++ b/util/nvramtool/Makefile @@ -19,7 +19,7 @@ PROGRAM = nvramtool CC = gcc INSTALL = /usr/bin/env install PREFIX = /usr/local -CFLAGS = -O2 -g -Wall -W -I. -DCMOS_HAL=1 +CFLAGS = -O2 -g -Wall -W -Wmissing-prototypes -I. -DCMOS_HAL=1 #CFLAGS = -Os -Wall CLI_OBJS = cli/nvramtool.o cli/opts.o From 96e0ce30dbcdf709c92ef40ca9cfee0895b712ac Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 1 Jul 2019 12:13:48 -0600 Subject: [PATCH 107/231] util/nvramtool: Mark out_of_memory() as noreturn This silences several false positives from scan-build. Change-Id: I327a967c75d6aeec0b3aba16ee696dbae8cf997d Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33950 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Martin Roth --- util/nvramtool/common.c | 2 +- util/nvramtool/common.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/util/nvramtool/common.c b/util/nvramtool/common.c index 8ae6ea86f7..9b0a6b95ba 100644 --- a/util/nvramtool/common.c +++ b/util/nvramtool/common.c @@ -56,7 +56,7 @@ int get_line_from_file(FILE * f, char line[], int line_buf_size) * * We ran out of memory. Print an error message and die. ****************************************************************************/ -void out_of_memory(void) +_Noreturn void out_of_memory(void) { fprintf(stderr, "%s: Out of memory.\n", prog_name); exit(1); diff --git a/util/nvramtool/common.h b/util/nvramtool/common.h index 559e80f12b..19ce5666a7 100644 --- a/util/nvramtool/common.h +++ b/util/nvramtool/common.h @@ -76,7 +76,7 @@ extern const char prog_name[]; extern const char prog_version[]; int get_line_from_file(FILE * f, char line[], int line_buf_size); -void out_of_memory(void); +_Noreturn void out_of_memory(void); void usage(FILE * outfile); #endif /* COMMON_H */ From 2d58bf6a037c8ad474db4a902e799bee637e7ec0 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 2 Jul 2019 14:38:38 -0600 Subject: [PATCH 108/231] util/cbfstool: Prevent overflow of 16 bit multiplications Considering the following integer multiplication: u64 = u16 * u16 What on earth, one might wonder, is the problem with this? Well, due to C's unfortunately abstruse integer semantics, both u16's are implicitly converted to int before the multiplication, which cannot hold all possible values of a u16 * u16. Even worse, after overflow the intermediate result will be a negative number, which during the conversion to a u64 will be sign-extended to a huge integer. Not good. The solution is to manually cast one of the u16 to a u32 or u64, which are large enough to not have any overflow and will prevent the implicit conversion. The type of the u64 is preferred, though a u32 is used instead of size_t, since that can change depending on the platform. Change-Id: I5391221d46d620d0e5bd629e2f9680be7a53342e Signed-off-by: Jacob Garber Found-by: Coverity CID 12297{03,04,05,06,07,08,09,10} Reviewed-on: https://review.coreboot.org/c/coreboot/+/33986 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Paul Menzel --- util/cbfstool/elfheaders.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/util/cbfstool/elfheaders.c b/util/cbfstool/elfheaders.c index 8da54d09e0..676a635b8a 100644 --- a/util/cbfstool/elfheaders.c +++ b/util/cbfstool/elfheaders.c @@ -262,7 +262,8 @@ phdr_read(const struct buffer *in, struct parsed_elf *pelf, * per the ELF spec, You'd be surprised how many ELF * readers miss this little detail. */ - buffer_splice(&b, in, ehdr->e_phoff, ehdr->e_phentsize * ehdr->e_phnum); + buffer_splice(&b, in, ehdr->e_phoff, + (uint32_t)ehdr->e_phentsize * ehdr->e_phnum); if (check_size(in, ehdr->e_phoff, buffer_size(&b), "program headers")) return -1; @@ -304,7 +305,8 @@ shdr_read(const struct buffer *in, struct parsed_elf *pelf, * per the ELF spec, You'd be surprised how many ELF * readers miss this little detail. */ - buffer_splice(&b, in, ehdr->e_shoff, ehdr->e_shentsize * ehdr->e_shnum); + buffer_splice(&b, in, ehdr->e_shoff, + (uint32_t)ehdr->e_shentsize * ehdr->e_shnum); if (check_size(in, ehdr->e_shoff, buffer_size(&b), "section headers")) return -1; @@ -1180,8 +1182,8 @@ int elf_writer_serialize(struct elf_writer *ew, struct buffer *out) ew->ehdr.e_shnum = ew->num_secs; metadata_size = 0; metadata_size += ew->ehdr.e_ehsize; - metadata_size += ew->ehdr.e_shnum * ew->ehdr.e_shentsize; - metadata_size += ew->ehdr.e_phnum * ew->ehdr.e_phentsize; + metadata_size += (Elf64_Xword)ew->ehdr.e_shnum * ew->ehdr.e_shentsize; + metadata_size += (Elf64_Xword)ew->ehdr.e_phnum * ew->ehdr.e_phentsize; shstroffset = metadata_size; /* Align up section header string size and metadata size to 4KiB */ metadata_size = ALIGN(metadata_size + shstrlen, 4096); @@ -1200,11 +1202,11 @@ int elf_writer_serialize(struct elf_writer *ew, struct buffer *out) */ ew->ehdr.e_shoff = ew->ehdr.e_ehsize; ew->ehdr.e_phoff = ew->ehdr.e_shoff + - ew->ehdr.e_shnum * ew->ehdr.e_shentsize; + (Elf64_Off)ew->ehdr.e_shnum * ew->ehdr.e_shentsize; buffer_splice(&metadata, out, 0, metadata_size); buffer_splice(&phdrs, out, ew->ehdr.e_phoff, - ew->ehdr.e_phnum * ew->ehdr.e_phentsize); + (uint32_t)ew->ehdr.e_phnum * ew->ehdr.e_phentsize); buffer_splice(&data, out, metadata_size, program_size); /* Set up the section header string table contents. */ strtab = &ew->shstrtab_sec->content; From 142258c2f6cbfd76caf749395e666de0b0595318 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 10 Feb 2019 16:29:06 +0100 Subject: [PATCH 109/231] arch/mips: Make MIPS specific options depend on ARCH_MIPS Also don't define the default as this result in spurious lines in the .config. TEST: The generated config.h remain exactly the same for all boards. Change-Id: I7f35a5a9dcbc7b25b7806056e2b8e822fa94e428 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/31312 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Martin Roth --- src/arch/mips/Kconfig | 6 ++++-- src/soc/imgtec/pistachio/Kconfig | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/arch/mips/Kconfig b/src/arch/mips/Kconfig index 9e51d9cf13..b8570c1c5d 100644 --- a/src/arch/mips/Kconfig +++ b/src/arch/mips/Kconfig @@ -16,12 +16,12 @@ config ARCH_MIPS bool - default n + +if ARCH_MIPS config ARCH_BOOTBLOCK_MIPS bool default n - select ARCH_MIPS select BOOTBLOCK_CUSTOM select C_ENVIRONMENT_BOOTBLOCK @@ -36,3 +36,5 @@ config ARCH_ROMSTAGE_MIPS config ARCH_RAMSTAGE_MIPS bool default n + +endif # if ARCH_MIPS diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 333216d15d..40b63c3d5a 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -15,6 +15,7 @@ # config CPU_IMGTEC_PISTACHIO + select ARCH_MIPS select ARCH_BOOTBLOCK_MIPS select ARCH_VERSTAGE_MIPS select ARCH_ROMSTAGE_MIPS From eb5e47dd9467602d09a3f8e6e4cf5dd702bb0cc4 Mon Sep 17 00:00:00 2001 From: Weiyi Lu Date: Mon, 15 Apr 2019 15:29:26 +0800 Subject: [PATCH 110/231] mediatek/mt8183: update dcxo output buffer setting DCXO consists of core that generates clock and output buffers that provide clock to other peripheral components. This patch mainly eliminates the extra power consumption of output buffers. We only enable the buffer for SOC and disable unused buffers for power-saving. Also disable useless buffer power mode to guarantee the lowest power state. BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe Signed-off-by: Weiyi Lu Reviewed-on: https://review.coreboot.org/c/coreboot/+/32323 Reviewed-by: Julius Werner Reviewed-by: You-Cheng Syu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8183/include/soc/rtc.h | 1 + src/soc/mediatek/mt8183/rtc.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 841a202519..1f6f06a568 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -147,6 +147,7 @@ enum { PMIC_RG_DCXO_CW15 = 0x07AE, PMIC_RG_DCXO_CW16 = 0x07B0, PMIC_RG_DCXO_CW21 = 0x07BA, + PMIC_RG_DCXO_CW23 = 0x07BE, PMIC_RG_DCXO_ELR0 = 0x07C4 }; diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 5879088434..3bd3ab4921 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -274,9 +274,10 @@ static void dcxo_init(void) rtc_write(PMIC_RG_DCXO_CW16, 0x9855); /* 26M enable control */ - /* Enable clock buffer XO_SOC, XO_CEL */ - rtc_write(PMIC_RG_DCXO_CW00, 0x4805); + /* Enable clock buffer XO_SOC */ + rtc_write(PMIC_RG_DCXO_CW00, 0x4005); rtc_write(PMIC_RG_DCXO_CW11, 0x8000); + rtc_write(PMIC_RG_DCXO_CW23, 0x0053); /* Load thermal coefficient */ rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7); From 78561f481e3c25e23dc658f883a16402fd9d38f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 2 Jul 2019 13:19:39 +0300 Subject: [PATCH 111/231] lib/romstage_stack.c: Remove file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After platforms have moved to POSTCAR_STAGE=y the only remaining user is binaryPI now. Make it simpler. Change-Id: Ia70c5c85e06c42f965fb7204b633db9b619e2e84 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/33957 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel --- src/cpu/amd/pi/romstage.c | 3 +-- src/include/program_loading.h | 4 ---- src/lib/Makefile.inc | 2 -- src/lib/romstage_stack.c | 34 ---------------------------------- 4 files changed, 1 insertion(+), 42 deletions(-) delete mode 100644 src/lib/romstage_stack.c diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c index aa14826149..cfd41648ba 100644 --- a/src/cpu/amd/pi/romstage.c +++ b/src/cpu/amd/pi/romstage.c @@ -40,8 +40,7 @@ void *asmlinkage romstage_main(unsigned long bist) romstage_handoff_init(s3resume); - uintptr_t stack_top = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, - ROMSTAGE_STACK_CBMEM); + char *stack_top = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE); stack_top += HIGH_ROMSTAGE_STACK_SIZE; printk(BIOS_DEBUG, "Move CAR stack.\n"); diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 223fc0bef1..5ac74bf238 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -173,10 +173,6 @@ void run_romstage(void); /* Run ramstage from romstage. */ void run_ramstage(void); -/* Determine where stack for ramstage loader is located. */ -enum { ROMSTAGE_STACK_CBMEM, ROMSTAGE_STACK_LOW_MEM }; -uintptr_t romstage_ram_stack_base(size_t size, int src); - /* Backup OS memory to CBMEM_ID_RESUME on ACPI S3 resume path, * if ramstage overwrites low memory. */ void backup_ramstage_section(uintptr_t base, size_t size); diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 16d5c649b2..f6d3f6deb5 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -89,9 +89,7 @@ ramstage-y += region_file.c romstage-y += region_file.c ramstage-y += romstage_handoff.c romstage-y += romstage_handoff.c -romstage-y += romstage_stack.c romstage-y += selfboot.c -ramstage-y += romstage_stack.c romstage-y += stack.c ramstage-y += rtc.c diff --git a/src/lib/romstage_stack.c b/src/lib/romstage_stack.c deleted file mode 100644 index 4fe1459532..0000000000 --- a/src/lib/romstage_stack.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -/* - * Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. - */ -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - -uintptr_t romstage_ram_stack_base(size_t size, int src) -{ - /* cbmem_add() does a find() before add(). */ - if (src == ROMSTAGE_STACK_CBMEM) - return (uintptr_t)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, size); - if (src == ROMSTAGE_STACK_LOW_MEM) - return CONFIG_RAMTOP - size; - return 0; -} From c2f6c1d544938459f4cc00d22126a6985c6fef85 Mon Sep 17 00:00:00 2001 From: Krishna Prasad Bhat Date: Wed, 3 Apr 2019 15:33:14 +0530 Subject: [PATCH 112/231] mb/google/hatch: Update GPIO settings for SD card and SPI1 Chip select This patch updates the following GPIO settings. 1. Set Native termination for GPP_G0 - G4 SD card pins. 2. Set GPP_B19 to NF1. BUG=b:123907904 TEST=Verified SD card functionality on hatch. Checked for SD detection, transferred files to and from SD card. Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2 Signed-off-by: Krishna Prasad Bhat Reviewed-on: https://review.coreboot.org/c/coreboot/+/32176 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../google/hatch/variants/baseboard/gpio.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 56ae601df0..528ab02c5d 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -99,8 +99,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* B19 : GPP_B19 ==> NC */ - PAD_NC(GPP_B19, NONE), + /* B19 : Set to NF1 to match FSP setting it to NF1, i.e., GSPI1_CS0# */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* B20 : PCH_SPI_FPMCU_CLK_R */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* B21 : PCH_SPI_FPMCU_MISO */ @@ -311,15 +311,15 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ - PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1), /* G1 : SD_DATA0 */ - PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1), /* G2 : SD_DATA1 */ - PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1), /* G3 : SD_DATA2 */ - PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1), /* G4 : SD_DATA3 */ - PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1), /* G5 : SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1), /* G6 : SD_CLK */ From 3076deb391a69ea502cbf1312a83cb56d91a9b01 Mon Sep 17 00:00:00 2001 From: Frank Wu Date: Wed, 26 Jun 2019 17:13:05 +0800 Subject: [PATCH 113/231] mb/google/hatch: Set GPP_D9 as enable pin for Goodix Touch Screen and increase reset off delay time Goodix touchscreen cannot work in normal mode because PP3300_TOUCHSCREEN_DX dropped. Configure GPP_D9 as enable pin in the devicetree.cb to fix the power sequence. Increase reset_off_delay time from 1ms to 3ms to met the HW requirement. BUG=b:135287161 BRANCH=None TEST=local build and measure sequence with Goodix touch screen Change-Id: I33140869990aa4715c780b0fa322921e450530ef Signed-off-by: Frank Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/33808 Reviewed-by: Paul Fagerburg Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh Reviewed-by: EricR Lai Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/baseboard/gpio.c | 4 ++-- src/mainboard/google/hatch/variants/hatch/overridetree.cb | 4 +++- src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb | 4 +++- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 528ab02c5d..1da3d756e2 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -181,8 +181,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D7, NONE), /* D8 : WWAN_CONFIG_3 */ PAD_NC(GPP_D8, NONE), - /* D9 : GPP_D9 ==> NC */ - PAD_NC(GPP_D9, NONE), + /* D9 : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_D9, 0, DEEP), /* D10 : GPP_D10 ==> NC */ PAD_NC(GPP_D10, NONE), /* D11 : GPP_D11 ==> NC */ diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 2582940a1a..18878cee4a 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -90,7 +90,9 @@ chip soc/intel/cannonlake register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "10" - register "generic.reset_off_delay_ms" = "1" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "12" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb index 373438cf8a..03218675c0 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb @@ -81,7 +81,9 @@ chip soc/intel/cannonlake register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "10" - register "generic.reset_off_delay_ms" = "1" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "12" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end From af15d040e11aea95bb7ff14531739f5075d72bc9 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Mon, 6 May 2019 09:03:48 +0200 Subject: [PATCH 114/231] payloads/external/Memtest86Plus: update to version 002 stable The memtest86plus project has been tagged as stable. Update the coreboot build accordingly. Change-Id: I078ac5d91e60a424efb5e14f39ae59e7ae9cbfe2 Signed-off-by: Martin Kepplinger Reviewed-on: https://review.coreboot.org/c/coreboot/+/32613 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber Reviewed-by: Martin Roth --- payloads/external/Memtest86Plus/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/Memtest86Plus/Makefile b/payloads/external/Memtest86Plus/Makefile index 4b3132ddf5..b799f9ea71 100644 --- a/payloads/external/Memtest86Plus/Makefile +++ b/payloads/external/Memtest86Plus/Makefile @@ -15,7 +15,7 @@ TAG-$(CONFIG_MEMTEST_MASTER)=origin/master NAME-$(CONFIG_MEMTEST_MASTER)=Master -TAG-$(CONFIG_MEMTEST_STABLE)=3754fd440f4009b62244e0f95c56bbb12c2fffcb +TAG-$(CONFIG_MEMTEST_STABLE)=0bd34c22604660e4283316331f3e7bf8a3863753 NAME-$(CONFIG_MEMTEST_STABLE)=Stable TAG-$(CONFIG_MEMTEST_REVISION)=$(CONFIG_MEMTEST_REVISION_ID) From f8c3442df0db4aa6c842f6875677d38f378f31d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 6 Jul 2019 07:46:16 +0300 Subject: [PATCH 115/231] drivers/pc80: Move UDELAY_IO and UDELAY_TIMER2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No longer fallback to UDELAY_IO as default. Since these are not cpu properties or features, move the Kconfig location. Change-Id: I9809cdc285c7bf741aa391ddb5755390bbfc2909 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34107 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/cpu/x86/Kconfig | 10 ---------- src/drivers/pc80/pc/Kconfig | 14 +++++++++++++- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 608afd7a28..99a70750af 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -17,11 +17,6 @@ config PARALLEL_MP_AP_WORK Allow APs to do other work after initialization instead of going to sleep. -config UDELAY_IO - bool - default y if !UDELAY_LAPIC && !UDELAY_TSC && !UDELAY_TIMER2 && !GENERIC_UDELAY - default n - config UDELAY_LAPIC bool default n @@ -54,11 +49,6 @@ config TSC_MONOTONIC_TIMER help Expose monotonic time using the TSC. -# This option is used in code but never selected. -config UDELAY_TIMER2 - bool - default n - config TSC_SYNC_LFENCE bool default n diff --git a/src/drivers/pc80/pc/Kconfig b/src/drivers/pc80/pc/Kconfig index c44cf9144d..bba45f6a64 100644 --- a/src/drivers/pc80/pc/Kconfig +++ b/src/drivers/pc80/pc/Kconfig @@ -1,10 +1,11 @@ +if PC80_SYSTEM + # Might be removed (alongside with the PS/2 init code) once payloads # reliably support PS/2 init themselves. config DRIVERS_PS2_KEYBOARD bool "PS/2 keyboard init" default n - depends on PC80_SYSTEM help Enable this option to initialize PS/2 keyboards found connected to the PS/2 port. @@ -16,3 +17,14 @@ config DRIVERS_PS2_KEYBOARD If you know you will only use a payload which does not require this option, then you can say N here to speed up boot time. Otherwise say Y. + +config UDELAY_IO + bool + default n + +# This option is used in code but never selected. +config UDELAY_TIMER2 + bool + default n + +endif From c804f31a1331532f25b4936a4542d3241e3d5332 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 6 Jul 2019 06:49:37 +0300 Subject: [PATCH 116/231] intel/fsp_baytrail: Move TSC_MONOTONIC_TIMER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ib61ea29724401146eb6f008374cdf599f418e81f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34108 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber Reviewed-by: Werner Zeh --- src/mainboard/esd/atom15/Kconfig | 1 - src/mainboard/intel/bayleybay_fsp/Kconfig | 1 - src/mainboard/intel/minnowmax/Kconfig | 1 - src/mainboard/opencellular/rotundu/Kconfig | 1 - src/mainboard/siemens/mc_tcu3/Kconfig | 1 - src/soc/intel/fsp_baytrail/Kconfig | 1 + 6 files changed, 1 insertion(+), 5 deletions(-) diff --git a/src/mainboard/esd/atom15/Kconfig b/src/mainboard/esd/atom15/Kconfig index 94dae0882b..5726461539 100644 --- a/src/mainboard/esd/atom15/Kconfig +++ b/src/mainboard/esd/atom15/Kconfig @@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select TSC_MONOTONIC_TIMER config MAINBOARD_DIR string diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index c849438028..4a08fb1f78 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT - select TSC_MONOTONIC_TIMER config MAINBOARD_DIR string diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 59172e3190..ca24c92aa6 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select TSC_MONOTONIC_TIMER config MAINBOARD_DIR string diff --git a/src/mainboard/opencellular/rotundu/Kconfig b/src/mainboard/opencellular/rotundu/Kconfig index f5d9340114..fe1cbf94e6 100644 --- a/src/mainboard/opencellular/rotundu/Kconfig +++ b/src/mainboard/opencellular/rotundu/Kconfig @@ -22,7 +22,6 @@ config BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select ENABLE_BUILTIN_COM1 - select TSC_MONOTONIC_TIMER select ENABLE_FSP_FAST_BOOT select HAVE_ACPI_RESUME select USE_BLOBS diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index db0fd247f4..508aaebefb 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS select ENABLE_BUILTIN_COM1 select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select ENABLE_FSP_FAST_BOOT - select TSC_MONOTONIC_TIMER select DRIVER_INTEL_I210 select SOC_INTEL_FSP_BAYTRAIL_MD select USE_BLOBS diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 5228bb7ae4..26c95483c0 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -40,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_CONSTANT_RATE select TSC_SYNC_MFENCE select UDELAY_TSC + select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_HOOKED_UP select INTEL_DESCRIPTOR_MODE_CAPABLE From f2a66d2b0c6b7fb1a8f295585ab1e936b1c9c013 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 6 Jul 2019 06:49:37 +0300 Subject: [PATCH 117/231] intel/fsp_broadwell_de: Remove redundant TSC_MONOTONIC_TIMER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I240e9e767c9b38b3b06d3978fd20ddb37a96e470 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34109 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons Reviewed-by: Werner Zeh --- src/mainboard/intel/camelbackmountain_fsp/Kconfig | 1 - src/mainboard/ocp/monolake/Kconfig | 1 - src/mainboard/ocp/wedge100s/Kconfig | 1 - src/mainboard/siemens/mc_bdx1/Kconfig | 1 - 4 files changed, 4 deletions(-) diff --git a/src/mainboard/intel/camelbackmountain_fsp/Kconfig b/src/mainboard/intel/camelbackmountain_fsp/Kconfig index 2829b8441c..696fbf440c 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/Kconfig +++ b/src/mainboard/intel/camelbackmountain_fsp/Kconfig @@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select TSC_MONOTONIC_TIMER select INTEGRATED_UART if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index 037c322620..13d7876cea 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select TSC_MONOTONIC_TIMER select INTEGRATED_UART if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig index 491829a084..ef0fe88082 100644 --- a/src/mainboard/ocp/wedge100s/Kconfig +++ b/src/mainboard/ocp/wedge100s/Kconfig @@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select TSC_MONOTONIC_TIMER select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE select FSP_EHCI1_ENABLE diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig b/src/mainboard/siemens/mc_bdx1/Kconfig index d99fea8a0a..6feb1cf563 100644 --- a/src/mainboard/siemens/mc_bdx1/Kconfig +++ b/src/mainboard/siemens/mc_bdx1/Kconfig @@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select TSC_MONOTONIC_TIMER select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select CBFS_AUTOGEN_ATTRIBUTES select USE_SIEMENS_HWILIB From b14aedc3adf73156f2eef86e86abfe58479d7499 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 6 Jul 2019 08:27:17 +0300 Subject: [PATCH 118/231] intel/nehalem: Move TSC_MONOTONIC_TIMER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ib7f2f7773d0eef5ac4e277b44ee9114aa6729527 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34110 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/cpu/intel/model_2065x/Kconfig | 1 + src/northbridge/intel/nehalem/Kconfig | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index d8c016867c..0af0d35dda 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_TSC select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER select SMM_TSEG select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 1e504593ca..02b6e80832 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -18,7 +18,6 @@ config NORTHBRIDGE_INTEL_NEHALEM select CPU_INTEL_MODEL_2065X select VGA select INTEL_EDID - select TSC_MONOTONIC_TIMER select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select POSTCAR_STAGE From 26210fa040b4f2e987560a65fd3b4f822de670a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 6 Jul 2019 06:37:17 +0300 Subject: [PATCH 119/231] intel/socket_mPGA604: Enable TSC_MONOTONIC_TIMER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I3ca2b7752905209e8db6b1dc74b930445676792e Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34111 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/cpu/intel/socket_mPGA604/Kconfig | 1 + src/mainboard/aopen/dxplplusu/Kconfig | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index ca2f7b36ee..1453f9962b 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -9,6 +9,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select MMX select SSE select UDELAY_TSC + select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index 7dc0eab674..738a2ea0ae 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_I82870 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_LPC47M10X - select UDELAY_TSC select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 From fbdeb4af75d022c237ff48cb3021451d7e8c5328 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 14 Feb 2019 19:47:03 +0100 Subject: [PATCH 120/231] qemu-q35: die if started on wrong machine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The QEMU machine "PC" doesn't support MCFG. Die after console init if the user selected the wrong qemu machine and print a message to use the correct machine type. Without this patch ramstage dies with non-helpful message: "get_pbus: dev is NULL!" Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/31425 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki Reviewed-by: Paul Menzel --- src/mainboard/emulation/qemu-q35/bootblock.c | 7 +++++++ src/mainboard/emulation/qemu-q35/romstage.c | 14 ++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 13550f7e3d..d5ca7f9ce7 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -14,6 +14,7 @@ #include #include #include +#include /* Just define these here, there is no gm35.h file to include. */ #define D0F0_PCIEXBAR_LO 0x60 @@ -39,6 +40,12 @@ static void bootblock_northbridge_init(void) pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */ pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); + + /* MCFG is now active. If it's not qemu was started for machine PC */ + if (CONFIG(BOOTBLOCK_CONSOLE) && + (pci_read_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO) != + (CONFIG_MMCONF_BASE_ADDRESS | 1))) + die("You must run qemu for machine Q35 (-M q35)"); } static void enable_spi_prefetch(void) diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index e409ad1e5f..dbaead982a 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -22,6 +22,18 @@ #include #include #include +#include + +#define D0F0_PCIEXBAR_LO 0x60 + +static void mainboard_machine_check(void) +{ + /* Check that MCFG is active. If it's not qemu was started for machine PC */ + if (!CONFIG(BOOTBLOCK_CONSOLE) && + (pci_read_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO) != + (CONFIG_MMCONF_BASE_ADDRESS | 1))) + die("You must run qemu for machine Q35 (-M q35)"); +} asmlinkage void car_stage_entry(void) { @@ -29,6 +41,8 @@ asmlinkage void car_stage_entry(void) i82801ix_early_init(); console_init(); + mainboard_machine_check(); + cbmem_recovery(0); timestamp_add_now(TS_START_ROMSTAGE); From cca6e008687b7eb0f0a8862869702925a53ee2f4 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 26 Jun 2019 12:12:00 +0200 Subject: [PATCH 121/231] src/arch/x86/acpigen: Compare dev_states_count to size_t Spotted out using -Wconversion gcc warning option. Change-Id: Ib882cfa6d429fbfcab2b8132280182b427d510aa Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33803 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/arch/x86/acpigen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 74cd25a858..f9af10229e 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1115,7 +1115,7 @@ void acpigen_write_uuid(const char *uuid) void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order, const char *dev_states[], size_t dev_states_count) { - int i; + size_t i; for (i = 0; i < dev_states_count; i++) { acpigen_write_name(dev_states[i]); acpigen_write_package(1); From 3fcea0dfadde89fd425bcaaecdd357e0d10caf87 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 26 Jun 2019 12:18:15 +0200 Subject: [PATCH 122/231] cpu/x86/smm/smm_module_loader: Compare num_concurrent_stacks to size_t Spotted out using -Wconversion gcc warning option. Change-Id: I11e4792804f0f7b5a7ce504c46654c1bff775c32 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33804 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/cpu/x86/smm/smm_module_loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index b3ffb3d318..fb5c5f33e9 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -185,7 +185,7 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params, void *stacks_top; size_t size; char *base; - int i; + size_t i; struct smm_stub_params *stub_params; struct rmodule smm_stub; From 92185e373ea70b4a9af6fb7f38b0855d7d898bf3 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 28 May 2019 13:06:34 +0200 Subject: [PATCH 123/231] sb/intel/common: Add a common interface to set final OPs settings This adds a common place to set the final opprefix, optype and opmenu, with a hook to override the opmenu. Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33036 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/common/spi.c | 41 ++++++++++++++++++++++++++++++ src/southbridge/intel/common/spi.h | 38 +++++++++++++++++++++++++++ 2 files changed, 79 insertions(+) create mode 100644 src/southbridge/intel/common/spi.h diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index e9e66dcda3..8430dc8611 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -31,6 +31,8 @@ #include +#include "spi.h" + #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ @@ -1048,6 +1050,45 @@ static int spi_flash_protect(const struct spi_flash *flash, return 0; } +void spi_finalize_ops(void) +{ + struct ich_spi_controller *cntlr = &g_cntlr; + u16 spi_opprefix; + u16 optype = 0; + struct intel_swseq_spi_config spi_config = { + {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */ + { /* OPTYPE and OPCODE */ + {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ + {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */ + {0x03, READ_WITH_ADDR}, /* READ: Read Data */ + {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ + {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ + {0x9f, READ_NO_ADDR}, /* RDID: Read ID */ + {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */ + {0x0b, READ_WITH_ADDR}, /* FAST: Fast Read */ + } + }; + int i; + + if (spi_locked()) + return; + + intel_southbridge_override_spi(&spi_config); + + spi_opprefix = spi_config.opprefixes[0] + | (spi_config.opprefixes[1] << 8); + writew_(spi_opprefix, cntlr->preop); + for (i = 0; i < ARRAY_SIZE(spi_config.ops); i++) { + optype |= (spi_config.ops[i].type & 3) << (i * 2); + writeb_(spi_config.ops[i].op, &cntlr->opmenu[i]); + } + writew_(optype, &cntlr->optype); +} + +__weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) +{ +} + static const struct spi_ctrlr spi_ctrlr = { .xfer_vector = xfer_vectors, .max_xfer_size = member_size(struct ich9_spi_regs, fdata), diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h new file mode 100644 index 0000000000..3b8410cd9f --- /dev/null +++ b/src/southbridge/intel/common/spi.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_SPI_H +#define SOUTHBRIDGE_INTEL_SPI_H + +enum optype { + READ_NO_ADDR = 0, + WRITE_NO_ADDR = 1, + READ_WITH_ADDR = 2, + WRITE_WITH_ADDR = 3 +}; + +struct intel_spi_op { + u8 op; + enum optype type; +}; + +struct intel_swseq_spi_config { + u8 opprefixes[2]; + struct intel_spi_op ops[8]; +}; + +void spi_finalize_ops(void); +void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config); + +#endif From b429c5be15dd4263e8ddb599e1e1f15dd95c3bf0 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 28 May 2019 13:24:15 +0200 Subject: [PATCH 124/231] sb/intel/i82801gx: Use common final SPI OPs setup Change-Id: I30f80c237bccf8dc350249fd12ca6c4559d23d4f Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33037 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/i82801gx/i82801gx.h | 46 ----------------------- src/southbridge/intel/i82801gx/lpc.c | 7 +--- 2 files changed, 2 insertions(+), 51 deletions(-) diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 76420b4e17..fb855dc743 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -355,51 +355,5 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, #define C3_RES 0x54 #define TCO1_CNT 0x68 -/* SPIBAR - * - * SPI Opcode Menu setup for SPIBAR lockdown - * should support most common flash chips. - */ - -#define PREOP 0x54 -#define OPTYPE 0x56 -#define OPMENU 0x58 - -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ - #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 846a70997b..6236ebd800 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -33,6 +33,7 @@ #include #include #include +#include #include "chip.h" #include "i82801gx.h" @@ -621,11 +622,7 @@ static void lpc_final(struct device *dev) if (!CONFIG(INTEL_CHIPSET_LOCKDOWN)) return; - SPIBAR16(PREOP) = SPI_OPPREFIX; - /* Set SPI opcode menu */ - SPIBAR16(OPTYPE) = SPI_OPTYPE; - SPIBAR32(OPMENU) = SPI_OPMENU_LOWER; - SPIBAR32(OPMENU + 4) = SPI_OPMENU_UPPER; + spi_finalize_ops(); /* Lock SPIBAR */ SPIBAR16(0) = SPIBAR16(0) | (1 << 15); From aadd1d0eaf860c6b503f4f10e17ea0abec6a9939 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 28 May 2019 13:39:20 +0200 Subject: [PATCH 125/231] sb/intel/ibexpeak: Use common final SPI OPs setup This also removes the relevant RCBA replays the mainboard dir. Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33038 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Thomas Heijligen --- src/mainboard/lenovo/x201/mainboard.c | 29 -------------- src/mainboard/packardbell/ms2290/mainboard.c | 25 ------------ src/southbridge/intel/ibexpeak/lpc.c | 3 ++ src/southbridge/intel/ibexpeak/pch.h | 41 -------------------- 4 files changed, 3 insertions(+), 95 deletions(-) diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 70b393cc18..96033f88df 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -28,34 +28,6 @@ #include #include -static void mainboard_init(struct device *dev) -{ - printk(BIOS_SPEW, "starting SPI configuration\n"); - - /* Configure SPI. */ - RCBA32(0x3800) = 0x07ff0500; - RCBA32(0x3804) = 0x3f046008; - RCBA32(0x3808) = 0x0058efc0; - RCBA32(0x384c) = 0x92000000; - RCBA32(0x3850) = 0x00000a0b; - RCBA32(0x3858) = 0x07ff0500; - RCBA32(0x385c) = 0x04ff0003; - RCBA32(0x3860) = 0x00020001; - RCBA32(0x3864) = 0x00000fff; - RCBA32(0x3874) = 0; - RCBA32(0x3890) = 0xf8400000; - RCBA32(0x3894) = 0x143b5006; - RCBA32(0x3898) = 0x05200302; - RCBA32(0x389c) = 0x0601209f; - RCBA32(0x38b0) = 0x00000004; - RCBA32(0x38b4) = 0x03040002; - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x3804) = 0x3f04e008; - - printk(BIOS_SPEW, "SPI configured\n"); -} - static void fill_ssdt(struct device *device) { drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); @@ -65,7 +37,6 @@ static void mainboard_enable(struct device *dev) { u16 pmbase; - dev->ops->init = mainboard_init; dev->ops->acpi_fill_ssdt_generator = fill_ssdt; pmbase = pci_read_config32(pcidev_on_root(0x1f, 0), diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 28d3bb0958..785e6e8103 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -35,31 +35,6 @@ static void mainboard_enable(struct device *dev) { u16 pmbase; - printk(BIOS_SPEW, "starting SPI configuration\n"); - - /* Configure SPI. */ - RCBA32(0x3800) = 0x07ff0500; - RCBA32(0x3804) = 0x3f046008; - RCBA32(0x3808) = 0x0058efc0; - RCBA32(0x384c) = 0x92000000; - RCBA32(0x3850) = 0x00000a0b; - RCBA32(0x3858) = 0x07ff0500; - RCBA32(0x385c) = 0x04ff0003; - RCBA32(0x3860) = 0x00020001; - RCBA32(0x3864) = 0x00000fff; - RCBA32(0x3874) = 0; - RCBA32(0x3890) = 0xf8400000; - RCBA32(0x3894) = 0x143b5006; - RCBA32(0x3898) = 0x05200302; - RCBA32(0x389c) = 0x0601209f; - RCBA32(0x38b0) = 0x00000004; - RCBA32(0x38b4) = 0x03040002; - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x3804) = 0x3f04e008; - - printk(BIOS_SPEW, "SPI configured\n"); - int i; const u8 dmp[256] = { 0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x89, 0xe4, 0x30, 0x00, 0x40, 0x14, 0x00, 0x00, 0x00, 0x11, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index e7162b1e04..fa1ca92d78 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -38,6 +38,7 @@ #include "nvs.h" #include #include +#include #define NMI_OFF 0 @@ -785,6 +786,8 @@ static void southbridge_fill_ssdt(struct device *device) static void lpc_final(struct device *dev) { + spi_finalize_ops(); + /* Call SMM finalize() handlers before resume */ if (CONFIG(HAVE_SMI_HANDLER)) { if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 04cc21d475..24a7905ed2 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -455,47 +455,6 @@ void southbridge_configure_default_intmap(void); #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 -/* - * SPI Opcode Menu setup for SPIBAR lockdown - * should support most common flash chips. - */ - -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ - #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ From a3121b0b2fca0a1f568fe66e5ca3baed1be8acee Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 28 May 2019 13:46:49 +0200 Subject: [PATCH 126/231] sb/intel/lynxpoint: Use common final SPI OPs setup Change-Id: I12e238b3a33c909103986822bd7398e1c3bac676 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33039 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/lynxpoint/lpc.c | 6 ++--- src/southbridge/intel/lynxpoint/pch.h | 36 --------------------------- 2 files changed, 2 insertions(+), 40 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index b0f57c122b..4efb83e05e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -36,6 +36,7 @@ #include #include #include +#include #define NMI_OFF 0 @@ -960,10 +961,7 @@ static unsigned long southbridge_write_acpi_tables(struct device *device, static void lpc_final(struct device *dev) { - RCBA16(0x3894) = SPI_OPPREFIX; - RCBA16(0x3896) = SPI_OPTYPE; - RCBA32(0x3898) = SPI_OPMENU_LOWER; - RCBA32(0x389c) = SPI_OPMENU_UPPER; + spi_finalize_ops(); if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) outb(APM_CNT_FINALIZE, APM_CNT); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 93c2bc5703..626d22d57f 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -746,42 +746,6 @@ void mainboard_config_superio(void); #define FDOC 0xb0 #define FDOD 0xb4 -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ - #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ From 674bb3bf65635cc08730be298eeee540efc899bd Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 24 May 2019 09:07:04 +0200 Subject: [PATCH 127/231] util/superiotool: Add AST2400 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for AST2400 Super I/O. The device doesn't have an ID register, so probe for scratch register not to read as 0xff. Tested on platform which has an AST2400. Change-Id: I86af69c6b2ccefe2c88eef875bc858239df834f1 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32984 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- util/superiotool/Makefile | 2 +- util/superiotool/aspeed.c | 128 +++++++++++++++++++++++++++++++++ util/superiotool/superiotool.h | 6 ++ 3 files changed, 135 insertions(+), 1 deletion(-) create mode 100644 util/superiotool/aspeed.c diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 3a0bcf0abe..2bc88aba64 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -29,7 +29,7 @@ CFLAGS += -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \ LDFLAGS += -lz OBJS = superiotool.o serverengines.o ali.o exar.o fintek.o ite.o nsc.o \ - nuvoton.o smsc.o winbond.o infineon.o + nuvoton.o smsc.o winbond.o infineon.o aspeed.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/superiotool/aspeed.c b/util/superiotool/aspeed.c new file mode 100644 index 0000000000..6d49c16e9a --- /dev/null +++ b/util/superiotool/aspeed.c @@ -0,0 +1,128 @@ +/* + * This file is part of the superiotool project. + * + * Copyright (C) 9elements Agency GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "superiotool.h" + +#define DEVICE_SCRATCH_REG 0x21 + +static const struct superio_registers reg_table[] = { + {0x00, "AST2400", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x02, "SUART1", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x02,RSVD,EOT}}, + {0x03, "SUART1", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x02,0x00,EOT}}, + {0x04, "SWC", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67, + 0x70,0x71,EOT}, + {0x00,0x08,0xe6,0x08,0xe0,0x08,0xe4,0x08,0xe8, + 0x09,0x01,EOT}}, + {0x05, "Keyboard config (KBC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x72,0x73, + 0xf0,EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x02,0x0c,0x02, + 0x83,EOT}}, + {0x07, "GPIO", + {0x30,0x38,0x70,0x71,EOT}, + {0x00,0x00,0x0b,0x01,EOT}}, + {0x0b, "SUART3", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x03,0xe8,0x06,0x02,0x00,EOT}}, + {0x0c, "SUART4", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x02,0xe8,0x05,0x02,0x00,EOT}}, + {0x0d, "iLPC2AHB", + {0x30,0x70,0x71,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5, + 0xf6,0xf7,0xf8,0xfe,EOT}, + {0x00,0x09,0x01,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,0x00,0x00,EOT}}, + {0x0e, "Mailbox", + {0x30,0x60,0x61,0x70,0x71,EOT}, + {0x00,0x08,0xc0,0x09,0x01,EOT}}, + {EOT}}}, + {EOT} +}; + +static void enter_conf_mode_ast(uint16_t port) +{ + OUTB(0xa5, port); + OUTB(0xa5, port); +} + +static void exit_conf_mode_ast(uint16_t port) +{ + OUTB(0xaa, port); +} + +static int detect_ast_superio(uint16_t port) +{ + int i; + enter_conf_mode_ast(port); + + /* Aspeed devices doesn't have a DEVICE_ID_REG. + * Host cycles that aren't decoded read as 0xff. + * Probe for the scratch register that are initialized to zero. + * The firmware might overwrite that, but it's the best we have. + */ + + for (i = DEVICE_SCRATCH_REG; i < 0x30; i++) { + if (regval(port, i) != 0xff) + break; + } + if (i == 0x30) { + if (verbose) + printf(NOTFOUND + "scratch registers all read as 0xff\n"); + } + exit_conf_mode_ast(port); + + return i < 0x30; +} + +void probe_idregs_aspeed(uint16_t port) +{ + uint16_t chip_id = 0; + + probing_for("Aspeed", "", port); + + if (!detect_ast_superio(port)) + return; + + if (superio_unknown(reg_table, chip_id)) { + if (verbose) + printf(NOTFOUND "id=0x%02x\n", chip_id); + return; + } + + printf("Found Aspeed %s (id=0x%02x) at 0x%x\n", + get_superio_name(reg_table, chip_id), chip_id, port); + chip_found = 1; + + enter_conf_mode_ast(port); + dump_superio("Aspeed", reg_table, port, chip_id, LDN_SEL); + exit_conf_mode_ast(port); +} + +void print_aspeed_chips(void) +{ + print_vendor_chips("Aspeed", reg_table); +} diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index 6e59933792..d3b9fd004c 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -190,6 +190,10 @@ void print_vendor_chips(const char *vendor, void probe_idregs_ali(uint16_t port); void print_ali_chips(void); +/* aspeed.c */ +void probe_idregs_aspeed(uint16_t port); +void print_aspeed_chips(void); + /* amd.c */ void probe_idregs_amd(uint16_t port); void print_amd_chips(void); @@ -243,6 +247,7 @@ static const struct { int ports[MAXNUMPORTS]; /* Signed, as we need EOT. */ } superio_ports_table[] = { {probe_idregs_ali, {0x3f0, 0x370, EOT}}, + {probe_idregs_aspeed, {0x2e, 0x4e, EOT}}, {probe_idregs_exar, {0x2e, 0x4e, EOT}}, {probe_idregs_fintek, {0x2e, 0x4e, EOT}}, {probe_idregs_fintek_alternative, {0x2e, 0x4e, EOT}}, @@ -278,6 +283,7 @@ static const struct { #ifdef PCI_SUPPORT {print_via_chips}, {print_amd_chips}, + {print_aspeed_chips}, #endif {print_serverengines_chips}, {print_infineon_chips}, From 45564050ec00b6d4b2c5b27cf26a56b46db8df1c Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 8 Jul 2019 22:11:52 +0200 Subject: [PATCH 128/231] crossgcc: Fix runtime initialization of a constant GNAT had a constant initialized at runtime which led to trouble with compilers that decided to place it into an actual constant section (e.g. GCC 9). Usually, this would be handled gracefully if the Ada compiler knew about the runtime initialization. How- ever, as the initialization was done by taking the address of the variable, the compiler had no clue. Change-Id: I73ce4cadc612c814ed2e22b44f429af2ad3db288 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/34147 Reviewed-by: Patrick Georgi Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons Reviewed-by: Edward O'Callaghan Tested-by: build bot (Jenkins) --- .../patches/gcc-8.3.0_gnat-bad_constant.patch | 150 ++++++++++++++++++ 1 file changed, 150 insertions(+) create mode 100644 util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch diff --git a/util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch b/util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch new file mode 100644 index 0000000000..e98f933a13 --- /dev/null +++ b/util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch @@ -0,0 +1,150 @@ +commit b6f742f96c62bab0582021455328ae3be58e16d3 +Author: pmderodat +Date: Fri May 25 09:05:10 2018 +0000 + + [Ada] Remove "constant" attribute on Osint.Unknown_Attributes + + 2018-05-25 Arnaud Charlet + + gcc/ada/ + + * exp_aggr.adb (Convert_To_Positional): Bump default for + Max_Others_Replicate to 32. Update comments. + * osint.ads (Unknown_Attributes): No longer pretend this is a constant. + (No_File_Info_Cache): Initialize separately. + * osint.adb (No_File_Info_Cache): Update initializer. + + git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260739 138bc75d-0d04-0410-961f-82ee72b054a4 + +diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog +index e4127e472aa..d56240b7b82 100644 +--- a/gcc/ada/ChangeLog ++++ b/gcc/ada/ChangeLog +@@ -188,6 +188,14 @@ + an allocator if the type is an unconstrained record type with default + discriminant. + ++2018-05-25 Arnaud Charlet ++ ++ * exp_aggr.adb (Convert_To_Positional): Bump default for ++ Max_Others_Replicate to 32. Update comments. ++ * osint.ads (Unknown_Attributes): No longer pretend this is a constant. ++ (No_File_Info_Cache): Initialize separately. ++ * osint.adb (No_File_Info_Cache): Update initializer. ++ + 2018-05-04 John Marino + + PR ada/85635 +diff --git a/gcc/ada/exp_aggr.adb b/gcc/ada/exp_aggr.adb +index f723c1b4d99..ff5210eb4e4 100644 +--- a/gcc/ada/exp_aggr.adb ++++ b/gcc/ada/exp_aggr.adb +@@ -284,14 +284,14 @@ package body Exp_Aggr is + + procedure Convert_To_Positional + (N : Node_Id; +- Max_Others_Replicate : Nat := 5; ++ Max_Others_Replicate : Nat := 32; + Handle_Bit_Packed : Boolean := False); + -- If possible, convert named notation to positional notation. This + -- conversion is possible only in some static cases. If the conversion is + -- possible, then N is rewritten with the analyzed converted aggregate. + -- The parameter Max_Others_Replicate controls the maximum number of + -- values corresponding to an others choice that will be converted to +- -- positional notation (the default of 5 is the normal limit, and reflects ++ -- positional notation (the default of 32 is the normal limit, and reflects + -- the fact that normally the loop is better than a lot of separate + -- assignments). Note that this limit gets overridden in any case if + -- either of the restrictions No_Elaboration_Code or No_Implicit_Loops is +@@ -301,11 +301,6 @@ package body Exp_Aggr is + -- Packed_Array_Aggregate_Handled, we set this parameter to True, since + -- these are cases we handle in there. + +- -- It would seem useful to have a higher default for Max_Others_Replicate, +- -- but aggregates in the compiler make this impossible: the compiler +- -- bootstrap fails if Max_Others_Replicate is greater than 25. This +- -- is unexpected ??? +- + procedure Expand_Array_Aggregate (N : Node_Id); + -- This is the top-level routine to perform array aggregate expansion. + -- N is the N_Aggregate node to be expanded. +@@ -4292,7 +4287,7 @@ package body Exp_Aggr is + + procedure Convert_To_Positional + (N : Node_Id; +- Max_Others_Replicate : Nat := 5; ++ Max_Others_Replicate : Nat := 32; + Handle_Bit_Packed : Boolean := False) + is + Typ : constant Entity_Id := Etype (N); +diff --git a/gcc/ada/osint.adb b/gcc/ada/osint.adb +index 0c23761b6dc..896fbc7ee37 100644 +--- a/gcc/ada/osint.adb ++++ b/gcc/ada/osint.adb +@@ -250,8 +250,7 @@ package body Osint is + Attr : aliased File_Attributes; + end record; + +- No_File_Info_Cache : constant File_Info_Cache := +- (No_File, Unknown_Attributes); ++ No_File_Info_Cache : constant File_Info_Cache := (No_File, (others => 0)); + + package File_Name_Hash_Table is new GNAT.HTable.Simple_HTable ( + Header_Num => File_Hash_Num, +diff --git a/gcc/ada/osint.ads b/gcc/ada/osint.ads +index 65a87fe4ce3..6c75b521456 100644 +--- a/gcc/ada/osint.ads ++++ b/gcc/ada/osint.ads +@@ -255,10 +255,26 @@ package Osint is + -- from the disk and then cached in the File_Attributes parameter (possibly + -- along with other values). + +- type File_Attributes is private; +- Unknown_Attributes : constant File_Attributes; ++ File_Attributes_Size : constant Natural := 32; ++ -- This should be big enough to fit a "struct file_attributes" on any ++ -- system. It doesn't cause any malfunction if it is too big (which avoids ++ -- the need for either mapping the struct exactly or importing the sizeof ++ -- from C, which would result in dynamic code). However, it does waste ++ -- space (e.g. when a component of this type appears in a record, if it is ++ -- unnecessarily large). Note: for runtime units, use System.OS_Constants. ++ -- SIZEOF_struct_file_attributes instead, which has the exact value. ++ ++ type File_Attributes is ++ array (1 .. File_Attributes_Size) ++ of System.Storage_Elements.Storage_Element; ++ for File_Attributes'Alignment use Standard'Maximum_Alignment; ++ ++ Unknown_Attributes : File_Attributes; + -- A cache for various attributes for a file (length, accessibility,...) +- -- This must be initialized to Unknown_Attributes prior to the first call. ++ -- Will be initialized properly at elaboration (for efficiency later on, ++ -- avoid function calls every time we want to reset the attributes) prior ++ -- to the first usage. We cannot make it constant since the compiler may ++ -- put it in a read-only section. + + function Is_Directory + (Name : C_File_Name; +@@ -754,22 +770,4 @@ private + -- detected, the file being written is deleted, and a fatal error is + -- signalled. + +- File_Attributes_Size : constant Natural := 32; +- -- This should be big enough to fit a "struct file_attributes" on any +- -- system. It doesn't cause any malfunction if it is too big (which avoids +- -- the need for either mapping the struct exactly or importing the sizeof +- -- from C, which would result in dynamic code). However, it does waste +- -- space (e.g. when a component of this type appears in a record, if it is +- -- unnecessarily large). Note: for runtime units, use System.OS_Constants. +- -- SIZEOF_struct_file_attributes instead, which has the exact value. +- +- type File_Attributes is +- array (1 .. File_Attributes_Size) +- of System.Storage_Elements.Storage_Element; +- for File_Attributes'Alignment use Standard'Maximum_Alignment; +- +- Unknown_Attributes : constant File_Attributes := (others => 0); +- -- Will be initialized properly at elaboration (for efficiency later on, +- -- avoid function calls every time we want to reset the attributes). +- + end Osint; From df29d23ee3f36d3d6a5fa0fde46beeb67554a8da Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 5 Jul 2019 16:00:38 +0530 Subject: [PATCH 129/231] soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/34085 Reviewed-by: Aamir Bohra Reviewed-by: Lean Sheng Tan Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/acpi.c | 3 +-- src/soc/intel/icelake/chip.c | 3 +-- src/soc/intel/icelake/cpu.c | 3 +-- src/soc/intel/icelake/espi.c | 3 +-- src/soc/intel/icelake/finalize.c | 3 +-- src/soc/intel/icelake/fsp_params.c | 2 +- src/soc/intel/icelake/include/soc/ramstage.h | 3 +-- src/soc/intel/icelake/memmap.c | 3 +-- src/soc/intel/icelake/pmc.c | 3 +-- src/soc/intel/icelake/pmutil.c | 3 +-- src/soc/intel/icelake/romstage/fsp_params.c | 2 +- src/soc/intel/icelake/romstage/romstage.c | 3 +-- src/soc/intel/icelake/sd.c | 2 +- src/soc/intel/icelake/smihandler.c | 3 +-- src/soc/intel/icelake/smmrelocate.c | 2 +- 15 files changed, 15 insertions(+), 26 deletions(-) diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 3a46c930ab..ae7b344df0 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -27,12 +27,11 @@ #include #include #include +#include #include #include #include -#include "chip.h" - /* * List of supported C-states in this processor. */ diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index eff1c7a17c..ceef266c06 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -26,8 +26,7 @@ #include #include #include - -#include "chip.h" +#include #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 527b989e1a..67d41d79fd 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -31,8 +31,7 @@ #include #include #include - -#include "chip.h" +#include static void soc_fsp_load(void) { diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 8ab909d861..a4b6d80aa9 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -29,8 +29,7 @@ #include #include #include - -#include "chip.h" +#include /* * As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index b838c199e7..e035c958df 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -30,11 +30,10 @@ #include #include #include +#include #include #include -#include "chip.h" - #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ #define CAM_CLK_EN (1 << 1) diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index ac7edd2dbb..8b65a89731 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -23,6 +22,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/icelake/include/soc/ramstage.h b/src/soc/intel/icelake/include/soc/ramstage.h index d78380a6dc..606e2ffb8d 100644 --- a/src/soc/intel/icelake/include/soc/ramstage.h +++ b/src/soc/intel/icelake/include/soc/ramstage.h @@ -19,8 +19,7 @@ #include #include #include - -#include "../../chip.h" +#include void mainboard_silicon_init_params(FSP_S_CONFIG *params); void soc_init_pre_device(void *chip_info); diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 49af604c75..67f71da28a 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -23,11 +23,10 @@ #include #include #include +#include #include #include -#include "chip.h" - void smm_region(void **start, size_t *size) { *start = (void *)sa_get_tseg_base(); diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 053d7e8e46..d98c83ecdb 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -23,8 +23,7 @@ #include #include #include - -#include "chip.h" +#include /* * Set which power state system will be after reapplying diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 0edec4bb1d..45f2a70d7c 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -37,10 +37,9 @@ #include #include #include +#include #include -#include "chip.h" - /* * SMI */ diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index fa6f9392a4..420c427e7a 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -14,12 +14,12 @@ */ #include -#include #include #include #include #include #include +#include static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_icelake_config *config) diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 514e5e8925..65e65cc80e 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -27,11 +27,10 @@ #include #include #include +#include #include #include -#include "../chip.h" - #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ diff --git a/src/soc/intel/icelake/sd.c b/src/soc/intel/icelake/sd.c index 19c3bca459..4d84bb43ff 100644 --- a/src/soc/intel/icelake/sd.c +++ b/src/soc/intel/icelake/sd.c @@ -14,7 +14,7 @@ */ #include -#include "chip.h" +#include int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, struct device *dev) { diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index a7ea0948ea..3d41ee034d 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -23,8 +23,7 @@ #include #include #include - -#include "chip.h" +#include #define CSME0_FBE 0xf #define CSME0_BAR 0x0 diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 05871e4f23..4e2d6840bb 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -31,8 +31,8 @@ #include #include #include +#include #include -#include "chip.h" /* This gets filled in and used during relocation. */ static struct smm_relocation_params smm_reloc_params; From cb587a2522a9f5b68ee10e70832fa90eb84e6cc2 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 3 Jul 2019 16:50:17 +0530 Subject: [PATCH 130/231] drivers/intel: Move FSP stage_cache implementation into common block Change-Id: Iebb6d698c236a95162b3c7eb07987483a293b50a Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/34005 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/intel/fsp2_0/Makefile.inc | 3 --- src/drivers/intel/fsp2_0/stage_cache.c | 29 -------------------------- src/soc/intel/common/block/smm/smm.c | 13 ++++++++++++ 3 files changed, 13 insertions(+), 32 deletions(-) delete mode 100644 src/drivers/intel/fsp2_0/stage_cache.c diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index d627a3dbb1..b0a1f2b4e2 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -23,7 +23,6 @@ romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c romstage-y += util.c romstage-y += memory_init.c -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c ramstage-y += debug.c @@ -34,12 +33,10 @@ ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c ramstage-y += notify.c ramstage-y += silicon_init.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma_core.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c postcar-$(CONFIG_FSP_CAR) += util.c postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c deleted file mode 100644 index a9ec154d38..0000000000 --- a/src/drivers/intel/fsp2_0/stage_cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -void stage_cache_external_region(void **base, size_t *size) -{ - if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; - *size = 0; - } -} diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index 75b933e0e9..a2a7c164c8 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -18,10 +18,23 @@ #include #include #include +#include #include #include #include #include +#include + +#if !CONFIG(PLATFORM_USES_FSP1_1) +void stage_cache_external_region(void **base, size_t *size) +{ + if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { + printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); + *base = NULL; + *size = 0; + } +} +#endif void smm_southbridge_clear_state(void) { From 9265f89f4e892caa043f60272980e7cec81bce62 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 7 Jul 2019 23:58:34 +0300 Subject: [PATCH 131/231] arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber Reviewed-by: Furquan Shaikh Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) --- src/arch/x86/Makefile.inc | 2 -- src/cpu/amd/agesa/family15tn/Makefile.inc | 2 +- src/cpu/amd/pi/00630F01/Makefile.inc | 2 +- src/cpu/intel/common/Makefile.inc | 2 +- src/cpu/intel/haswell/Makefile.inc | 4 ++-- src/cpu/intel/model_2065x/Makefile.inc | 4 ++-- src/cpu/intel/model_206ax/Makefile.inc | 6 +++--- src/cpu/x86/smm/Makefile.inc | 9 ++++----- src/cpu/x86/tsc/Makefile.inc | 2 -- src/ec/acpi/Makefile.inc | 2 +- src/ec/lenovo/pmh7/Makefile.inc | 2 +- src/mainboard/google/auron/Makefile.inc | 2 +- src/mainboard/google/beltino/Makefile.inc | 2 +- src/mainboard/google/butterfly/Makefile.inc | 2 +- src/mainboard/google/cyan/Makefile.inc | 2 +- src/mainboard/google/dragonegg/Makefile.inc | 2 +- src/mainboard/google/eve/Makefile.inc | 2 +- src/mainboard/google/fizz/Makefile.inc | 2 +- src/mainboard/google/fizz/variants/karma/Makefile.inc | 2 +- src/mainboard/google/glados/Makefile.inc | 2 +- .../google/glados/variants/caroline/Makefile.inc | 2 +- src/mainboard/google/glados/variants/cave/Makefile.inc | 2 +- src/mainboard/google/glados/variants/chell/Makefile.inc | 2 +- src/mainboard/google/glados/variants/glados/Makefile.inc | 2 +- src/mainboard/google/hatch/Makefile.inc | 2 +- src/mainboard/google/jecht/Makefile.inc | 2 +- src/mainboard/google/kahlee/Makefile.inc | 2 +- src/mainboard/google/link/Makefile.inc | 2 +- src/mainboard/google/octopus/Makefile.inc | 2 +- src/mainboard/google/poppy/Makefile.inc | 2 +- src/mainboard/google/poppy/variants/nami/Makefile.inc | 2 +- .../google/poppy/variants/nautilus/Makefile.inc | 4 ++-- .../google/poppy/variants/nocturne/Makefile.inc | 2 +- src/mainboard/google/rambi/Makefile.inc | 2 +- src/mainboard/google/reef/Makefile.inc | 2 +- src/mainboard/google/sarien/Makefile.inc | 2 +- src/mainboard/google/slippy/Makefile.inc | 2 +- src/mainboard/google/stout/Makefile.inc | 4 ++-- src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc | 2 +- src/mainboard/intel/baskingridge/Makefile.inc | 2 +- src/mainboard/intel/cannonlake_rvp/Makefile.inc | 2 +- src/mainboard/intel/dcp847ske/Makefile.inc | 2 +- src/mainboard/intel/glkrvp/Makefile.inc | 2 +- src/mainboard/intel/kblrvp/Makefile.inc | 2 +- src/mainboard/intel/kunimitsu/Makefile.inc | 2 +- src/mainboard/intel/strago/Makefile.inc | 2 +- src/mainboard/lenovo/g505s/Makefile.inc | 2 +- src/mainboard/lenovo/l520/Makefile.inc | 2 +- src/mainboard/lenovo/s230u/Makefile.inc | 2 +- src/mainboard/lenovo/t420/Makefile.inc | 2 +- src/mainboard/lenovo/t420s/Makefile.inc | 2 +- src/mainboard/lenovo/t430/Makefile.inc | 2 +- src/mainboard/lenovo/t430s/Makefile.inc | 2 +- src/mainboard/lenovo/t520/Makefile.inc | 2 +- src/mainboard/lenovo/t530/Makefile.inc | 2 +- src/mainboard/lenovo/t60/Makefile.inc | 2 +- src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc | 2 +- src/mainboard/lenovo/x201/Makefile.inc | 4 ++-- src/mainboard/lenovo/x220/Makefile.inc | 2 +- src/mainboard/lenovo/x230/Makefile.inc | 2 +- src/mainboard/lenovo/x60/Makefile.inc | 2 +- src/mainboard/lenovo/z61t/Makefile.inc | 2 +- src/mainboard/packardbell/ms2290/Makefile.inc | 2 +- src/mainboard/scaleway/tagada/Makefile.inc | 2 +- src/northbridge/intel/fsp_rangeley/Makefile.inc | 2 +- src/northbridge/intel/gm45/Makefile.inc | 2 +- src/northbridge/intel/haswell/Makefile.inc | 2 +- src/northbridge/intel/nehalem/Makefile.inc | 2 +- src/northbridge/intel/sandybridge/Makefile.inc | 4 ++-- src/soc/intel/denverton_ns/Makefile.inc | 8 ++++---- src/soc/intel/fsp_baytrail/Makefile.inc | 8 ++++---- src/soc/intel/fsp_broadwell_de/Makefile.inc | 6 +++--- src/southbridge/amd/agesa/hudson/Makefile.inc | 2 +- src/southbridge/amd/pi/hudson/Makefile.inc | 4 ++-- src/southbridge/intel/bd82x6x/Makefile.inc | 2 +- src/southbridge/intel/i82801dx/Makefile.inc | 2 +- src/southbridge/intel/i82801gx/Makefile.inc | 2 +- src/southbridge/intel/i82801ix/Makefile.inc | 2 +- src/southbridge/intel/i82801jx/Makefile.inc | 2 +- src/southbridge/intel/lynxpoint/Makefile.inc | 6 +++--- 80 files changed, 100 insertions(+), 105 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 025b933dba..32e0173804 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -404,8 +404,6 @@ smm-y += memmove.c smm-y += memset.c smm-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c -ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/smihandler.c),) smm-srcs += src/mainboard/$(MAINBOARDDIR)/smihandler.c endif -endif diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 98a7050c21..46ae346282 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -19,7 +19,7 @@ ramstage-y += fixme.c ramstage-y += chip_name.c ramstage-y += model_15_init.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c +smm-y += udelay.c subdirs-y += ../../mtrr subdirs-y += ../../smm diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc index 98a7050c21..46ae346282 100644 --- a/src/cpu/amd/pi/00630F01/Makefile.inc +++ b/src/cpu/amd/pi/00630F01/Makefile.inc @@ -19,7 +19,7 @@ ramstage-y += fixme.c ramstage-y += chip_name.c ramstage-y += model_15_init.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c +smm-y += udelay.c subdirs-y += ../../mtrr subdirs-y += ../../smm diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index b67ca85f0e..2fc6da908b 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -2,4 +2,4 @@ ramstage-y += common_init.c romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += fsb.c +smm-y += fsb.c diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 72f66ef7b8..a472da2d5e 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -13,8 +13,8 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +smm-y += finalize.c +smm-y += tsc_freq.c ifneq ($(CONFIG_TSC_MONOTONIC_TIMER),y) bootblock-y += monotonic_timer.c diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index f494e9b049..9a11b06e4d 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -13,11 +13,11 @@ subdirs-y += ../common ramstage-y += tsc_freq.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +smm-y += tsc_freq.c ramstage-y += acpi.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-y += finalize.c romstage-y += stage_cache.c ramstage-y += stage_cache.c diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 78a6283a5d..f5de8c38fa 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -15,14 +15,14 @@ ramstage-y += acpi.c ramstage-y += common.c romstage-y += common.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c +smm-y += common.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +smm-y += tsc_freq.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-y += finalize.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index e6add1d0d0..5c7aab3ffc 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -36,13 +36,16 @@ $(call src-to-obj,ramstage,$(obj)/cpu/x86/smm/smm.manual): $(obj)/smm/smm @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) +ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual +endif + ifeq ($(CONFIG_SMM_TSEG),y) smmstub-y += smm_stub.S smm-y += smm_module_handler.c -ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual ramstage-srcs += $(obj)/cpu/x86/smm/smmstub.manual # SMM Stub Module. The stub is used as a trampoline for relocation and normal @@ -82,10 +85,6 @@ $(obj)/smm/smm: $(obj)/smm/smm.o $(src)/cpu/x86/smm/smm.ld $(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@ -ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) -ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual -endif - smm-y += smmhandler.S smm-y += smihandler.c diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index 9751cacc87..ab7453f262 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -3,6 +3,4 @@ ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c postcar-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c -ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c -endif diff --git a/src/ec/acpi/Makefile.inc b/src/ec/acpi/Makefile.inc index 34fc307d5c..fae8fbf6b3 100644 --- a/src/ec/acpi/Makefile.inc +++ b/src/ec/acpi/Makefile.inc @@ -2,6 +2,6 @@ ifeq ($(CONFIG_EC_ACPI),y) ramstage-y += ec.c romstage-y += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c +smm-y += ec.c endif diff --git a/src/ec/lenovo/pmh7/Makefile.inc b/src/ec/lenovo/pmh7/Makefile.inc index a619cc7a3f..d5524dca1f 100644 --- a/src/ec/lenovo/pmh7/Makefile.inc +++ b/src/ec/lenovo/pmh7/Makefile.inc @@ -1,7 +1,7 @@ ifeq ($(CONFIG_EC_LENOVO_PMH7),y) ramstage-y += pmh7.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += pmh7.c +smm-y += pmh7.c romstage-y += pmh7.c endif diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index d2b6d0eb9a..6b1de0536c 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -19,7 +19,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index bb90e9780b..e1bebc1369 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -18,7 +18,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c ramstage-y += lan.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c variants/$(VARIANT_DIR)/led.c +smm-y += smihandler.c variants/$(VARIANT_DIR)/led.c romstage-y += variants/$(VARIANT_DIR)/led.c diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index 8033e1c325..b6654b8c0a 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -19,6 +19,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c romstage-y += gpio.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +smm-y += mainboard_smi.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index 027c49cc8f..86198a61dc 100644 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -24,7 +24,7 @@ ramstage-y += ec.c ramstage-y += irqroute.c ramstage-y += w25q64.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/dragonegg/Makefile.inc b/src/mainboard/google/dragonegg/Makefile.inc index 39e94d0119..dcd8cbccbc 100644 --- a/src/mainboard/google/dragonegg/Makefile.inc +++ b/src/mainboard/google/dragonegg/Makefile.inc @@ -26,7 +26,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c ramstage-y += ramstage.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/eve/Makefile.inc b/src/mainboard/google/eve/Makefile.inc index c96e23ea49..d853404a45 100644 --- a/src/mainboard/google/eve/Makefile.inc +++ b/src/mainboard/google/eve/Makefile.inc @@ -26,4 +26,4 @@ ramstage-y += mainboard.c ramstage-y += ramstage.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c diff --git a/src/mainboard/google/fizz/Makefile.inc b/src/mainboard/google/fizz/Makefile.inc index 59f84b543a..5514090d4e 100644 --- a/src/mainboard/google/fizz/Makefile.inc +++ b/src/mainboard/google/fizz/Makefile.inc @@ -25,7 +25,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c ramstage-y += ramstage.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/fizz/variants/karma/Makefile.inc b/src/mainboard/google/fizz/variants/karma/Makefile.inc index 747552267d..ec115e4655 100644 --- a/src/mainboard/google/fizz/variants/karma/Makefile.inc +++ b/src/mainboard/google/fizz/variants/karma/Makefile.inc @@ -3,4 +3,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += nhlt.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc index ccfeb8506f..da9de29521 100644 --- a/src/mainboard/google/glados/Makefile.inc +++ b/src/mainboard/google/glados/Makefile.inc @@ -29,7 +29,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c ramstage-y += ramstage.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/glados/variants/caroline/Makefile.inc b/src/mainboard/google/glados/variants/caroline/Makefile.inc index 73d7090953..21b20e6912 100644 --- a/src/mainboard/google/glados/variants/caroline/Makefile.inc +++ b/src/mainboard/google/glados/variants/caroline/Makefile.inc @@ -16,7 +16,7 @@ romstage-y += variant.c ramstage-y += variant.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += variant.c +smm-y += variant.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/glados/variants/cave/Makefile.inc b/src/mainboard/google/glados/variants/cave/Makefile.inc index 5d95e348af..f3b52c2398 100644 --- a/src/mainboard/google/glados/variants/cave/Makefile.inc +++ b/src/mainboard/google/glados/variants/cave/Makefile.inc @@ -16,7 +16,7 @@ romstage-y += variant.c ramstage-y += variant.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += variant.c +smm-y += variant.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/glados/variants/chell/Makefile.inc b/src/mainboard/google/glados/variants/chell/Makefile.inc index 2eff4b1f1d..986bdd8552 100644 --- a/src/mainboard/google/glados/variants/chell/Makefile.inc +++ b/src/mainboard/google/glados/variants/chell/Makefile.inc @@ -16,7 +16,7 @@ romstage-y += variant.c ramstage-y += variant.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += variant.c +smm-y += variant.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/glados/variants/glados/Makefile.inc b/src/mainboard/google/glados/variants/glados/Makefile.inc index 82dbcade42..b6dbbd4562 100644 --- a/src/mainboard/google/glados/variants/glados/Makefile.inc +++ b/src/mainboard/google/glados/variants/glados/Makefile.inc @@ -16,7 +16,7 @@ romstage-y += variant.c ramstage-y += variant.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += variant.c +smm-y += variant.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index 3f35f8266e..01a1eb85dd 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -24,7 +24,7 @@ romstage-y += romstage.c romstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index 116792fab7..9ea24f6aa0 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -19,7 +19,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += lan.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c +smm-y += smihandler.c led.c romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc index 770a999eca..0abd8840ec 100644 --- a/src/mainboard/google/kahlee/Makefile.inc +++ b/src/mainboard/google/kahlee/Makefile.inc @@ -29,7 +29,7 @@ ramstage-y += OemCustomize.c verstage-y += chromeos.c verstage-y += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index 89bb365023..e6c7be181c 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -19,7 +19,7 @@ romstage-y += chromeos.c ramstage-y += chromeos.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +smm-y += mainboard_smi.c SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! diff --git a/src/mainboard/google/octopus/Makefile.inc b/src/mainboard/google/octopus/Makefile.inc index 1a9adbcd8c..aa055246d2 100644 --- a/src/mainboard/google/octopus/Makefile.inc +++ b/src/mainboard/google/octopus/Makefile.inc @@ -8,7 +8,7 @@ ramstage-y += ec.c ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/poppy/Makefile.inc b/src/mainboard/google/poppy/Makefile.inc index 86754e62eb..030cf1da2d 100644 --- a/src/mainboard/google/poppy/Makefile.inc +++ b/src/mainboard/google/poppy/Makefile.inc @@ -25,7 +25,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c ramstage-y += ramstage.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c subdirs-y += variants/baseboard diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index 0033c60ee7..7c1e4808a6 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -35,7 +35,7 @@ ramstage-y += gpio.c ramstage-y += nhlt.c ramstage-y += mainboard.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c # Add OEM ID table cbfs-files-y += oem.bin diff --git a/src/mainboard/google/poppy/variants/nautilus/Makefile.inc b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc index c71520601a..3a36b83bda 100644 --- a/src/mainboard/google/poppy/variants/nautilus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc @@ -14,5 +14,5 @@ ramstage-y += nhlt.c ramstage-y += mainboard.c ramstage-y += sku.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += sku.c +smm-y += smihandler.c +smm-y += sku.c diff --git a/src/mainboard/google/poppy/variants/nocturne/Makefile.inc b/src/mainboard/google/poppy/variants/nocturne/Makefile.inc index 260d9c0bf3..371655a94e 100644 --- a/src/mainboard/google/poppy/variants/nocturne/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nocturne/Makefile.inc @@ -22,4 +22,4 @@ ramstage-y += nhlt.c ramstage-y += mainboard.c ramstage-y += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c +smm-y += ec.c diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index 7c0fb35abf..0e80b64252 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -19,7 +19,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += irqroute.c ramstage-y += w25q64.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +smm-y += mainboard_smi.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/google/reef/Makefile.inc b/src/mainboard/google/reef/Makefile.inc index 3701a91344..a115677773 100644 --- a/src/mainboard/google/reef/Makefile.inc +++ b/src/mainboard/google/reef/Makefile.inc @@ -8,7 +8,7 @@ ramstage-y += ec.c ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index 7c37bc9901..7e230447aa 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -20,7 +20,7 @@ ramstage-y += sku.c romstage-y += romstage.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 53e8dffd85..921f9e7585 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -18,7 +18,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index be1f0fe91f..f4f2284de4 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -18,8 +18,8 @@ ramstage-y += ec.c romstage-y += chromeos.c ramstage-y += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c +smm-y += mainboard_smi.c +smm-y += ec.c SRC_ROOT = $(src)/mainboard/google/stout romstage-y += gpio.c diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc index 80dd0d2785..f030989b36 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc +++ b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc @@ -22,4 +22,4 @@ ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c ramstage-y += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +smm-y += mainboard_smi.c diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index 06e86c1d6c..e34704d79d 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -17,4 +17,4 @@ romstage-y += chromeos.c ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +smm-y += mainboard_smi.c diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/Makefile.inc index c18fd9b34d..d98477118d 100644 --- a/src/mainboard/intel/cannonlake_rvp/Makefile.inc +++ b/src/mainboard/intel/cannonlake_rvp/Makefile.inc @@ -27,7 +27,7 @@ romstage-y += romstage_fsp_params.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc index 4d516f6204..96bac06a0a 100644 --- a/src/mainboard/intel/dcp847ske/Makefile.inc +++ b/src/mainboard/intel/dcp847ske/Makefile.inc @@ -1,4 +1,4 @@ romstage-y += early_southbridge.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c diff --git a/src/mainboard/intel/glkrvp/Makefile.inc b/src/mainboard/intel/glkrvp/Makefile.inc index f2da3794d5..ea5b2c65c6 100644 --- a/src/mainboard/intel/glkrvp/Makefile.inc +++ b/src/mainboard/intel/glkrvp/Makefile.inc @@ -10,7 +10,7 @@ ramstage-y += ec.c ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/kblrvp/Makefile.inc b/src/mainboard/intel/kblrvp/Makefile.inc index 6da41ae02f..ffed7a257d 100644 --- a/src/mainboard/intel/kblrvp/Makefile.inc +++ b/src/mainboard/intel/kblrvp/Makefile.inc @@ -33,7 +33,7 @@ ramstage-y += ramstage.c ramstage-y += hda_verb.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index 3330a0aab8..933074b4c5 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -28,7 +28,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c ramstage-y += ramstage.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs)) diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index e6f0c9e652..3f88b3d64e 100644 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -25,4 +25,4 @@ ramstage-y += irqroute.c ramstage-y += ramstage.c ramstage-y += w25q64.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/g505s/Makefile.inc b/src/mainboard/lenovo/g505s/Makefile.inc index 80dd0d2785..f030989b36 100644 --- a/src/mainboard/lenovo/g505s/Makefile.inc +++ b/src/mainboard/lenovo/g505s/Makefile.inc @@ -22,4 +22,4 @@ ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c ramstage-y += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +smm-y += mainboard_smi.c diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc index 2aa7f0f6c9..2ce116f90c 100644 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -15,6 +15,6 @@ romstage-y += romstage.c romstage-y += gpio.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/s230u/Makefile.inc b/src/mainboard/lenovo/s230u/Makefile.inc index dea2e4e582..88626a275a 100644 --- a/src/mainboard/lenovo/s230u/Makefile.inc +++ b/src/mainboard/lenovo/s230u/Makefile.inc @@ -1,6 +1,6 @@ romstage-y += gpio.c ramstage-y += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c # FIXME: SPD images for samsung_8gb and hynix_8gb are missing. # It's possible that no mainboards with that variation were manufactured. diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 2dab9507f1..30cf715194 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc index 2dab9507f1..30cf715194 100644 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ b/src/mainboard/lenovo/t420s/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t430/Makefile.inc b/src/mainboard/lenovo/t430/Makefile.inc index ada25f7136..558ab0a966 100644 --- a/src/mainboard/lenovo/t430/Makefile.inc +++ b/src/mainboard/lenovo/t430/Makefile.inc @@ -1,5 +1,5 @@ romstage-y += romstage.c romstage-y += gpio.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index d70c22e6e3..4008f5ab07 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index 7187013da4..ee4669c055 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc index 7187013da4..ee4669c055 100644 --- a/src/mainboard/lenovo/t530/Makefile.inc +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t60/Makefile.inc b/src/mainboard/lenovo/t60/Makefile.inc index 8473a13505..f646af8fd5 100644 --- a/src/mainboard/lenovo/t60/Makefile.inc +++ b/src/mainboard/lenovo/t60/Makefile.inc @@ -13,6 +13,6 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c +smm-y += dock.c romstage-y += dock.c romstage-y += gpio.c diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc index ee08d78642..63b41a49a2 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc @@ -15,7 +15,7 @@ subdirs-y += spd -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc index f7ff93b626..f97235612e 100644 --- a/src/mainboard/lenovo/x201/Makefile.inc +++ b/src/mainboard/lenovo/x201/Makefile.inc @@ -13,8 +13,8 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += dock.c +smm-y += smihandler.c romstage-y += dock.c ramstage-y += dock.c romstage-y += gpio.c diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index 2c52c21d33..a1cbc4cea5 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index 2dab9507f1..30cf715194 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x60/Makefile.inc b/src/mainboard/lenovo/x60/Makefile.inc index 4b17ea8e6c..a7ad539a1f 100644 --- a/src/mainboard/lenovo/x60/Makefile.inc +++ b/src/mainboard/lenovo/x60/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c +smm-y += dock.c romstage-y += dock.c ramstage-y += dock.c romstage-y += gpio.c diff --git a/src/mainboard/lenovo/z61t/Makefile.inc b/src/mainboard/lenovo/z61t/Makefile.inc index 8473a13505..f646af8fd5 100644 --- a/src/mainboard/lenovo/z61t/Makefile.inc +++ b/src/mainboard/lenovo/z61t/Makefile.inc @@ -13,6 +13,6 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c +smm-y += dock.c romstage-y += dock.c romstage-y += gpio.c diff --git a/src/mainboard/packardbell/ms2290/Makefile.inc b/src/mainboard/packardbell/ms2290/Makefile.inc index da1f50d115..b23d2e5560 100644 --- a/src/mainboard/packardbell/ms2290/Makefile.inc +++ b/src/mainboard/packardbell/ms2290/Makefile.inc @@ -13,6 +13,6 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/scaleway/tagada/Makefile.inc b/src/mainboard/scaleway/tagada/Makefile.inc index c33e993c30..8370c8aaac 100644 --- a/src/mainboard/scaleway/tagada/Makefile.inc +++ b/src/mainboard/scaleway/tagada/Makefile.inc @@ -26,6 +26,6 @@ bootblock-y += bmcinfo.c postcar-y += bmcinfo.c romstage-y += bmcinfo.c ramstage-y += bmcinfo.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += bmcinfo.c +smm-y += bmcinfo.c CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc index 410a308249..f9bf0507dc 100644 --- a/src/northbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/northbridge/intel/fsp_rangeley/Makefile.inc @@ -27,7 +27,7 @@ romstage-y += raminit.c romstage-y += ../../../arch/x86/walkcbfs.S romstage-y += port_access.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c +smm-y += udelay.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index 16a9ddb648..e74f475987 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -35,7 +35,7 @@ ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c +smm-y += ../../../cpu/x86/lapic/apic_timer.c postcar-y += ram_calc.c diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 7abbccacd2..ca1c04fa13 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -29,7 +29,7 @@ romstage-y += raminit.c romstage-y += early_init.c romstage-y += report_platform.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-y += finalize.c # We don't ship that, but booting without it is bound to fail cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index 6722621ba1..c0d46c9a0c 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -27,7 +27,7 @@ romstage-y += raminit.c romstage-y += early_init.c romstage-y += ../../../arch/x86/walkcbfs.S -smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-y += finalize.c postcar-y += ram_calc.c diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index c77f3bac6a..8a0b67b2c9 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -26,7 +26,7 @@ romstage-y += ram_calc.c ramstage-y += common.c romstage-y += common.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c +smm-y += common.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) romstage-y += early_dmi.c @@ -46,7 +46,7 @@ romstage-y += romstage.c romstage-y += early_init.c romstage-y += ../../../arch/x86/walkcbfs.S -smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-y += finalize.c postcar-y += ram_calc.c diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index e9d5022511..cfd814910e 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -71,10 +71,10 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += soc_util.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +smm-y += pmutil.c +smm-y += soc_util.c +smm-y += smihandler.c +smm-y += tsc_freq.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c smm-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index ca2b353b0f..2fbf34ecbb 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -33,10 +33,10 @@ romstage-y += memmap.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +smm-y += tsc_freq.c ramstage-y += spi.c romstage-y += spi.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += spi.c +smm-y += spi.c ramstage-y += chip.c ramstage-y += iosf.c romstage-y += iosf.c @@ -51,8 +51,8 @@ ramstage-y += cpu.c ramstage-y += acpi.c ramstage-y += lpe.c ramstage-y += lpss.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += pmutil.c +smm-y += smihandler.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index e8a31890ba..c73c12a430 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -31,9 +31,9 @@ ramstage-y += iou_complto.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c ramstage-y += vtd.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +smm-y += pmutil.c +smm-y += smihandler.c +smm-y += tsc_freq.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 5d3d5b4ad4..cd0a1d53e1 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -31,7 +31,7 @@ postcar-y += ramtop.c romstage-y += imc.c ramstage-y += imc.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c +smm-y += smihandler.c smi_util.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c # ROMSIG At ROMBASE + 0x20000: diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index c7cd757da2..c8949b055c 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -60,8 +60,8 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-$(CONFIG_HUDSON_UART) += uart.c ramstage-y += usb.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +smm-y += smihandler.c +smm-y += smi_util.c # ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index b6023b00b3..b23fa7a327 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -34,7 +34,7 @@ ramstage-y += me_status.c ramstage-$(CONFIG_ELOG) += elog.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c pch.c +smm-y += smihandler.c me.c me_8.x.c pch.c romstage-y += early_smbus.c me_status.c romstage-y += early_rcba.c diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index 5ba21309d6..ae0a10f96f 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -26,7 +26,7 @@ ramstage-y += usb2.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 6e7f9bf945..237c2d5f8e 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -32,7 +32,7 @@ ramstage-y += usb_ehci.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index caa493211c..0b9ade824e 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -33,7 +33,7 @@ ifneq ($(CONFIG_SMM_TSEG),y) ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S endif -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += early_init.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 6626bb5d33..02da8146e9 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -29,7 +29,7 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 3e3ef35e2d..e53ed8d826 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -42,8 +42,8 @@ ramstage-y += acpi.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c pch.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c +smm-y += smihandler.c me_9.x.c pch.c +smm-y += pmutil.c usb_ehci.c usb_xhci.c bootblock-y += early_pch.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c @@ -52,7 +52,7 @@ romstage-y += rcba.c pmutil.c ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) romstage-y += lp_gpio.c ramstage-y += lp_gpio.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += lp_gpio.c +smm-y += lp_gpio.c endif verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += pmutil.c From 60012ac64e4b1ecc0d9a1b6fd497020dfd70a31e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 8 Jul 2019 00:01:42 +0300 Subject: [PATCH 132/231] arch/x86: Replace some uses of SMM_TSEG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No reason why the files could not be used with ASEG. Attempts to use malloc() from ASEG would still fail, though, due the lack of heap. Change-Id: Idf470ae84eb34c442e833925510b08d5314e7638 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34126 Reviewed-by: Nico Huber Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/console/Makefile.inc | 4 ++-- src/lib/Makefile.inc | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 4f0c2ef613..3311849941 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -8,8 +8,8 @@ ramstage-$(CONFIG_RAMSTAGE_LIBHWBASE) += hw-debug_sink.adb endif smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c -smm-$(CONFIG_SMM_TSEG) += die.c -smm-$(CONFIG_SMM_TSEG) += post.c +smm-y += die.c +smm-y += post.c verstage-y += init.c verstage-y += printk.c diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index f6d3f6deb5..f0738eef4e 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -117,7 +117,6 @@ ramstage-y += fmap.c ramstage-y += memchr.c ramstage-y += memcmp.c ramstage-y += malloc.c -smm-$(CONFIG_SMM_TSEG) += malloc.c ramstage-y += dimm_info_util.c ramstage-y += delay.c ramstage-y += fallback_boot.c @@ -190,6 +189,7 @@ romstage-y += boot_device.c ramstage-y += boot_device.c smm-y += boot_device.c +smm-y += malloc.c smm-y += delay.c smm-y += fmap.c smm-y += cbfs.c memcmp.c From 8f076f2be8ed0671c226fed1403183e6ad9fb83e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 8 Jul 2019 09:16:13 +0300 Subject: [PATCH 133/231] soc/amd/stoneyridge,picasso: Switch SMM lock condition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SMM_TSEG is a qualifier between TSEG and ASEG memory region. ASEG is deprecated and not supported for this platform in coreboot codebase. The SMM lock should be set based on whether SMM is installed or not, HAVE_SMI_HANDLER currently tells that. Change-Id: I9756f8a59ccfedd59d5b997b35313452dd0c4f46 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34127 Reviewed-by: Richard Spiegel Reviewed-by: Marshall Dawson Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/finalize.c | 2 +- src/soc/amd/stoneyridge/finalize.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/picasso/finalize.c b/src/soc/amd/picasso/finalize.c index 6572e1a201..5a4627a432 100644 --- a/src/soc/amd/picasso/finalize.c +++ b/src/soc/amd/picasso/finalize.c @@ -29,7 +29,7 @@ static void per_core_finalize(void *unused) if (hwcr.lo & SMM_LOCK) /* Skip if already locked, avoid GPF */ return; - if (CONFIG(SMM_TSEG)) { + if (CONFIG(HAVE_SMI_HANDLER)) { mask = rdmsr(SMM_MASK_MSR); mask.lo |= SMM_TSEG_VALID; wrmsr(SMM_MASK_MSR, mask); diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 6572e1a201..5a4627a432 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -29,7 +29,7 @@ static void per_core_finalize(void *unused) if (hwcr.lo & SMM_LOCK) /* Skip if already locked, avoid GPF */ return; - if (CONFIG(SMM_TSEG)) { + if (CONFIG(HAVE_SMI_HANDLER)) { mask = rdmsr(SMM_MASK_MSR); mask.lo |= SMM_TSEG_VALID; wrmsr(SMM_MASK_MSR, mask); From 328d42f2d8e3b3eb9a451285a8d3e2f4c9fde029 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 8 Jul 2019 09:16:13 +0300 Subject: [PATCH 134/231] cpu/intel: Drop SMM_TSEG conditional MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SMM_TSEG is a qualifier between TSEG and ASEG memory region. ASEG is deprecated and not supported for these CPUs in coreboot codebase. Change-Id: I0602e04957a390473a2449e1c5ff951f9fdff73b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34133 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/cpu/intel/model_1067x/Makefile.inc | 2 +- src/cpu/intel/model_106cx/Makefile.inc | 2 +- src/cpu/intel/model_6ex/Makefile.inc | 2 +- src/cpu/intel/model_6fx/Makefile.inc | 2 +- src/cpu/intel/model_f3x/Makefile.inc | 2 +- src/cpu/intel/model_f4x/Makefile.inc | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc index caeab563a4..743e780a36 100644 --- a/src/cpu/intel/model_1067x/Makefile.inc +++ b/src/cpu/intel/model_1067x/Makefile.inc @@ -2,6 +2,6 @@ ramstage-y += model_1067x_init.c ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c subdirs-y += ../../x86/name subdirs-y += ../common -subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +subdirs-y += ../smm/gen1 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*) diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index a1f2d0d1f0..6701e6fc18 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,7 +1,7 @@ ramstage-y += model_106cx_init.c subdirs-y += ../../x86/name subdirs-y += ../common -subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +subdirs-y += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-1c-*) diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index cef2b0be86..e1491e6fb4 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -1,7 +1,7 @@ ramstage-y += model_6ex_init.c subdirs-y += ../../x86/name subdirs-y += ../common -subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +subdirs-y += ../smm/gen1 ramstage-y += ../model_1067x/mp_init.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0e-*) diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc index 9121e3b64a..f1d64b7454 100644 --- a/src/cpu/intel/model_6fx/Makefile.inc +++ b/src/cpu/intel/model_6fx/Makefile.inc @@ -2,6 +2,6 @@ ramstage-y += model_6fx_init.c subdirs-y += ../../x86/name subdirs-y += ../common ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c -subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +subdirs-y += ../smm/gen1 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*) diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index ed1eb5f7d8..1f2b564dac 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -1,5 +1,5 @@ ramstage-y += model_f3x_init.c -subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +subdirs-y += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-03-*) diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc index 196d63e462..7e853b07da 100644 --- a/src/cpu/intel/model_f4x/Makefile.inc +++ b/src/cpu/intel/model_f4x/Makefile.inc @@ -1,5 +1,5 @@ ramstage-y += model_f4x_init.c -subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +subdirs-y += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-04-*) From 4d372c7353727e9ffce9ec4e6b2de3cd6ab8e320 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 8 Jul 2019 13:48:57 +0300 Subject: [PATCH 135/231] cpu/x86: Declare SMM_ASEG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is really an inverse of SMM_TSEG to flag platforms that should potentially move away from ASEG implementation. Change-Id: I3b9007c55c75a59a9e6acc0a0e701300f7d21f87 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34134 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/Kconfig | 4 ---- src/cpu/amd/agesa/Kconfig | 1 + src/cpu/amd/pi/Kconfig | 1 + src/cpu/intel/model_f2x/Kconfig | 1 + src/cpu/qemu-x86/Kconfig | 1 + src/cpu/x86/Kconfig | 9 +++++++++ src/cpu/x86/smm/smmrelocate.S | 7 +++---- src/southbridge/intel/i82801dx/Makefile.inc | 3 +++ src/southbridge/intel/i82801ix/Makefile.inc | 2 +- 9 files changed, 20 insertions(+), 9 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 778f1694b6..38209ee6e1 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -543,10 +543,6 @@ config HAVE_OPTION_TABLE file containing NVRAM/CMOS bit definitions. It defaults to 'n' but can be selected in mainboard/*/Kconfig. -config HAVE_SMI_HANDLER - bool - default n - config PCI_IO_CFG_EXT bool default n diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 5f7e0f9987..4c5463cc8a 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -30,6 +30,7 @@ config CPU_AMD_AGESA select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select POSTCAR_STAGE + select SMM_ASEG if CPU_AMD_AGESA diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 8dc7f5abf9..a902089099 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -29,6 +29,7 @@ config CPU_AMD_PI select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select POSTCAR_STAGE if !BINARYPI_LEGACY_WRAPPER + select SMM_ASEG if CPU_AMD_PI diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 5ef1539995..9e70775650 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -6,3 +6,4 @@ config CPU_INTEL_MODEL_F2X select ARCH_RAMSTAGE_X86_32 select SMP select SUPPORT_CPU_UCODE_IN_CBFS + select SMM_ASEG diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 70cce9b705..0473e2f7f0 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -22,3 +22,4 @@ config CPU_QEMU_X86 select SMP select UDELAY_TSC select C_ENVIRONMENT_BOOTBLOCK + select SMM_ASEG diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 99a70750af..d230a57e3f 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -88,6 +88,15 @@ config LOGICAL_CPUS bool default y +config HAVE_SMI_HANDLER + bool + default n + depends on (SMM_ASEG || SMM_TSEG) + +config SMM_ASEG + bool + default n + config SMM_TSEG bool default n diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index c282904de9..e23b082aa7 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -32,10 +32,9 @@ // ADDR32() macro #include -#if CONFIG(SMM_TSEG) -#error "Don't use this file with TSEG." - -#endif /* CONFIG_SMM_TSEG */ +#if !CONFIG(SMM_ASEG) +#error "Only use this file with ASEG." +#endif /* CONFIG_SMM_ASEG */ #define LAPIC_ID 0xfee00020 diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index ae0a10f96f..a8931fffc1 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -24,8 +24,11 @@ ramstage-y += lpc.c ramstage-y += usb.c ramstage-y += usb2.c +ifeq ($(CONFIG_SMM_ASEG),y) ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S +endif + smm-y += smihandler.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 0b9ade824e..49db1230b7 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -29,7 +29,7 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -ifneq ($(CONFIG_SMM_TSEG),y) +ifeq ($(CONFIG_SMM_ASEG),y) ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S endif From 8abf66e4e06412db08918dcde31f2d515040a409 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 8 Jul 2019 09:56:00 +0300 Subject: [PATCH 136/231] cpu/x86: Flip SMM_TSEG default MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is only a qualifier between TSEG and ASEG. Change-Id: I8051df92d9014e3574f6e7d5b6f1d6677fe77c82 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34135 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/cpu/intel/fsp_model_406dx/Kconfig | 1 + src/cpu/intel/haswell/Kconfig | 1 - src/cpu/intel/model_2065x/Kconfig | 1 - src/cpu/intel/model_206ax/Kconfig | 1 - src/cpu/intel/slot_1/Kconfig | 1 + src/cpu/x86/Kconfig | 17 ++++++++++++----- src/northbridge/intel/gm45/Kconfig | 1 - src/northbridge/intel/i945/Kconfig | 1 - src/northbridge/intel/pineview/Kconfig | 1 - src/northbridge/intel/x4x/Kconfig | 1 - src/soc/amd/picasso/Kconfig | 1 - src/soc/amd/stoneyridge/Kconfig | 1 - src/soc/intel/apollolake/Kconfig | 1 - src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/cannonlake/Kconfig | 1 - src/soc/intel/denverton_ns/Kconfig | 1 - src/soc/intel/fsp_baytrail/Kconfig | 1 - src/soc/intel/fsp_broadwell_de/Kconfig | 1 - src/soc/intel/icelake/Kconfig | 1 - src/soc/intel/skylake/Kconfig | 1 - 22 files changed, 14 insertions(+), 24 deletions(-) diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index f40842fce8..6bf8dc7eec 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -35,6 +35,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER select CPU_INTEL_COMMON + select NO_SMM # Microcode header files are delivered in FSP package select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 5936953b52..9cc040ec62 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -16,7 +16,6 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_TSC select TSC_CONSTANT_RATE - select SMM_TSEG select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 0af0d35dda..089b3fead0 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER - select SMM_TSEG select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index dbb8982121..2af63d6079 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -15,7 +15,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER - select SMM_TSEG select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index ab6663258f..890e33bbf8 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -25,6 +25,7 @@ config SLOT_SPECIFIC_OPTIONS # dummy select CPU_INTEL_MODEL_68X select CPU_INTEL_MODEL_6BX select CPU_INTEL_MODEL_6XX + select NO_SMM config DCACHE_RAM_BASE hex diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index d230a57e3f..8cc493ed55 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -93,18 +93,25 @@ config HAVE_SMI_HANDLER default n depends on (SMM_ASEG || SMM_TSEG) -config SMM_ASEG +config NO_SMM bool default n -config SMM_TSEG +config SMM_ASEG bool default n + depends on !NO_SMM + +config SMM_TSEG + bool + default y + depends on !(NO_SMM || SMM_ASEG) + +if SMM_TSEG config SMM_MODULE_HEAP_SIZE hex default 0x4000 - depends on SMM_TSEG help This option determines the size of the heap within the SMM handler modules. @@ -112,7 +119,6 @@ config SMM_MODULE_HEAP_SIZE config SMM_MODULE_STACK_SIZE hex default 0x400 - depends on SMM_TSEG help This option determines the size of the stack within the SMM handler modules. @@ -120,11 +126,12 @@ config SMM_MODULE_STACK_SIZE config SMM_STUB_STACK_SIZE hex default 0x400 - depends on SMM_TSEG help This option determines the size of the stack within the SMM handler modules. +endif + config SMM_LAPIC_REMAP_MITIGATION bool default y if NORTHBRIDGE_INTEL_I945 diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index f1318ebc93..c3d24820a5 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -28,7 +28,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_GMA_SSC_ALTERNATE_REF select POSTCAR_STAGE select POSTCAR_CONSOLE - select SMM_TSEG select PARALLEL_MP select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 93251965c1..b151e8fb92 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -29,7 +29,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select POSTCAR_STAGE select POSTCAR_CONSOLE - select SMM_TSEG select PARALLEL_MP select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 2b4f502c61..37959dd2e6 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -30,7 +30,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_GMA_ACPI select POSTCAR_STAGE select POSTCAR_CONSOLE - select SMM_TSEG select PARALLEL_MP select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 7cae91e324..ce43936c37 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -28,7 +28,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select CACHE_MRC_SETTINGS select POSTCAR_STAGE select POSTCAR_CONSOLE - select SMM_TSEG select PARALLEL_MP select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index a930f60d27..048193e8c7 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -57,7 +57,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER - select SMM_TSEG select POSTCAR_STAGE select POSTCAR_CONSOLE select SSE2 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index ba82565bf4..f730cb2e1c 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -65,7 +65,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER - select SMM_TSEG select POSTCAR_STAGE select POSTCAR_CONSOLE select SSE2 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 1f819eab06..4cddb586ed 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -63,7 +63,6 @@ config CPU_SPECIFIC_OPTIONS select PMC_INVALID_READ_AFTER_WRITE select PMC_GLOBAL_RESET_ENABLE_LOCK select REG_SCRIPT - select SMM_TSEG select SA_ENABLE_IMR select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 43c2906f15..4b816a20b6 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -24,7 +24,6 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_COMMON_CLOCK select REG_SCRIPT select RTC - select SMM_TSEG select SMP select SPI_FLASH select SSE2 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 920179f834..61bedb426e 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -34,7 +34,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_RESET - select SMM_TSEG select SMP select SPI_FLASH select SSE2 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 801800c5f4..3f7aef5e79 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -26,7 +26,6 @@ config CPU_SPECIFIC_OPTIONS select REG_SCRIPT select PARALLEL_MP select RTC - select SMM_TSEG select SMP select SPI_FLASH select SSE2 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5e405db4d8..48e5f6b83b 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -80,7 +80,6 @@ config CPU_SPECIFIC_OPTIONS select POSTCAR_CONSOLE select POSTCAR_STAGE select REG_SCRIPT - select SMM_TSEG select SMP select SOC_AHCI_PORT_IMPLEMENTED_INVERT select PMC_GLOBAL_RESET_ENABLE_LOCK diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 273ce30d66..c230337449 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -37,7 +37,6 @@ config CPU_SPECIFIC_OPTIONS select C_ENVIRONMENT_BOOTBLOCK select IOAPIC select HAVE_SMI_HANDLER - select SMM_TSEG select CACHE_MRC_SETTINGS select PARALLEL_MP select PCR_COMMON_IOSF_1_0 diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 26c95483c0..072df295a5 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -33,7 +33,6 @@ config CPU_SPECIFIC_OPTIONS select NO_RELOCATABLE_RAMSTAGE select PARALLEL_MP select REG_SCRIPT - select SMM_TSEG select SMP select SPI_FLASH select SSE2 diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index f71148f6fe..0af2aad228 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -21,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE - select SMM_TSEG select HAVE_SMI_HANDLER select TSC_MONOTONIC_TIMER select TSC_CONSTANT_RATE diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index f0b291877d..db0f110cb7 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -37,7 +37,6 @@ config CPU_SPECIFIC_OPTIONS select POSTCAR_CONSOLE select POSTCAR_STAGE select REG_SCRIPT - select SMM_TSEG select SMP select SOC_AHCI_PORT_IMPLEMENTED_INVERT select PMC_GLOBAL_RESET_ENABLE_LOCK diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index fb455d2392..ca690f41e8 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -50,7 +50,6 @@ config CPU_SPECIFIC_OPTIONS select PCIEX_LENGTH_64MB select REG_SCRIPT select SA_ENABLE_DPR - select SMM_TSEG select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON From 517546aaabbbcea0a8a89a249bb85a6e732a1cbc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 7 Jul 2019 08:42:19 +0300 Subject: [PATCH 137/231] emulation/qemu-power8: Select CPU_QEMU_POWER8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I5fa6486e96cd81767225a3e1015341c0c89053d1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34115 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/emulation/qemu-power8/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/emulation/qemu-power8/Kconfig b/src/mainboard/emulation/qemu-power8/Kconfig index 66a3d8c25f..c3a9904986 100644 --- a/src/mainboard/emulation/qemu-power8/Kconfig +++ b/src/mainboard/emulation/qemu-power8/Kconfig @@ -19,6 +19,7 @@ if BOARD_EMULATION_QEMU_POWER8 config BOARD_SPECIFIC_OPTIONS def_bool y + select CPU_QEMU_POWER8 select BOARD_ROMSIZE_KB_4096 select ARCH_BOOTBLOCK_PPC64 select HAVE_UART_SPECIAL From c6b152a976e02b1693a2f8239b11675e80acf541 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 8 Jul 2019 09:47:02 +0200 Subject: [PATCH 138/231] libpayload/usb: fix DWC2 driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A typo introduced in commit bf2c693f893ab6f9458f1a4840c2a9cbbd4bb9f2 made the driver not build: DWC_SLEEP_TIME_US instead of DWC2_SLEEP_TIME_US. Change-Id: I197b25fd4f568cce7a4bbcee8cc285b25b26afb1 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/34131 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Keith Short Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- payloads/libpayload/drivers/usb/dwc2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c index 06c54e1030..963ae84762 100644 --- a/payloads/libpayload/drivers/usb/dwc2.c +++ b/payloads/libpayload/drivers/usb/dwc2.c @@ -159,14 +159,14 @@ wait_for_complete(endpoint_t *ep, uint32_t ch_num) hcchar_t hcchar; hctsiz_t hctsiz; dwc2_reg_t *reg = DWC2_REG(ep->dev->controller); - int timeout = USB_MAX_PROCESSING_TIME_US / DWC_SLEEP_TIME_US; + int timeout = USB_MAX_PROCESSING_TIME_US / DWC2_SLEEP_TIME_US; /* * TODO: We should take care of up to three times of transfer error * retry here, according to the USB 2.0 spec 4.5.2 */ do { - udelay(DWC_SLEEP_TIME_US); + udelay(DWC2_SLEEP_TIME_US); hcint.d32 = readl(®->host.hchn[ch_num].hcintn); hctsiz.d32 = readl(®->host.hchn[ch_num].hctsizn); From 76c43866990bf61c35b1fb6f6915614eebc8d4a4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 1 Jul 2019 17:25:41 +0300 Subject: [PATCH 139/231] arch/non-x86: Flip HAVE_MONOTONIC_TIMER default MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Also remove allwinner/a10 dummy monotonic_timer implementation. Change-Id: I9dfa9b92dc63375465e3bb87b73eeefad601c810 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34112 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/Kconfig | 10 +++++++-- src/cpu/allwinner/a10/Kconfig | 2 +- src/cpu/allwinner/a10/Makefile.inc | 1 - src/cpu/allwinner/a10/monotonic_timer.c | 25 ---------------------- src/cpu/qemu-power8/Kconfig | 1 + src/cpu/ti/am335x/Kconfig | 2 -- src/mainboard/emulation/qemu-armv7/Kconfig | 1 + src/soc/cavium/cn81xx/Kconfig | 2 -- src/soc/imgtec/pistachio/Kconfig | 2 -- src/soc/mediatek/mt8173/Kconfig | 2 -- src/soc/mediatek/mt8183/Kconfig | 2 -- src/soc/nvidia/tegra124/Kconfig | 2 -- src/soc/nvidia/tegra210/Kconfig | 2 -- src/soc/qualcomm/ipq40xx/Kconfig | 4 +++- src/soc/qualcomm/ipq806x/Kconfig | 1 + src/soc/qualcomm/qcs405/Kconfig | 2 -- src/soc/qualcomm/sdm845/Kconfig | 2 -- src/soc/rockchip/rk3288/Kconfig | 2 -- src/soc/rockchip/rk3399/Kconfig | 2 -- src/soc/samsung/exynos5250/Kconfig | 2 -- src/soc/samsung/exynos5420/Kconfig | 2 -- src/soc/sifive/fu540/Kconfig | 2 -- src/soc/ucb/riscv/Kconfig | 2 -- 23 files changed, 15 insertions(+), 60 deletions(-) delete mode 100644 src/cpu/allwinner/a10/monotonic_timer.c diff --git a/src/Kconfig b/src/Kconfig index 38209ee6e1..f79a3904af 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -501,14 +501,20 @@ config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK bool default n -config HAVE_MONOTONIC_TIMER +config NO_MONOTONIC_TIMER def_bool n + +config HAVE_MONOTONIC_TIMER + bool + depends on !NO_MONOTONIC_TIMER + default y if !ARCH_X86 help The board/chipset provides a monotonic timer. config GENERIC_UDELAY - def_bool n + bool depends on HAVE_MONOTONIC_TIMER + default y if !ARCH_X86 help The board/chipset uses a generic udelay function utilizing the monotonic timer. diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 87693ed600..0b5d9bf60d 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -10,7 +10,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 - select HAVE_MONOTONIC_TIMER + select NO_MONOTONIC_TIMER select HAVE_UART_SPECIAL select UART_OVERRIDE_REFCLK select BOOT_DEVICE_NOT_SPI_FLASH diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index a6cd4b48a7..cbdb5ae856 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -17,7 +17,6 @@ ramstage-y += bootblock_media.c ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += cpu.c -ramstage-y += monotonic_timer.c ramstage-y += timer.c ramstage-y += twi.c diff --git a/src/cpu/allwinner/a10/monotonic_timer.c b/src/cpu/allwinner/a10/monotonic_timer.c deleted file mode 100644 index 479dee9471..0000000000 --- a/src/cpu/allwinner/a10/monotonic_timer.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Alexandru Gagniuc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the Licenseor (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Placeholder for code to come (needed to complete build) - * - */ - -#include - -void timer_monotonic_get(struct mono_time *mt) -{ - (void)mt; -} diff --git a/src/cpu/qemu-power8/Kconfig b/src/cpu/qemu-power8/Kconfig index c1f8309795..ef995b6398 100644 --- a/src/cpu/qemu-power8/Kconfig +++ b/src/cpu/qemu-power8/Kconfig @@ -19,3 +19,4 @@ config CPU_QEMU_POWER8 select ARCH_VERSTAGE_PPC64 select ARCH_ROMSTAGE_PPC64 select ARCH_RAMSTAGE_PPC64 + select NO_MONOTONIC_TIMER diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index 20e7458baf..6de5eb4df3 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -3,9 +3,7 @@ config CPU_TI_AM335X select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 - select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select GENERIC_UDELAY select UART_OVERRIDE_REFCLK select BOOT_DEVICE_NOT_SPI_FLASH bool diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 0bb5f3abc5..fc770cf27d 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -35,6 +35,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_4096 select BOOT_DEVICE_NOT_SPI_FLASH select MISSING_BOARD_RESET + select NO_MONOTONIC_TIMER config MAINBOARD_DIR string diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index 9119bcc152..f64350eb9e 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -6,8 +6,6 @@ config SOC_CAVIUM_CN81XX select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 select DRIVERS_UART_PL011 - select GENERIC_UDELAY - select HAVE_MONOTONIC_TIMER select UART_OVERRIDE_REFCLK select SOC_CAVIUM_COMMON select CAVIUM_BDK_DDR_TUNE_HW_OFFSETS diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 40b63c3d5a..30d7bee2c0 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -20,8 +20,6 @@ config CPU_IMGTEC_PISTACHIO select ARCH_VERSTAGE_MIPS select ARCH_ROMSTAGE_MIPS select ARCH_RAMSTAGE_MIPS - select GENERIC_UDELAY - select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select GENERIC_GPIO_LIB select UART_OVERRIDE_REFCLK diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index e966b8e58b..6476d42b0a 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -8,8 +8,6 @@ config SOC_MEDIATEK_MT8173 select ARCH_VERSTAGE_ARMV8_64 select ARM64_USE_ARM_TRUSTED_FIRMWARE select HAVE_UART_SPECIAL - select HAVE_MONOTONIC_TIMER - select GENERIC_UDELAY select GENERIC_GPIO_LIB select RTC diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index f96282cf62..c60cdea38d 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -6,9 +6,7 @@ config SOC_MEDIATEK_MT8183 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 select ARM64_USE_ARM_TRUSTED_FIRMWARE - select GENERIC_UDELAY select HAVE_UART_SPECIAL - select HAVE_MONOTONIC_TIMER select COMPRESS_BOOTBLOCK if SOC_MEDIATEK_MT8183 diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 475d50e210..c962aead71 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -7,8 +7,6 @@ config SOC_NVIDIA_TEGRA124 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL - select HAVE_MONOTONIC_TIMER - select GENERIC_UDELAY select ARM_LPAE select GENERIC_GPIO_LIB select MAINBOARD_HAS_NATIVE_VGA_INIT diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 6750aa9f9a..0e1efd7050 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -7,8 +7,6 @@ config SOC_NVIDIA_TEGRA210 select ARCH_ROMSTAGE_ARMV4 select ARCH_RAMSTAGE_ARMV8_64 select GIC - select HAVE_MONOTONIC_TIMER - select GENERIC_UDELAY select HAVE_UART_SPECIAL select ARM64_USE_ARM_TRUSTED_FIRMWARE select GENERIC_GPIO_LIB diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index 90744d5285..ef80772b2f 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -7,10 +7,12 @@ config SOC_QC_IPQ40XX select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL select GENERIC_GPIO_LIB - select HAVE_MONOTONIC_TIMER if SOC_QC_IPQ40XX +config GENERIC_UDELAY + def_bool n + config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 0b112d952d..fa0fefef67 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -7,6 +7,7 @@ config SOC_QC_IPQ806X select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL select GENERIC_GPIO_LIB + select NO_MONOTONIC_TIMER if SOC_QC_IPQ806X diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index aa867c2f25..48e2fd4e4d 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -8,8 +8,6 @@ config SOC_QUALCOMM_QCS405 select ARCH_VERSTAGE_ARMV8_64 select BOOTBLOCK_CONSOLE select GENERIC_GPIO_LIB - select GENERIC_UDELAY - select HAVE_MONOTONIC_TIMER select ARM64_USE_ARCH_TIMER select HAVE_UART_SPECIAL diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig index 459a4411b2..dbe025e93a 100644 --- a/src/soc/qualcomm/sdm845/Kconfig +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -7,8 +7,6 @@ config SOC_QUALCOMM_SDM845 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 select GENERIC_GPIO_LIB - select GENERIC_UDELAY - select HAVE_MONOTONIC_TIMER select ARM64_USE_ARCH_TIMER select SOC_QUALCOMM_COMMON diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index f845f07514..3aebab9754 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -21,8 +21,6 @@ config SOC_ROCKCHIP_RK3288 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 select DRIVERS_UART_8250MEM_32 - select HAVE_MONOTONIC_TIMER - select GENERIC_UDELAY select UNCOMPRESSED_RAMSTAGE select GENERIC_GPIO_LIB select RTC diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig index 83fc437073..7e3c44b674 100644 --- a/src/soc/rockchip/rk3399/Kconfig +++ b/src/soc/rockchip/rk3399/Kconfig @@ -8,8 +8,6 @@ config SOC_ROCKCHIP_RK3399 select ARM64_USE_ARM_TRUSTED_FIRMWARE select DRIVERS_UART_8250MEM_32 select GENERIC_GPIO_LIB - select GENERIC_UDELAY - select HAVE_MONOTONIC_TIMER select UART_OVERRIDE_REFCLK select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select COMPRESS_BOOTBLOCK diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 5b3972427f..680bd66cb7 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -3,8 +3,6 @@ config CPU_SAMSUNG_EXYNOS5250 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 - select HAVE_MONOTONIC_TIMER - select GENERIC_UDELAY select HAVE_UART_SPECIAL bool default n diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index 7b87650fa9..3af8e64ac3 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -3,8 +3,6 @@ config CPU_SAMSUNG_EXYNOS5420 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 - select HAVE_MONOTONIC_TIMER - select GENERIC_UDELAY select HAVE_UART_SPECIAL select RELOCATABLE_MODULES select NO_BOOTBLOCK_CONSOLE diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 6ebde33da0..82b42e5559 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -22,8 +22,6 @@ config SOC_SIFIVE_FU540 select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV select DRIVERS_UART_SIFIVE - select GENERIC_UDELAY - select HAVE_MONOTONIC_TIMER select RISCV_USE_ARCH_TIMER select UART_OVERRIDE_REFCLK diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index ad48c1cb76..324a0fb840 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -6,8 +6,6 @@ config SOC_UCB_RISCV select ARCH_VERSTAGE_RISCV select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV - select GENERIC_UDELAY - select HAVE_MONOTONIC_TIMER select RISCV_USE_ARCH_TIMER bool default n From b28b6b53cc51fef83eb290e746c91afcddc6eb49 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 1 Jul 2019 15:38:25 +0300 Subject: [PATCH 140/231] arch/x86: Flip HAVE_MONOTONIC_TIMER default MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Id56139a3d0840684b13179821a77bc8ae28e05ae Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34113 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/Kconfig | 2 +- src/cpu/amd/family_10h-family_15h/Kconfig | 1 - src/cpu/intel/haswell/Kconfig | 1 - src/cpu/intel/slot_1/Kconfig | 1 + src/cpu/qemu-x86/Kconfig | 1 + src/cpu/via/nano/Kconfig | 1 + src/cpu/x86/Kconfig | 2 -- src/soc/amd/picasso/Kconfig | 1 - src/soc/amd/stoneyridge/Kconfig | 1 - src/soc/intel/apollolake/Kconfig | 1 - src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/cannonlake/Kconfig | 1 - src/soc/intel/icelake/Kconfig | 1 - src/soc/intel/quark/Kconfig | 1 - src/soc/intel/skylake/Kconfig | 1 - 16 files changed, 4 insertions(+), 14 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index f79a3904af..b64fdca4ee 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -507,7 +507,7 @@ config NO_MONOTONIC_TIMER config HAVE_MONOTONIC_TIMER bool depends on !NO_MONOTONIC_TIMER - default y if !ARCH_X86 + default y help The board/chipset provides a monotonic timer. diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index 8ff685f0c1..df6549987e 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -7,7 +7,6 @@ config CPU_AMD_MODEL_10XXX select SSE2 select TSC_SYNC_LFENCE select UDELAY_LAPIC - select HAVE_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES select ACPI_HUGE_LOWMEM_BACKUP diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 9cc040ec62..cb8bc77335 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -10,7 +10,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select HAVE_MONOTONIC_TIMER select SMP select MMX select SSE2 diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 890e33bbf8..adfc2da75a 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -26,6 +26,7 @@ config SLOT_SPECIFIC_OPTIONS # dummy select CPU_INTEL_MODEL_6BX select CPU_INTEL_MODEL_6XX select NO_SMM + select NO_MONOTONIC_TIMER config DCACHE_RAM_BASE hex diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 0473e2f7f0..141749eca4 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -21,5 +21,6 @@ config CPU_QEMU_X86 select ARCH_RAMSTAGE_X86_32 select SMP select UDELAY_TSC + select NO_MONOTONIC_TIMER select C_ENVIRONMENT_BOOTBLOCK select SMM_ASEG diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig index c7e7060957..de1c2155e5 100644 --- a/src/cpu/via/nano/Kconfig +++ b/src/cpu/via/nano/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select UDELAY_TSC + select NO_MONOTONIC_TIMER select MMX select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 8cc493ed55..caee5dbd10 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -24,7 +24,6 @@ config UDELAY_LAPIC config LAPIC_MONOTONIC_TIMER def_bool n depends on UDELAY_LAPIC - select HAVE_MONOTONIC_TIMER help Expose monotonic time using the local APIC. @@ -45,7 +44,6 @@ config TSC_CONSTANT_RATE config TSC_MONOTONIC_TIMER def_bool n depends on UDELAY_TSC - select HAVE_MONOTONIC_TIMER help Expose monotonic time using the TSC. diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 048193e8c7..d654e9494e 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -34,7 +34,6 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_UDELAY select IOAPIC select HAVE_USBDEBUG_OPTIONS - select HAVE_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select TSC_SYNC_LFENCE select COLLECT_TIMESTAMPS diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index f730cb2e1c..78b89e3025 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -39,7 +39,6 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_UDELAY select IOAPIC select HAVE_USBDEBUG_OPTIONS - select HAVE_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select TSC_SYNC_LFENCE select COLLECT_TIMESTAMPS diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4cddb586ed..cf3d2446b4 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -101,7 +101,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER - select HAVE_MONOTONIC_TIMER select PLATFORM_USES_FSP2_0 select UDK_2015_BINDING if !SOC_INTEL_GLK select UDK_2017_BINDING if SOC_INTEL_GLK diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 61bedb426e..7887156716 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_IN_BLOB_REPO select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED - select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 3f7aef5e79..bf6b78c222 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -18,7 +18,6 @@ config CPU_SPECIFIC_OPTIONS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS - select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET select HAVE_USBDEBUG diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 48e5f6b83b..fed7f02dc6 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -66,7 +66,6 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE - select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_GMA_ACPI diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index db0f110cb7..a2261a0457 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -23,7 +23,6 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE - select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_GMA_ACPI diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 2a0c13297e..4aa641cc70 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -27,7 +27,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select C_ENVIRONMENT_BOOTBLOCK - select HAVE_MONOTONIC_TIMER select NO_MMCONF_SUPPORT select REG_SCRIPT select SOC_INTEL_COMMON diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index ca690f41e8..f36d5ca0f3 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -38,7 +38,6 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE - select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI From 8261d67ae705d6a29edd8bbe52a2b1aa72ae53d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 4 Jul 2019 06:12:55 +0300 Subject: [PATCH 141/231] device/oprom: Reduce indentation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Iadae9221f7ea549e91cdc501155de058c51a982c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34081 Tested-by: build bot (Jenkins) Reviewed-by: Mike Banon --- src/device/oprom/yabel/io.c | 195 +++++++++++++++++++----------------- 1 file changed, 101 insertions(+), 94 deletions(-) diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index 7117a6eed4..2b384ea7b4 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -410,66 +410,69 @@ my_outl(X86EMU_pioAddr addr, u32 val) u32 pci_cfg_read(X86EMU_pioAddr addr, u8 size) { + u32 port_cf8_val = 0; u32 rval = 0xFFFFFFFF; - struct device * dev; - if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) { - // PCI Configuration Mechanism 1 step 1 - // write to 0xCF8, sets bus, device, function and Config Space offset - // later read from 0xCFC-0xCFF returns the value... - u8 bus, devfn, offs; - u32 port_cf8_val = my_inl(0xCF8); - if ((port_cf8_val & 0x80000000) != 0) { - //highest bit enables config space mapping - bus = (port_cf8_val & 0x00FF0000) >> 16; - devfn = (port_cf8_val & 0x0000FF00) >> 8; - offs = (port_cf8_val & 0x000000FF); - offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly - DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", - __func__, bus, devfn, offs); + struct device *dev = NULL; + u8 bus, devfn, offs; + + // PCI Configuration Mechanism 1 step 1 + // write to 0xCF8, sets bus, device, function and Config Space offset + // later read from 0xCFC-0xCFF returns the value... + if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) + port_cf8_val = my_inl(0xCF8); + + if ((port_cf8_val & 0x80000000) == 0) + return rval; + + //highest bit enables config space mapping + bus = (port_cf8_val & 0x00FF0000) >> 16; + devfn = (port_cf8_val & 0x0000FF00) >> 8; + offs = (port_cf8_val & 0x000000FF); + offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly + DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", + __func__, bus, devfn, offs); #if CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES) - dev = dev_find_slot(bus, devfn); - DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", - __func__, dev_path(dev)); - if (dev == 0) { - // fail accesses to non-existent devices... + dev = dev_find_slot(bus, devfn); + DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", + __func__, dev_path(dev)); + if (dev == 0) { + // fail accesses to non-existent devices... #else - dev = bios_device.dev; - if ((bus != bios_device.bus) - || (devfn != bios_device.devfn)) { - // fail accesses to any device but ours... + dev = bios_device.dev; + if ((bus != bios_device.bus) + || (devfn != bios_device.devfn)) { + // fail accesses to any device but ours... #endif - printf - ("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n", - __func__, bus, bios_device.bus, devfn, - bios_device.devfn, offs); - SET_FLAG(F_CF); - HALT_SYS(); - return 0; - } else { + printf + ("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n", + __func__, bus, bios_device.bus, devfn, + bios_device.devfn, offs); + SET_FLAG(F_CF); + HALT_SYS(); + return 0; + } else { #if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - switch (size) { - case 1: - rval = pci_read_config8(dev, offs); - break; - case 2: - rval = pci_read_config16(dev, offs); - break; - case 4: - rval = pci_read_config32(dev, offs); - break; - } -#else - rval = - (u32) rtas_pci_config_read(bios_device. - puid, size, - bus, devfn, - offs); -#endif - DEBUG_PRINTF_IO - ("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n", - __func__, addr, offs, size, rval); - } + switch (size) { + case 1: + rval = pci_read_config8(dev, offs); + break; + case 2: + rval = pci_read_config16(dev, offs); + break; + case 4: + rval = pci_read_config32(dev, offs); + break; } +#else + rval = + (u32) rtas_pci_config_read(bios_device. + puid, size, + bus, devfn, + offs); +#endif + DEBUG_PRINTF_IO + ("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n", + __func__, addr, offs, size, rval); } return rval; } @@ -477,50 +480,54 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size) void pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size) { - if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) { - // PCI Configuration Mechanism 1 step 1 - // write to 0xCF8, sets bus, device, function and Config Space offset - // later write to 0xCFC-0xCFF sets the value... - u8 bus, devfn, offs; - u32 port_cf8_val = my_inl(0xCF8); - if ((port_cf8_val & 0x80000000) != 0) { - //highest bit enables config space mapping - bus = (port_cf8_val & 0x00FF0000) >> 16; - devfn = (port_cf8_val & 0x0000FF00) >> 8; - offs = (port_cf8_val & 0x000000FF); - offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly - if ((bus != bios_device.bus) - || (devfn != bios_device.devfn)) { - // fail accesses to any device but ours... - printf - ("Config write access invalid! PCI device %x:%x.%x, offs: %x\n", - bus, devfn >> 3, devfn & 7, offs); + u32 port_cf8_val = 0; + u8 bus, devfn, offs; + + // PCI Configuration Mechanism 1 step 1 + // write to 0xCF8, sets bus, device, function and Config Space offset + // later write to 0xCFC-0xCFF sets the value... + + if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) + port_cf8_val = my_inl(0xCF8); + + if ((port_cf8_val & 0x80000000) == 0) + return; + + //highest bit enables config space mapping + bus = (port_cf8_val & 0x00FF0000) >> 16; + devfn = (port_cf8_val & 0x0000FF00) >> 8; + offs = (port_cf8_val & 0x000000FF); + offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly + if ((bus != bios_device.bus) + || (devfn != bios_device.devfn)) { + // fail accesses to any device but ours... + printf + ("Config write access invalid! PCI device %x:%x.%x, offs: %x\n", + bus, devfn >> 3, devfn & 7, offs); #if !CONFIG(YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG) - HALT_SYS(); + HALT_SYS(); #endif - } else { + } else { #if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - switch (size) { - case 1: - pci_write_config8(bios_device.dev, offs, val); - break; - case 2: - pci_write_config16(bios_device.dev, offs, val); - break; - case 4: - pci_write_config32(bios_device.dev, offs, val); - break; - } -#else - rtas_pci_config_write(bios_device.puid, - size, bus, devfn, offs, - val); -#endif - DEBUG_PRINTF_IO - ("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n", - __func__, addr, offs, size, val); - } + switch (size) { + case 1: + pci_write_config8(bios_device.dev, offs, val); + break; + case 2: + pci_write_config16(bios_device.dev, offs, val); + break; + case 4: + pci_write_config32(bios_device.dev, offs, val); + break; } +#else + rtas_pci_config_write(bios_device.puid, + size, bus, devfn, offs, + val); +#endif + DEBUG_PRINTF_IO + ("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n", + __func__, addr, offs, size, val); } } From f94aed877303107309cc021059423bf0eabfc81e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 5 Jul 2019 13:22:59 +0300 Subject: [PATCH 142/231] device/oprom: Replace CONFIG() preprocessor statements MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I7737b5f2a5c2598af68f2bca769232413f343a39 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34082 Tested-by: build bot (Jenkins) Reviewed-by: Mike Banon --- src/device/oprom/yabel/device.h | 2 + src/device/oprom/yabel/interrupt.c | 244 ++++++++++++++--------------- src/device/oprom/yabel/io.c | 83 +++++----- 3 files changed, 165 insertions(+), 164 deletions(-) diff --git a/src/device/oprom/yabel/device.h b/src/device/oprom/yabel/device.h index 8e8450a1ed..4f28a59dfa 100644 --- a/src/device/oprom/yabel/device.h +++ b/src/device/oprom/yabel/device.h @@ -85,7 +85,9 @@ typedef struct { u8 devfn; #if CONFIG(PCI_OPTION_ROM_RUN_YABEL) struct device* dev; + u64 puid; /* unused */ #else + void *dev; u64 puid; phandle_t phandle; ihandle_t ihandle; diff --git a/src/device/oprom/yabel/interrupt.c b/src/device/oprom/yabel/interrupt.c index ea2a8036aa..2bc238e75a 100644 --- a/src/device/oprom/yabel/interrupt.c +++ b/src/device/oprom/yabel/interrupt.c @@ -343,7 +343,8 @@ handleInt1a(void) { // function number in AX u8 bus, devfn, offs; - struct device* dev; + struct device *dev = NULL; + switch (M.x86.R_AX) { case 0xb101: // Installation check @@ -361,30 +362,28 @@ handleInt1a(void) // DEBUG_PRINTF_INTR("%s(): function: %x: PCI Find Device\n", __func__, M.x86.R_AX); - /* FixME: support SI != 0 */ -#if CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES) - dev = dev_find_device(M.x86.R_DX, M.x86.R_CX, 0); - if (dev != 0) { - DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Find Device --> 0x%04x\n", - __func__, M.x86.R_AX, M.x86.R_BX); - M.x86.R_BH = dev->bus->secondary; - M.x86.R_BL = dev->path.pci.devfn; - M.x86.R_AH = 0x00; // return code: success - CLEAR_FLAG(F_CF); -#else + /* FixME: support SI != 0 */ + // only allow the device to find itself... if ((M.x86.R_CX == bios_device.pci_device_id) && (M.x86.R_DX == bios_device.pci_vendor_id) // device index must be 0 && (M.x86.R_SI == 0)) { - CLEAR_FLAG(F_CF); - M.x86.R_AH = 0x00; // return code: success + dev = bios_device.dev; M.x86.R_BH = bios_device.bus; M.x86.R_BL = bios_device.devfn; -#endif - } else { + } else if (CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES)) { + dev = dev_find_device(M.x86.R_DX, M.x86.R_CX, 0); + if (dev != NULL) { + M.x86.R_BH = dev->bus->secondary; + M.x86.R_BL = dev->path.pci.devfn; + DEBUG_PRINTF_INTR + ("%s(): function %x: PCI Find Device --> 0x%04x\n", + __func__, M.x86.R_AX, M.x86.R_BX); + } + } + if (dev == NULL) { DEBUG_PRINTF_INTR ("%s(): function %x: invalid device/vendor/device index! (%04x/%04x/%02x expected: %04x/%04x/00)\n", __func__, M.x86.R_AX, M.x86.R_CX, M.x86.R_DX, @@ -393,7 +392,10 @@ handleInt1a(void) SET_FLAG(F_CF); M.x86.R_AH = 0x86; // return code: device not found + return; } + CLEAR_FLAG(F_CF); + M.x86.R_AH = 0x00; // return code: success break; case 0xb108: //read configuration byte case 0xb109: //read configuration word @@ -403,18 +405,16 @@ handleInt1a(void) offs = M.x86.R_DI; DEBUG_PRINTF_INTR("%s(): function: %x: PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", __func__, M.x86.R_AX, bus, devfn, offs); -#if CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES) - dev = dev_find_slot(bus, devfn); - DEBUG_PRINTF_INTR("%s(): function: %x: dev_find_slot() returned: %s\n", + + if ((bus == bios_device.bus) && (devfn == bios_device.devfn)) { + dev = bios_device.dev; + } else if (CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES)) { + dev = dev_find_slot(bus, devfn); + DEBUG_PRINTF_INTR("%s(): function: %x: dev_find_slot() returned: %s\n", __func__, M.x86.R_AX, dev_path(dev)); - if (dev == 0) { - // fail accesses to non-existent devices... -#else - dev = bios_device.dev; - if ((bus != bios_device.bus) - || (devfn != bios_device.devfn)) { - // fail accesses to any device but ours... -#endif + } + + if (dev == NULL) { printf ("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n", __func__, bus, bios_device.bus, devfn, @@ -423,57 +423,54 @@ handleInt1a(void) M.x86.R_AH = 0x87; //return code: bad pci register HALT_SYS(); return; - } else { - switch (M.x86.R_AX) { - case 0xb108: - M.x86.R_CL = -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - pci_read_config8(dev, offs); -#else - (u8) rtas_pci_config_read(bios_device. - puid, 1, - bus, devfn, - offs); -#endif - DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Read @%02x --> 0x%02x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_CL); - break; - case 0xb109: - M.x86.R_CX = -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - pci_read_config16(dev, offs); -#else - (u16) rtas_pci_config_read(bios_device. - puid, 2, - bus, devfn, - offs); -#endif - DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Read @%02x --> 0x%04x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_CX); - break; - case 0xb10a: - M.x86.R_ECX = -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - pci_read_config32(dev, offs); -#else - (u32) rtas_pci_config_read(bios_device. - puid, 4, - bus, devfn, - offs); -#endif - DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Read @%02x --> 0x%08x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_ECX); - break; - } - CLEAR_FLAG(F_CF); - M.x86.R_AH = 0x0; // return code: success } + + switch (M.x86.R_AX) { + case 0xb108: + M.x86.R_CL = +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + pci_read_config8(dev, offs); +#else + (u8) rtas_pci_config_read(bios_device.puid, 1, + bus, devfn, + offs); +#endif + DEBUG_PRINTF_INTR + ("%s(): function %x: PCI Config Read @%02x --> 0x%02x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_CL); + break; + case 0xb109: + M.x86.R_CX = +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + pci_read_config16(dev, offs); +#else + (u16) rtas_pci_config_read(bios_device.puid, 2, + bus, devfn, + offs); +#endif + DEBUG_PRINTF_INTR + ("%s(): function %x: PCI Config Read @%02x --> 0x%04x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_CX); + break; + case 0xb10a: + M.x86.R_ECX = +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + pci_read_config32(dev, offs); +#else + (u32) rtas_pci_config_read(bios_device.puid, 4, + bus, devfn, + offs); +#endif + DEBUG_PRINTF_INTR + ("%s(): function %x: PCI Config Read @%02x --> 0x%08x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_ECX); + break; + } + CLEAR_FLAG(F_CF); + M.x86.R_AH = 0x0; // return code: success break; case 0xb10b: //write configuration byte case 0xb10c: //write configuration word @@ -481,9 +478,12 @@ handleInt1a(void) bus = M.x86.R_BH; devfn = M.x86.R_BL; offs = M.x86.R_DI; - if ((bus != bios_device.bus) - || (devfn != bios_device.devfn)) { - // fail accesses to any device but ours... + + if ((bus == bios_device.bus) && (devfn == bios_device.devfn)) { + dev = bios_device.dev; + } + + if (dev == NULL) { printf ("%s(): Config read access invalid! bus: %x (%x), devfn: %x (%x), offs: %x\n", __func__, bus, bios_device.bus, devfn, @@ -492,48 +492,48 @@ handleInt1a(void) M.x86.R_AH = 0x87; //return code: bad pci register HALT_SYS(); return; - } else { - switch (M.x86.R_AX) { - case 0xb10b: -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - pci_write_config8(bios_device.dev, offs, M.x86.R_CL); -#else - rtas_pci_config_write(bios_device.puid, 1, bus, - devfn, offs, M.x86.R_CL); -#endif - DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Write @%02x <-- 0x%02x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_CL); - break; - case 0xb10c: -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - pci_write_config16(bios_device.dev, offs, M.x86.R_CX); -#else - rtas_pci_config_write(bios_device.puid, 2, bus, - devfn, offs, M.x86.R_CX); -#endif - DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Write @%02x <-- 0x%04x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_CX); - break; - case 0xb10d: -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - pci_write_config32(bios_device.dev, offs, M.x86.R_ECX); -#else - rtas_pci_config_write(bios_device.puid, 4, bus, - devfn, offs, M.x86.R_ECX); -#endif - DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Write @%02x <-- 0x%08x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_ECX); - break; - } - CLEAR_FLAG(F_CF); - M.x86.R_AH = 0x0; // return code: success } + + switch (M.x86.R_AX) { + case 0xb10b: +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + pci_write_config8(dev, offs, M.x86.R_CL); +#else + rtas_pci_config_write(bios_device.puid, 1, bus, + devfn, offs, M.x86.R_CL); +#endif + DEBUG_PRINTF_INTR + ("%s(): function %x: PCI Config Write @%02x <-- 0x%02x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_CL); + break; + case 0xb10c: +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + pci_write_config16(dev, offs, M.x86.R_CX); +#else + rtas_pci_config_write(bios_device.puid, 2, bus, + devfn, offs, M.x86.R_CX); +#endif + DEBUG_PRINTF_INTR + ("%s(): function %x: PCI Config Write @%02x <-- 0x%04x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_CX); + break; + case 0xb10d: +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + pci_write_config32(dev, offs, M.x86.R_ECX); +#else + rtas_pci_config_write(bios_device.puid, 4, bus, + devfn, offs, M.x86.R_ECX); +#endif + DEBUG_PRINTF_INTR + ("%s(): function %x: PCI Config Write @%02x <-- 0x%08x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_ECX); + break; + } + CLEAR_FLAG(F_CF); + M.x86.R_AH = 0x0; // return code: success break; default: printf("%s(): unknown function (%x) for int1a handler.\n", diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index 2b384ea7b4..8ae91d46e0 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -431,18 +431,16 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size) offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", __func__, bus, devfn, offs); -#if CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES) - dev = dev_find_slot(bus, devfn); - DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", - __func__, dev_path(dev)); - if (dev == 0) { - // fail accesses to non-existent devices... -#else - dev = bios_device.dev; - if ((bus != bios_device.bus) - || (devfn != bios_device.devfn)) { - // fail accesses to any device but ours... -#endif + + if ((bus == bios_device.bus) && (devfn == bios_device.devfn)) { + dev = bios_device.dev; + } else if (CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES)) { + dev = dev_find_slot(bus, devfn); + DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", + __func__, dev_path(dev)); + } + + if (dev == NULL) { printf ("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n", __func__, bus, bios_device.bus, devfn, @@ -450,8 +448,9 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size) SET_FLAG(F_CF); HALT_SYS(); return 0; - } else { -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + } + + if (CONFIG(PCI_OPTION_ROM_RUN_YABEL)) { switch (size) { case 1: rval = pci_read_config8(dev, offs); @@ -463,23 +462,21 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size) rval = pci_read_config32(dev, offs); break; } -#else - rval = - (u32) rtas_pci_config_read(bios_device. - puid, size, - bus, devfn, - offs); -#endif - DEBUG_PRINTF_IO - ("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n", - __func__, addr, offs, size, rval); + } else { + rval = (u32) rtas_pci_config_read(bios_device.puid, size, bus, devfn, offs); } + + DEBUG_PRINTF_IO + ("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n", + __func__, addr, offs, size, rval); + return rval; } void pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size) { + struct device *dev = NULL; u32 port_cf8_val = 0; u8 bus, devfn, offs; @@ -498,37 +495,39 @@ pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size) devfn = (port_cf8_val & 0x0000FF00) >> 8; offs = (port_cf8_val & 0x000000FF); offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly - if ((bus != bios_device.bus) - || (devfn != bios_device.devfn)) { - // fail accesses to any device but ours... + + if ((bus == bios_device.bus) && (devfn == bios_device.devfn)) { + dev = bios_device.dev; + } else { printf ("Config write access invalid! PCI device %x:%x.%x, offs: %x\n", bus, devfn >> 3, devfn & 7, offs); -#if !CONFIG(YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG) + + if (CONFIG(YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG)) + return; + // fail accesses to any device but ours... HALT_SYS(); -#endif - } else { -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + } + + if (CONFIG(PCI_OPTION_ROM_RUN_YABEL)) { switch (size) { case 1: - pci_write_config8(bios_device.dev, offs, val); + pci_write_config8(dev, offs, val); break; case 2: - pci_write_config16(bios_device.dev, offs, val); + pci_write_config16(dev, offs, val); break; case 4: - pci_write_config32(bios_device.dev, offs, val); + pci_write_config32(dev, offs, val); break; } -#else - rtas_pci_config_write(bios_device.puid, - size, bus, devfn, offs, - val); -#endif - DEBUG_PRINTF_IO - ("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n", - __func__, addr, offs, size, val); + } else { + rtas_pci_config_write(bios_device.puid, size, bus, devfn, offs, val); } + + DEBUG_PRINTF_IO + ("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n", + __func__, addr, offs, size, val); } u8 From f08f266aa23c444d43cd4b521278c130cfa37c95 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 8 Jul 2019 22:21:17 +0300 Subject: [PATCH 143/231] cpu/amd: Remove empty smm_lock() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I599d1d7e28f3a6439b04ef9bd38f671e1a876e92 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34148 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans --- src/cpu/amd/smm/smm_init.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c index 3efb964165..60e506c4e5 100644 --- a/src/cpu/amd/smm/smm_init.c +++ b/src/cpu/amd/smm/smm_init.c @@ -70,11 +70,6 @@ void smm_init(void) /* CPU MSR are set in CPU init */ } -void smm_lock(void) -{ - /* We lock SMM in CPU init */ -} - void smm_init_completion(void) { } From eac7023f848599f023cc07a95a32040da711a700 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 8 Jul 2019 21:32:58 +0300 Subject: [PATCH 144/231] soc/intel: Remove invalid smm_relocate stubs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the per-platform empty stubs, builds would just fail as there is no equivalent conditional for the smmrelocate.c file. Change-Id: Ie11f307b7bc5415bfdba6a2c66aed01b70d9f0e0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34150 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel --- src/soc/intel/cannonlake/include/soc/smm.h | 11 ----------- src/soc/intel/icelake/include/soc/smm.h | 11 ----------- src/soc/intel/skylake/include/soc/smm.h | 10 ---------- 3 files changed, 32 deletions(-) diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index e38c3381d8..e1c819ba14 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -50,7 +50,6 @@ struct smm_relocation_params { /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); -#if CONFIG(HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, @@ -58,14 +57,4 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, void smm_initialize(void); void smm_relocate(void); -#else /* CONFIG_HAVE_SMI_HANDLER */ -static inline void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) {} -static inline void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) {} -static inline void smm_initialize(void) {} - -static inline void smm_relocate(void) {} -#endif /* CONFIG_HAVE_SMI_HANDLER */ - #endif diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index f556b11514..3c66f57d43 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -49,7 +49,6 @@ struct smm_relocation_params { /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); -#if CONFIG(HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, @@ -57,14 +56,4 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, void smm_initialize(void); void smm_relocate(void); -#else /* CONFIG_HAVE_SMI_HANDLER */ -static inline void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) {} -static inline void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) {} -static inline void smm_initialize(void) {} - -static inline void smm_relocate(void) {} -#endif /* CONFIG_HAVE_SMI_HANDLER */ - #endif diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 72992d2517..7114a80b08 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -48,21 +48,11 @@ struct smm_relocation_params { int smm_save_state_in_msrs; }; -#if CONFIG(HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); void smm_initialize(void); void smm_relocate(void); -#else /* CONFIG_HAVE_SMI_HANDLER */ -static inline void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) {} -static inline void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) {} -static inline void smm_initialize(void) {} - -static inline void smm_relocate(void) {} -#endif /* CONFIG_HAVE_SMI_HANDLER */ #endif From 571b7b211893e09c05287dda773579d367df548c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 8 Jul 2019 23:25:05 +0300 Subject: [PATCH 145/231] intel/i82801ix: Rename smm_lock() prototype MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This southbridge code may be built with either ASEG or TSEG. Fix minor collision in namespaces. Change-Id: I04f90fb308c280621a3037fee4bece1e5655480e Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34153 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans --- src/southbridge/intel/i82801ix/i82801ix.h | 2 ++ src/southbridge/intel/i82801ix/lpc.c | 9 +++------ src/southbridge/intel/i82801ix/smi.c | 2 +- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 421a101bdc..31eabb6e42 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -212,6 +212,8 @@ static inline int lpc_is_mobile(const u16 devid) } #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) +void aseg_smm_lock(void); + #if defined(__PRE_RAM__) void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index c7de2a14df..546fbced77 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -366,7 +366,6 @@ static void enable_clock_gating(void) RCBA32(0x38c0) |= 7; } -#if CONFIG(HAVE_SMI_HANDLER) static void i82801ix_lock_smm(struct device *dev) { if (!acpi_is_wakeup_s3()) { @@ -387,9 +386,8 @@ static void i82801ix_lock_smm(struct device *dev) * userspace applications to deceive us: */ if (!CONFIG(PARALLEL_MP)) - smm_lock(); + aseg_smm_lock(); } -#endif static void lpc_init(struct device *dev) { @@ -431,9 +429,8 @@ static void lpc_init(struct device *dev) /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); -#if CONFIG(HAVE_SMI_HANDLER) - i82801ix_lock_smm(dev); -#endif + if (CONFIG(HAVE_SMI_HANDLER)) + i82801ix_lock_smm(dev); } static void i82801ix_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index a9d5e7dc08..5d898cc3c6 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -171,7 +171,7 @@ void smm_init_completion(void) restore_default_smm_area(default_smm_area); } -void smm_lock(void) +void aseg_smm_lock(void) { /* LOCK the SMM memory window and enable normal SMM. * After running this function, only a full reset can From fd10f773dbecc7ac9a2b8af131e91c107409dbc8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 9 Jul 2019 04:37:35 +0300 Subject: [PATCH 146/231] cpu/x86: Remove obsolete smm_init_completion() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is not used together with PARALLEL_MP and SMM_TSEG. Platforms with SMM_ASEG continue to have their local implementation doing the same thing. Change-Id: I13a2f164804330c93240bff7f048e0a162b3ae25 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34154 Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/cpu/intel/smm/gen1/smmrelocate.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index d52043f047..986929c9cb 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -57,7 +57,6 @@ struct smm_relocation_params { /* This gets filled in and used during relocation. */ static struct smm_relocation_params smm_reloc_params; -static void *default_smm_area = NULL; /* On model_6fx, model_1067x and model_106cx SMRR functions slightly differently. The MSR are at different location from the rest @@ -168,11 +167,6 @@ static void setup_ied_area(struct smm_relocation_params *params) memset(ied_base + (1 << 20), 0, (32 << 10)); } -void smm_init_completion(void) -{ - restore_default_smm_area(default_smm_area); -} - void smm_lock(void) { /* LOCK the SMM memory window and enable normal SMM. From 0d9f4e92776846554607902c188a389e4aee1f8e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 9 Jul 2019 10:40:13 +0300 Subject: [PATCH 147/231] soc/intel: Drop some HAVE_SMI_HANDLER guards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The necessary conditionals are evaluated within cpu/x86/Makefile.inc and there are no default targets added unconditionally to build. Change-Id: I694cccf6779551445b83659838749dff02aedece Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34172 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans --- src/soc/intel/denverton_ns/Makefile.inc | 2 +- src/soc/intel/fsp_baytrail/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index cfd814910e..f01fadbdfe 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -19,7 +19,7 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 2fbf34ecbb..3a58be9afd 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -20,7 +20,7 @@ ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y) subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/intel/microcode From 6665da81ef289e9ba478e93b6c41928fa19f7d28 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Thu, 25 Apr 2019 11:17:05 +0200 Subject: [PATCH 148/231] soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size only Fixed ROM area is allocated. Reduce the ROM size using CONFIG_COREBOOT_ROMSIZE. BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I7a47bf2600f546271c5a65641d29f868ff2748bf Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/31822 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/braswell/acpi/lpc.asl | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 6b2ececc40..9caa8f17eb 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. - * Copyright (C) 2018 Eltan B.V. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -42,10 +42,20 @@ Device (LPCB) Device (FWH) /* Firmware Hub */ { Name (_HID, EISAID("INT0800")) - Name (_CRS, ResourceTemplate() + Name (RBUF, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + Memory32Fixed(ReadOnly, 0, 0, FBAR) }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^FBAR._BAS, FBAS) + CreateDwordField (^RBUF, ^FBAR._LEN, FLEN) + Multiply(CONFIG_COREBOOT_ROMSIZE_KB, 1024, Local0) + Store(Local0, FLEN) + Add(Subtract(0xffffffff, Local0), 1, FBAS) + Return (^RBUF) + } } #if !CONFIG(DISABLE_HPET) From bd4ad6e630fd3ae8f19022bceca9022c7441547c Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Wed, 29 May 2019 14:12:30 +0200 Subject: [PATCH 149/231] vendorcode/eltan/security/lib: Implement SHA endian function digest from vb2_digest_bufer() does not contains the correct endian. Create cb_sha_endian() which can convert the calculated digest into big endian or little endian when required. BUG=N/A TEST=Created binary and verify logging on Facebok FBG-1701 Change-Id: If828bde54c79e836a5b05ff0447645d7e06e819a Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/30831 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- .../eltan/security/include/cb_sha.h | 33 +++++++++++ .../eltan/security/lib/Makefile.inc | 59 +++++++++++++++++++ src/vendorcode/eltan/security/lib/cb_sha.c | 56 ++++++++++++++++++ 3 files changed, 148 insertions(+) create mode 100644 src/vendorcode/eltan/security/include/cb_sha.h create mode 100644 src/vendorcode/eltan/security/lib/Makefile.inc create mode 100644 src/vendorcode/eltan/security/lib/cb_sha.c diff --git a/src/vendorcode/eltan/security/include/cb_sha.h b/src/vendorcode/eltan/security/include/cb_sha.h new file mode 100644 index 0000000000..4d087f40c9 --- /dev/null +++ b/src/vendorcode/eltan/security/include/cb_sha.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_CB_SHA_H__ +#define __SECURITY_CB_SHA_H__ + +#include <2rsa.h> +#include +#include + +/* Supported Algorithm types for hash */ +enum endian_algorithm { + NO_ENDIAN_ALGORITHM = 0, + BIG_ENDIAN_ALGORITHM = 1, + LITTLE_ENDIAN_ALGORITHM = 2, +}; + +int cb_sha_endian(enum vb2_hash_algorithm hash_alg, const uint8_t *data, uint32_t len, + uint8_t *digest, enum endian_algorithm endian); + +#endif \ No newline at end of file diff --git a/src/vendorcode/eltan/security/lib/Makefile.inc b/src/vendorcode/eltan/security/lib/Makefile.inc new file mode 100644 index 0000000000..5ef1bca65f --- /dev/null +++ b/src/vendorcode/eltan/security/lib/Makefile.inc @@ -0,0 +1,59 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2018-2019 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# call with $1 = stage name to create rules for building the library +# for the stage and adding it to the stage's set of object files. +define vendor-security-lib +VEN_SEC_LIB_$(1) = $(obj)/external/ven_sec_lib-$(1)/vboot_fw21.a +VEN_SEC_CFLAGS_$(1) += $$(patsubst -I%,-I$(top)/%,\ + $$(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ + $$(filter-out -I$(obj), $$(CPPFLAGS_$(1))))) +VEN_SEC_CFLAGS_$(1) += $$(CFLAGS_$(1)) +VEN_SEC_CFLAGS_$(1) += $$($(1)-c-ccopts) +VEN_SEC_CFLAGS_$(1) += -I$(abspath $(obj)) -Wno-missing-prototypes + +$$(VEN_SEC_LIB_$(1)): $(obj)/config.h + printf " MAKE $(subst $(obj)/,,$(@))\n" + +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ + CC="$$(CC_$(1))" \ + CFLAGS="$$(VEN_SEC_CFLAGS_$(1))" VBOOT2="y" \ + $(MAKE) -C $(VBOOT_SOURCE) \ + BUILD=$$(abspath $$(dir $$(VEN_SEC_LIB_$(1)))) \ + V=$(V) \ + fwlib21 +endef # vendor-security-for-stage + +CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include +CFLAGS_common += -I3rdparty/vboot/firmware/lib21/include + +ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) + +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += cb_sha.c +$(eval $(call vendor-security-lib,bootblock)) +bootblock-srcs += $(obj)/external/ven_sec_lib-bootblock/vboot_fw21.a + +postcar-y += cb_sha.c +$(eval $(call vendor-security-lib,postcar)) +postcar-srcs += $(obj)/external/ven_sec_lib-postcar/vboot_fw21.a + +ramstage-y += cb_sha.c +$(eval $(call vendor-security-lib,ramstage)) +ramstage-srcs += $(obj)/external/ven_sec_lib-ramstage/vboot_fw21.a + +romstage-y += cb_sha.c +$(eval $(call vendor-security-lib,romstage)) +romstage-srcs += $(obj)/external/ven_sec_lib-romstage/vboot_fw21.a + +endif \ No newline at end of file diff --git a/src/vendorcode/eltan/security/lib/cb_sha.c b/src/vendorcode/eltan/security/lib/cb_sha.c new file mode 100644 index 0000000000..47cd10a47c --- /dev/null +++ b/src/vendorcode/eltan/security/lib/cb_sha.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +int cb_sha_endian(enum vb2_hash_algorithm hash_alg, const uint8_t *data, uint32_t len, + uint8_t *digest, enum endian_algorithm endian) +{ + int i; + int rv; + uint32_t digest_size; + uint8_t *result_ptr; + uint8_t result[VB2_MAX_DIGEST_SIZE]; + + switch (hash_alg) { + case VB2_HASH_SHA1: + digest_size = VB2_SHA1_DIGEST_SIZE; + break; + case VB2_HASH_SHA256: + digest_size = VB2_SHA256_DIGEST_SIZE; + break; + case VB2_HASH_SHA512: + digest_size = VB2_SHA512_DIGEST_SIZE; + break; + default: + return VB2_ERROR_SHA_INIT_ALGORITHM; + } + + result_ptr = result; + rv = vb2_digest_buffer(data, len, hash_alg, result_ptr, digest_size); + if (rv || (endian == NO_ENDIAN_ALGORITHM)) + return rv; + + for (i = 0; i < digest_size; ++i) { + if (endian == BIG_ENDIAN_ALGORITHM) { + /* use big endian */ + digest[i] = *result_ptr++; + } else { + /* use little endian */ + digest[digest_size - i - 1] = *result_ptr++; + } + } + return rv; +} From b3af349284c3fbe14ee55c48652fb46ddeb80484 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 10 Jun 2019 11:33:40 +0200 Subject: [PATCH 150/231] soc/intel/block/cpu: remove unused USE_COREBOOT_NATIVE_MP_INIT Only CONFIG_USE_INTEL_FSP_MP_INIT makes a difference whether native MP init is used or not. Also make USE_INTEL_FSP_MP_INIT mutually exclusive with USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI as this option requires coreboot to set up AP and publish PPI based on it. Change-Id: I65b80805d3cd7b66f8c9f878d3c741b98f24288d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33357 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- Documentation/soc/intel/mp_init/mp_init.md | 6 +++--- src/soc/intel/common/block/cpu/Kconfig | 13 +------------ 2 files changed, 4 insertions(+), 15 deletions(-) diff --git a/Documentation/soc/intel/mp_init/mp_init.md b/Documentation/soc/intel/mp_init/mp_init.md index f81ffc143e..7284e8a1c5 100644 --- a/Documentation/soc/intel/mp_init/mp_init.md +++ b/Documentation/soc/intel/mp_init/mp_init.md @@ -27,9 +27,9 @@ Considering these facts, there are 3 possible solutions to perform MP initialization from coreboot + FSP space. 1. coreboot to perform complete MP initialization by its own. This includes -BSP and AP programming of CPU features mostly non-restricted one. Preferred -Kconfig is USE_COREBOOT_NATIVE_MP_INIT. SoCs like SKL, KBL, APL are okay to -make use of same Kconfig option for MP initialization. +BSP and AP programming of CPU features mostly non-restricted one. This is +the default configuration. Most SoCs like SKL, KBL, APL are okay to make use +of this MP initialization method. 2. Alternatively, SoC users also can skip coreboot doing MP initialization and make use of FSP binary to perform same task. This can be achieved by using diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 9ec5307e48..8cc572d3b2 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,18 +51,10 @@ config INTEL_CAR_NEM_ENHANCED ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. -menu "Multiple Processor (MP) Initialization Options" -config USE_COREBOOT_NATIVE_MP_INIT - bool "Perform MP Initialization by coreboot" - default y if !PLATFORM_USES_FSP2_1 - default n - help - This option allows user to select native coreboot option to perform - multiprocessor initialization. - config USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" default n + depends on !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help This option allows FSP to perform multiprocessor initialization. @@ -71,9 +63,6 @@ config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI depends on FSP_USES_MP_SERVICES_PPI default y if PLATFORM_USES_FSP2_1 default n - select USE_COREBOOT_NATIVE_MP_INIT help This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization. - -endmenu # Multiple Processor (MP) Initialization Options From 64fb4a32e0b7e51f25f530d232fefc14c7523def Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 10 Jun 2019 17:29:18 -0600 Subject: [PATCH 151/231] nb/intel/nehalem: Die if no memory ranks found Die if there are no memory ranks found to prevent a division by zero. Change-Id: I6146dd8420f3734d1a672a9f29a098f47fcb739c Signed-off-by: Jacob Garber Found-by: Coverity CID 1229628 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33403 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/northbridge/intel/nehalem/raminit.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 2b71c81825..0b5f44c73f 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1010,6 +1010,9 @@ static void compute_derived_timings(struct raminfo *info) } } + if (count == 0) + die("No memory ranks found for channel %u\n", channel); + info->avg4044[channel] = sum / count; info->max4048[channel] = max_of_unk; } From 975a7e3ba3e646f91a5c6e73968e9efd1a1521f1 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 10 Jun 2019 16:32:47 -0600 Subject: [PATCH 152/231] nb/intel/nehalem: Tidy quickpath_reserved calculation - Remove unnecessary braces - Move variable assignment out of function call - Do not find lowest bit set of 0, which is undefined - Use unsigned integer when bit shifting Change-Id: I8651f8cd04165d8d31c44f7919ad5e43499d3d4c Signed-off-by: Jacob Garber Found-by: Coverity CID 1229562 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33381 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons --- src/northbridge/intel/nehalem/raminit.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 0b5f44c73f..b4ff85cdd4 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1434,14 +1434,17 @@ static void program_total_memory_map(struct raminfo *info) memory_map[2] = TOUUD | 1; quickpath_reserved = 0; - { - u32 t; + u32 t = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x68); - gav(t = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x68)); - if (t & 0x800) - quickpath_reserved = - (1 << find_lowest_bit_set32(t >> 20)); + gav(t); + + if (t & 0x800) { + u32 shift = t >> 20; + if (shift == 0) + die("Quickpath value is 0\n"); + quickpath_reserved = (u32)1 << find_lowest_bit_set32(shift); } + if (memory_remap) TOUUD -= quickpath_reserved; From 5ccce7cdc712843c4f3eef2153b91d98548a12bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 15 Mar 2019 10:04:11 +0200 Subject: [PATCH 153/231] util/sconfig: Declare the repeated devicetree storage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With DEVTREE_EARLY we could create incomplete device objects with topology links removed to reduce footprint for bootblock. Declare everything with 'static __unused DEVTREE_CONST' to avoid compiler errors and to not expose unusable device object names to global scope. Change-Id: Ie4cb9e75f179f44edf4f8256ad8320bc2d4ae71a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31931 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/sconfig/main.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 548063fd88..265e7285cb 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -696,17 +696,17 @@ static int dev_has_children(struct device *dev) static void pass0(FILE *fil, struct device *ptr, struct device *next) { if (ptr == &base_root_dev) { - fprintf(fil, "DEVTREE_CONST struct bus %s_links[];\n", + fprintf(fil, "STORAGE struct bus %s_links[];\n", ptr->name); return; } - fprintf(fil, "static DEVTREE_CONST struct device %s;\n", ptr->name); + fprintf(fil, "STORAGE struct device %s;\n", ptr->name); if (ptr->res) - fprintf(fil, "DEVTREE_CONST struct resource %s_res[];\n", + fprintf(fil, "STORAGE struct resource %s_res[];\n", ptr->name); if (dev_has_children(ptr)) - fprintf(fil, "DEVTREE_CONST struct bus %s_links[];\n", + fprintf(fil, "STORAGE struct bus %s_links[];\n", ptr->name); if (next) @@ -723,7 +723,7 @@ static void emit_resources(FILE *fil, struct device *ptr) return; int i = 1; - fprintf(fil, "DEVTREE_CONST struct resource %s_res[] = {\n", ptr->name); + fprintf(fil, "STORAGE struct resource %s_res[] = {\n", ptr->name); struct resource *r = ptr->res; while (r) { fprintf(fil, @@ -765,7 +765,7 @@ static void emit_bus(FILE *fil, struct bus *bus) static void emit_dev_links(FILE *fil, struct device *ptr) { - fprintf(fil, "DEVTREE_CONST struct bus %s_links[] = {\n", + fprintf(fil, "STORAGE struct bus %s_links[] = {\n", ptr->name); struct bus *bus = ptr->bus; @@ -784,9 +784,11 @@ static void pass1(FILE *fil, struct device *ptr, struct device *next) struct chip_instance *chip_ins = ptr->chip_instance; int has_children = dev_has_children(ptr); - if (ptr != &base_root_dev) - fprintf(fil, "static "); - fprintf(fil, "DEVTREE_CONST struct device %s = {\n", ptr->name); + if (ptr == &base_root_dev) + fprintf(fil, "DEVTREE_CONST struct device %s = {\n", ptr->name); + else + fprintf(fil, "STORAGE struct device %s = {\n", ptr->name); + fprintf(fil, "#if !DEVTREE_EARLY\n"); /* @@ -942,7 +944,7 @@ static void emit_chip_headers(FILE *fil, struct chip *chip) static void emit_chip_instance(FILE *fil, struct chip_instance *instance) { - fprintf(fil, "DEVTREE_CONST struct %s_config %s_info_%d = {", + fprintf(fil, "STORAGE struct %s_config %s_info_%d = {", instance->chip->name_underscore, instance->chip->name_underscore, instance->id); @@ -965,6 +967,8 @@ static void emit_chips(FILE *fil) emit_chip_headers(fil, chip); + fprintf(fil, "\n#define STORAGE static __unused DEVTREE_CONST\n\n"); + for (; chip; chip = chip->next) { if (!chip->chiph_exists) continue; From e29a6ac16a9f478fc00ce7cb83f3779954e3168d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 15 Mar 2019 17:05:19 +0200 Subject: [PATCH 154/231] util/sconfig: Add commonlib/helpers.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Followup work injects ARRAY_SIZE() in static.c Change-Id: Ifbcaa1b613aef312d3876e8b536499a9f01a8d19 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31932 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Martin Roth --- util/sconfig/Makefile.inc | 1 + util/sconfig/main.c | 1 + 2 files changed, 2 insertions(+) diff --git a/util/sconfig/Makefile.inc b/util/sconfig/Makefile.inc index 76bbd45674..c47b43956d 100644 --- a/util/sconfig/Makefile.inc +++ b/util/sconfig/Makefile.inc @@ -4,6 +4,7 @@ sconfigobj += sconfig.tab.o sconfigobj += main.o SCONFIGFLAGS += -I$(top)/util/sconfig -I$(objutil)/sconfig +SCONFIGFLAGS += -I$(top)/src/commonlib/include $(objutil)/sconfig: mkdir -p $@ diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 265e7285cb..385ced16ab 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -15,6 +15,7 @@ */ #include +#include #include "sconfig.h" #include "sconfig.tab.h" From ad1456f0d7c9fcfcf6ef78969cb0e1ac6f17739a Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 22 Jun 2019 09:52:12 +0200 Subject: [PATCH 155/231] vendorcode/amd: Move 'static' to the beginning of declaration Change-Id: Ib9934f103262c57af076bd27d97c3166d8f2318b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33674 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/vendorcode/amd/cimx/sb800/AZALIA.c | 16 ++++++++-------- src/vendorcode/amd/cimx/sb800/ECfanc.c | 6 +++--- src/vendorcode/amd/cimx/sb800/SATA.c | 6 +++--- src/vendorcode/amd/cimx/sb800/SBCMN.c | 8 ++++---- src/vendorcode/amd/cimx/sb800/SBPort.c | 4 ++-- 5 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/vendorcode/amd/cimx/sb800/AZALIA.c b/src/vendorcode/amd/cimx/sb800/AZALIA.c index ccb4f9092a..1d7d0f9d7f 100644 --- a/src/vendorcode/amd/cimx/sb800/AZALIA.c +++ b/src/vendorcode/amd/cimx/sb800/AZALIA.c @@ -61,7 +61,7 @@ VOID configureAzaliaSetConfigD4Dword (IN CODECENTRY* tempAzaliaCodecEntryPtr, IN * * */ -const static CODECENTRY AzaliaCodecAlc882Table[] = +static const CODECENTRY AzaliaCodecAlc882Table[] = { {0x14, 0x01014010}, {0x15, 0x01011012}, @@ -84,7 +84,7 @@ const static CODECENTRY AzaliaCodecAlc882Table[] = * * */ -const static CODECENTRY AzaliaCodecAlc262Table[] = +static const CODECENTRY AzaliaCodecAlc262Table[] = { {0x14, 0x01014010}, {0x15, 0x411111F0}, @@ -106,7 +106,7 @@ const static CODECENTRY AzaliaCodecAlc262Table[] = * * */ -const static CODECENTRY AzaliaCodecAlc269Table[] = +static const CODECENTRY AzaliaCodecAlc269Table[] = { {0x12, 0x99A30960}, {0x14, 0x99130110}, @@ -129,7 +129,7 @@ const static CODECENTRY AzaliaCodecAlc269Table[] = * * */ -const static CODECENTRY AzaliaCodecAlc861Table[] = +static const CODECENTRY AzaliaCodecAlc861Table[] = { {0x01, 0x8086C601}, {0x0B, 0x01014110}, @@ -152,7 +152,7 @@ const static CODECENTRY AzaliaCodecAlc861Table[] = * * */ -const static CODECENTRY AzaliaCodecAlc889Table[] = +static const CODECENTRY AzaliaCodecAlc889Table[] = { {0x11, 0x411111F0}, {0x14, 0x01014010}, @@ -176,7 +176,7 @@ const static CODECENTRY AzaliaCodecAlc889Table[] = * * */ -const static CODECENTRY AzaliaCodecAd1984Table[] = +static const CODECENTRY AzaliaCodecAd1984Table[] = { {0x11, 0x0221401F}, {0x12, 0x90170110}, @@ -198,7 +198,7 @@ const static CODECENTRY AzaliaCodecAd1984Table[] = * * */ -const static CODECENTRY FrontPanelAzaliaCodecTableList[] = +static const CODECENTRY FrontPanelAzaliaCodecTableList[] = { {0x19, 0x02A19040}, {0x1b, 0x02214020}, @@ -211,7 +211,7 @@ const static CODECENTRY FrontPanelAzaliaCodecTableList[] = * * */ -const static CODECTBLLIST azaliaCodecTableList[] = +static const CODECTBLLIST azaliaCodecTableList[] = { {0x010ec0880, (CODECENTRY*)&AzaliaCodecAlc882Table[0]}, {0x010ec0882, (CODECENTRY*)&AzaliaCodecAlc882Table[0]}, diff --git a/src/vendorcode/amd/cimx/sb800/ECfanc.c b/src/vendorcode/amd/cimx/sb800/ECfanc.c index 7e679c9995..151d882557 100644 --- a/src/vendorcode/amd/cimx/sb800/ECfanc.c +++ b/src/vendorcode/amd/cimx/sb800/ECfanc.c @@ -40,7 +40,7 @@ * * */ -const static UINT8 FunctionNumber[] = +static const UINT8 FunctionNumber[] = { Fun_81, Fun_83, @@ -55,7 +55,7 @@ const static UINT8 FunctionNumber[] = * * */ -const static UINT8 MaxZone[] = +static const UINT8 MaxZone[] = { 4, 4, @@ -70,7 +70,7 @@ const static UINT8 MaxZone[] = * * */ -const static UINT8 MaxRegister[] = +static const UINT8 MaxRegister[] = { MSG_REG9, MSG_REGB, diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c index c2f2162e9a..f9823d8fb5 100644 --- a/src/vendorcode/amd/cimx/sb800/SATA.c +++ b/src/vendorcode/amd/cimx/sb800/SATA.c @@ -176,7 +176,7 @@ shutdownUnconnectedSataPortClock ( * * */ -const static UINT32 sataIfCodeTable[] = +static const UINT32 sataIfCodeTable[] = { 0x01018F40, //sata class ID of IDE 0x01040040, //sata class ID of RAID @@ -192,7 +192,7 @@ const static UINT32 sataIfCodeTable[] = * * */ -const static UINT16 sataDeviceIDTable[] = +static const UINT16 sataDeviceIDTable[] = { 0x4390, //sata device ID of IDE 0x4392, //sata device ID of RAID @@ -208,7 +208,7 @@ const static UINT16 sataDeviceIDTable[] = * * */ -const static SATAPHYSETTING sataPhyTable[] = +static const SATAPHYSETTING sataPhyTable[] = { {0x3006, 0x0056A607}, {0x2006, 0x00061400}, diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c index 8e9f0e2814..ab203a111d 100644 --- a/src/vendorcode/amd/cimx/sb800/SBCMN.c +++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c @@ -83,7 +83,7 @@ VOID sbUsbPhySetting (IN UINT32 Value); * sbEarlyPostByteInitTable - PCI device registers initial during early POST. * */ -const static REG8MASK sbEarlyPostByteInitTable[] = +static const REG8MASK sbEarlyPostByteInitTable[] = { // SMBUS Device (Bus 0, Dev 20, Func 0) {0x00, SMBUS_BUS_DEV_FUN, 0}, @@ -134,7 +134,7 @@ const static REG8MASK sbEarlyPostByteInitTable[] = * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST. * */ -const static AcpiRegWrite sbPmioEPostInitTable[] = +static const AcpiRegWrite sbPmioEPostInitTable[] = { // HPET workaround {PMIO_BASE >> 8, SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1}, @@ -251,7 +251,7 @@ const static AcpiRegWrite sbPmioEPostInitTable[] = * abTblEntry800 - AB-Link Configuration Table for SB800 * */ -const static ABTBLENTRY abTblEntry800[] = +static const ABTBLENTRY abTblEntry800[] = { // RPR Enable downstream posted transactions to pass non-posted transactions. {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16}, @@ -297,7 +297,7 @@ const static ABTBLENTRY abTblEntry800[] = * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature * */ -const static ABTBLENTRY SbPcieOrderRule[] = +static const ABTBLENTRY SbPcieOrderRule[] = { // abPostPassNpDownStreamTbl {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31}, diff --git a/src/vendorcode/amd/cimx/sb800/SBPort.c b/src/vendorcode/amd/cimx/sb800/SBPort.c index 048850d4bb..ba6c8f025c 100644 --- a/src/vendorcode/amd/cimx/sb800/SBPort.c +++ b/src/vendorcode/amd/cimx/sb800/SBPort.c @@ -49,7 +49,7 @@ /** * sbPorInitPciTable - PCI device registers initial during the power on stage. */ -const static REG8MASK sbPorInitPciTable[] = +static const REG8MASK sbPorInitPciTable[] = { // SATA device {0x00, SATA_BUS_DEV_FUN, 0}, @@ -82,7 +82,7 @@ const static REG8MASK sbPorInitPciTable[] = /** * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage. */ -const static AcpiRegWrite sbPmioPorInitTable[] = +static const AcpiRegWrite sbPmioPorInitTable[] = { {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0}, {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5}, From 808440e6b2f7b69bcb14cccddf27b1239e47a792 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Thu, 4 Jul 2019 18:43:14 +0800 Subject: [PATCH 156/231] mb/google/octopus: Remove LPDDR4 RAMID index 5,6 CH[1] only SKU From Intel EDS: Table 3-5. LPDDR4 Configurations CH00 CH01 CH10 CH11 "x32 BGA" "x32 BGA" "x32 BGA" "x32 BGA" "x32 BGA" "x32 BGA" "Unpopulated" "Unpopulated" CH[1](CH10/CH11) can't use alone without CH[0] BUG=b:135498646,b:136694293 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: I03af74301aad3e688c97992b37c59b20a4fff58a Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/34069 Reviewed-by: Justin TerAvest Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- .../google/octopus/variants/baseboard/memory.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c index 604295b283..233ef84b80 100644 --- a/src/mainboard/google/octopus/variants/baseboard/memory.c +++ b/src/mainboard/google/octopus/variants/baseboard/memory.c @@ -178,17 +178,6 @@ static const struct lpddr4_sku cbi_skus[] = { .ch0_rank_density = LP4_8Gb_DENSITY, .ch0_dual_rank = 1, }, - /* Single Channel Configs 4GiB System Capacity Ch1 populated. */ - [5] = { - .speed = LP4_SPEED_2400, - .ch1_rank_density = LP4_16Gb_DENSITY, - }, - /* Single Channel Configs 4GiB System Capacity Ch1 populated. */ - [6] = { - .speed = LP4_SPEED_2400, - .ch1_rank_density = LP4_8Gb_DENSITY, - .ch1_dual_rank = 1, - }, /* Dual Channel Config 6GiB System Capacity */ [7] = { .speed = LP4_SPEED_2400, From 71c6c1725e0efe77787a8d3b7aaf14c0c0eba166 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 8 Jul 2019 14:16:13 -0500 Subject: [PATCH 157/231] arch/cpu/x86: Update AMD detection MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit AMD Picasso, and later, will not use CPU_AMD_AGESA or CPU_AMD_PI. Those two symbols indicate an Arch2008 system. Add SOC_AMD_COMMON to cause cpu_is_amd() to return TRUE on Picasso. This removes an error message of "Unknown CPU". The patch also assumes AMD Family 10h and non-AGESA Family 15h devices were seeing the "Unknown CPU" message. No functionality has been verified on these devices. Signed-off-by: Marshall Dawson Change-Id: I3357606c37082f3587ff91924bf7a0e0f8af9625 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34146 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/arch/x86/include/arch/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 38066c15a2..32717ba5b3 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -210,7 +210,8 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1); static inline bool cpu_is_amd(void) { - return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI); + return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI) + || CONFIG(SOC_AMD_COMMON) || CONFIG(CPU_AMD_MODEL_10XXX); } static inline bool cpu_is_intel(void) From 509f46953ece919b1610b685599e146461ae4163 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 28 Jun 2019 14:11:41 +0200 Subject: [PATCH 158/231] drivers/intel/fsp1_1/raminit.c: Always check FSP HOBs Check for FSP HOBs is depending on CONFIG_DISPLAY_HOBS. Use the CONFIG_DISPLAY_HOBS for display HOB info only and always check HOBs. Use BIOS_ERR of printk() for FSP errors. BUG=N/A TEST=Check console output on Facebook FBG1701. Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/29371 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/drivers/intel/fsp1_1/raminit.c | 63 ++++++++--------------------- src/drivers/intel/fsp1_1/ramstage.c | 21 ++++------ 2 files changed, 24 insertions(+), 60 deletions(-) diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 7c20b258e2..bcc8eca962 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014-2016 Intel Corporation - * Copyright (C) 2018 Eltan B.V. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -52,10 +52,7 @@ void raminit(struct romstage_params *params) VPD_DATA_REGION *vpd_ptr; UPD_DATA_REGION *upd_ptr; int fsp_verification_failure = 0; -#if CONFIG(DISPLAY_HOBS) - unsigned long int data; EFI_PEI_HOB_POINTERS hob_ptr; -#endif /* * Find and copy the UPD region to the stack so the platform can modify @@ -139,7 +136,7 @@ void raminit(struct romstage_params *params) fsp_memory = get_next_resource_hob(&fsp_reserved_guid, hob_list_ptr); if (fsp_memory == NULL) { fsp_verification_failure = 1; - printk(BIOS_DEBUG, + printk(BIOS_ERR, "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); } else { fsp_reserved_bytes = fsp_memory->ResourceLength; @@ -190,64 +187,36 @@ void raminit(struct romstage_params *params) if (memory_info_hob == NULL) { printk(BIOS_ERR, "FSP_SMBIOS_MEMORY_INFO HOB missing!\n"); fsp_verification_failure = 1; - } else { - printk(BIOS_DEBUG, - "FSP_SMBIOS_MEMORY_INFO HOB: 0x%p\n", - memory_info_hob); } -#if CONFIG(DISPLAY_HOBS) + if (hob_list_ptr == NULL) + die_with_post_code(POST_RAM_FAILURE, + "ERROR - HOB pointer is NULL!\n"); + /* * Verify that FSP is generating the required HOBs: * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0 * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified above * 7.3: FSP_NON_VOLATILE_STORAGE_HOB only produced when - * new NVS data is generated, verified below + * new NVS data is generated, verified below * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified above * 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit * FSP_SMBIOS_MEMORY_INFO HOB verified above */ - if (cbmem_root != NULL) { - printk(BIOS_DEBUG, - "7.4: FSP_BOOTLOADER_TOLUM_HOB: 0x%p\n", - cbmem_root); - data = cbmem_root->PhysicalStart; - printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data); - data = cbmem_root->ResourceLength; - printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data); - } hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr); - if (hob_ptr.Raw == NULL) { - if (params->saved_data == NULL) { - printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n"); - fsp_verification_failure = 1; - } - } else { - printk(BIOS_DEBUG, - "7.3: FSP_NON_VOLATILE_STORAGE_HOB: 0x%p\n", - hob_ptr.Raw); - } - if (fsp_memory != NULL) { - printk(BIOS_DEBUG, - "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB: 0x%p\n", - fsp_memory); - data = fsp_memory->PhysicalStart; - printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data); - data = fsp_memory->ResourceLength; - printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data); + if ((hob_ptr.Raw == NULL) && (params->saved_data == NULL)) { + printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n"); + fsp_verification_failure = 1; } /* Verify all the HOBs are present */ if (fsp_verification_failure) - printk(BIOS_DEBUG, + printk(BIOS_ERR, "ERROR - Missing one or more required FSP HOBs!\n"); /* Display the HOBs */ - if (hob_list_ptr != NULL) + if (CONFIG(DISPLAY_HOBS)) print_hob_type_structure(0, hob_list_ptr); - else - printk(BIOS_ERR, "ERROR - HOB pointer is NULL!\n"); -#endif /* Get the address of the CBMEM region for the FSP reserved memory */ fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); @@ -258,7 +227,7 @@ void raminit(struct romstage_params *params) if ((fsp_memory != NULL) && (cbmem_root != NULL) && (cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart)) { fsp_verification_failure = 1; - printk(BIOS_DEBUG, + printk(BIOS_ERR, "ERROR - FSP reserved memory above CBMEM root!\n"); } @@ -267,13 +236,13 @@ void raminit(struct romstage_params *params) (fsp_memory->PhysicalStart != (unsigned int)fsp_reserved_memory_area))) { fsp_verification_failure = 1; - printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n"); + printk(BIOS_ERR, "ERROR - Reserving FSP memory area!\n"); #if CONFIG(HAVE_SMI_HANDLER) if (cbmem_root != NULL) { size_t delta_bytes = (unsigned int)smm_base - cbmem_root->PhysicalStart - cbmem_root->ResourceLength; - printk(BIOS_DEBUG, + printk(BIOS_ERR, "0x%08x: Chipset reserved bytes reported by FSP\n", (unsigned int)delta_bytes); die_with_post_code(POST_INVALID_VENDOR_BINARY, @@ -292,7 +261,7 @@ void raminit(struct romstage_params *params) /* Locate the memory configuration data to speed up the next reboot */ mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr); - if (mrc_hob == NULL) + if ((mrc_hob == NULL) && CONFIG(DISPLAY_HOBS)) printk(BIOS_DEBUG, "Memory Configuration Data Hob not present\n"); else if (!vboot_recovery_mode_enabled()) { diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 814bddf007..52a886ce30 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -52,19 +52,16 @@ static void smm_memory_map(void) static void display_hob_info(FSP_INFO_HEADER *fsp_info_header) { const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID; - int missing_hob = 0; void *hob_list_ptr = get_hob_list(); - if (!CONFIG(DISPLAY_HOBS)) - return; - /* Verify the HOBs */ if (hob_list_ptr == NULL) { - printk(BIOS_INFO, "ERROR - HOB pointer is NULL!\n"); + printk(BIOS_ERR, "ERROR - HOB pointer is NULL!\n"); return; } - print_hob_type_structure(0, hob_list_ptr); + if (CONFIG(DISPLAY_HOBS)) + print_hob_type_structure(0, hob_list_ptr); /* * Verify that FSP is generating the required HOBs: @@ -77,14 +74,12 @@ static void display_hob_info(FSP_INFO_HEADER *fsp_info_header) * FSP_SMBIOS_MEMORY_INFO HOB verified by raminit */ if ((fsp_info_header->ImageAttribute & GRAPHICS_SUPPORT_BIT) && - !get_next_guid_hob(&graphics_info_guid, hob_list_ptr)) { - printk(BIOS_INFO, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n"); - missing_hob = 1; - } - - if (missing_hob) - printk(BIOS_INFO, + !get_next_guid_hob(&graphics_info_guid, hob_list_ptr) && + CONFIG(DISPLAY_HOBS)) { + printk(BIOS_ERR, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n"); + printk(BIOS_ERR, "ERROR - Missing one or more required FSP HOBs!\n"); + } } void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) From 2e31ea05bb2c88913310d20a9baaa83e8934da52 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 2 Jul 2019 17:50:59 -0600 Subject: [PATCH 159/231] util/cbfstool: Close file on error Prevents a resource leak. Change-Id: I032227228c8e37e989960ad6292ded39b81835a9 Signed-off-by: Jacob Garber Found-by: Coverity CID 1383919 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33992 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/cbfstool/partitioned_file.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/partitioned_file.c b/util/cbfstool/partitioned_file.c index 9abd32aab6..a2d9ddfee2 100644 --- a/util/cbfstool/partitioned_file.c +++ b/util/cbfstool/partitioned_file.c @@ -197,8 +197,10 @@ partitioned_file_t *partitioned_file_reopen(const char *filename, const struct fmap_area *fmap_fmap_entry = fmap_find_area(file->fmap, SECTION_NAME_FMAP); - if (!fmap_fmap_entry) + if (!fmap_fmap_entry) { + partitioned_file_close(file); return NULL; + } if ((long)fmap_fmap_entry->offset != fmap_region_offset) { ERROR("FMAP's '%s' section doesn't point back to FMAP start (did something corrupt this file?)\n", From 3dbaf4f33646dc2e0ae9aaa8f4c8570d50a04c27 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 2 Jul 2019 12:39:16 -0600 Subject: [PATCH 160/231] util/romcc: Correct format specifiers The right specifier for printing ptrdiff_t is %td. Change-Id: I7bae4d47f15cfe85ca870f687c6f702339f680bb Signed-off-by: Jacob Garber Found-by: Coverity CID 14021{64,68,76} Reviewed-on: https://review.coreboot.org/c/coreboot/+/33984 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- util/romcc/romcc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 2a158e5fe0..378bfc50f2 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -19873,7 +19873,7 @@ static int color_graph(struct compile_state *state, struct reg_state *rstate) else { return 1; } - cgdebug_printf(state, " %d\n", range - rstate->lr); + cgdebug_printf(state, " %td\n", range - rstate->lr); range->group_prev = 0; for(edge = range->edges; edge; edge = edge->next) { struct live_range *node; @@ -19891,7 +19891,7 @@ static int color_graph(struct compile_state *state, struct reg_state *rstate) if (&node->group_next == rstate->high_tail) { rstate->high_tail = node->group_prev; } - cgdebug_printf(state, "Moving...%d to low\n", node - rstate->lr); + cgdebug_printf(state, "Moving...%td to low\n", node - rstate->lr); node->group_prev = rstate->low_tail; node->group_next = 0; *rstate->low_tail = node; @@ -19904,7 +19904,7 @@ static int color_graph(struct compile_state *state, struct reg_state *rstate) } colored = color_graph(state, rstate); if (colored) { - cgdebug_printf(state, "Coloring %d @", range - rstate->lr); + cgdebug_printf(state, "Coloring %td @", range - rstate->lr); cgdebug_loc(state, range->defs->def); cgdebug_flush(state); colored = select_free_color(state, rstate, range); @@ -20198,7 +20198,7 @@ static void allocate_registers(struct compile_state *state) */ if ((range->degree < regc_max_size(state, range->classes)) || (range->color != REG_UNSET)) { - cgdebug_printf(state, "Lo: %5d degree %5d%s\n", + cgdebug_printf(state, "Lo: %5td degree %5d%s\n", range - rstate.lr, range->degree, (range->color != REG_UNSET) ? " (colored)": ""); *range->group_prev = range->group_next; @@ -20215,7 +20215,7 @@ static void allocate_registers(struct compile_state *state) next = point; } else { - cgdebug_printf(state, "hi: %5d degree %5d%s\n", + cgdebug_printf(state, "hi: %5td degree %5d%s\n", range - rstate.lr, range->degree, (range->color != REG_UNSET) ? " (colored)": ""); } From 967f862e47e26cd07b6b43eda6e1445f58e8989b Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Tue, 2 Jul 2019 10:35:10 -0600 Subject: [PATCH 161/231] util/amdfwtool: Close file descriptor on error Prevents a resource leak. Change-Id: Id5da2df3e37cba499cd2e9a7c3ede34e4de2ed77 Signed-off-by: Jacob Garber Found-by: Coverity CID 1402139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33961 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- util/amdfwtool/amdfwtool.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 37dbcd093f..e8ac0b1ae9 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -566,11 +566,13 @@ static ssize_t copy_blob(void *dest, const char *src_file, size_t room) if (fstat(fd, &fd_stat)) { printf("fstat error: %s\n", strerror(errno)); + close(fd); return -2; } if (fd_stat.st_size > room) { printf("Error: %s will not fit. Exiting.\n", src_file); + close(fd); return -3; } From 15947182fde54bbc3c4faba780a515d8b63bce7f Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Thu, 13 Jun 2019 16:34:54 -0600 Subject: [PATCH 162/231] sb/nvidia/ck804: Remove old debugging code These printk() statements were added in commit cdc526e582 (southbridge/nvidia/ck804: Fix boot hang on ASUS KFSN4-DRE w/ K8 CPU) when debugging another issue. They have undefined reads if ck804_num is 0 and aren't needed anymore, so drop them. Change-Id: I80b775370ac6485958948f0bff4510755a6cd2b8 Signed-off-by: Jacob Garber Found-by: Coverity CID 137058{1,3} Reviewed-on: https://review.coreboot.org/c/coreboot/+/33459 Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/southbridge/nvidia/ck804/early_setup_car.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 156c38745b..e7a06f9dc7 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -355,11 +355,8 @@ static int ck804_early_setup_x(void) } } - printk(BIOS_DEBUG, "ck804_early_set_port(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); ck804_early_set_port(ck804_num, busn, io_base); - printk(BIOS_DEBUG, "ck804_early_setup(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); ck804_early_setup(ck804_num, busn, io_base); - printk(BIOS_DEBUG, "ck804_early_clear_port(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); ck804_early_clear_port(ck804_num, busn, io_base); return set_ht_link_ck804(4); From 5b9948140f97eceb47ba026d7bad6dfa2a3c483d Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Wed, 10 Jul 2019 11:44:45 -0600 Subject: [PATCH 163/231] console: Correct printing of hexadecimal integers Commit b19946cc62 (console: Remove support for printing extra bases) truncated the digits string to only print integers of up to base 16. However, that string was also used to print the leading 'x' or 'X' for hexadecimal integers and is now too short. Fix this to prevent an out of bounds read. Change-Id: Iab6470cc88f445f074cf7c0b675346b37f3f2375 Signed-off-by: Jacob Garber Found-by: Coverity CID 1402999 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34211 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber Reviewed-by: Julius Werner --- src/console/vtxprintf.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index b50f3987a5..848ad501ce 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -107,7 +107,10 @@ static int number(void (*tx_byte)(unsigned char byte, void *data), call_tx('0'), count++; else if (base == 16) { call_tx('0'), count++; - call_tx(digits[33]), count++; + if (type & LARGE) + call_tx('X'), count++; + else + call_tx('x'), count++; } } if (!(type & LEFT)) { From 10a9432cc2ad77234442bd639194c5a80050854e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 8 Jul 2019 14:49:22 +0530 Subject: [PATCH 164/231] soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timer This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer for better code sharing. Also ported CB:33512 for SPT and ICP PCH. Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/Kconfig | 8 -------- src/soc/intel/common/block/timer/Kconfig | 10 ++++++++++ src/soc/intel/icelake/chip.h | 2 -- src/soc/intel/icelake/espi.c | 11 ----------- src/soc/intel/icelake/fsp_params.c | 4 ++++ src/soc/intel/skylake/chip.c | 3 +++ src/soc/intel/skylake/chip.h | 3 --- src/soc/intel/skylake/chip_fsp20.c | 3 +++ src/soc/intel/skylake/lpc.c | 11 ----------- 9 files changed, 20 insertions(+), 35 deletions(-) diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index fed7f02dc6..4235b7a0ce 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -316,14 +316,6 @@ config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT Setting non-zero value will allow to use DBC or DCI to debug SOC. PlatformDebugConsent in FspmUpd.h has the details. -config USE_LEGACY_8254_TIMER - bool "Use Legacy 8254 Timer" - default y if PAYLOAD_SEABIOS - default n - help - This sets the Enable8254ClockGating UPD, which according to the FSP Integration - guide needs to be disabled in order to boot SeaBIOS, but should otherwise be enabled. - config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xe00 diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig index a4150459aa..a214ef016b 100644 --- a/src/soc/intel/common/block/timer/Kconfig +++ b/src/soc/intel/common/block/timer/Kconfig @@ -2,3 +2,13 @@ config SOC_INTEL_COMMON_BLOCK_TIMER bool help Intel Processor common TIMER support + +config USE_LEGACY_8254_TIMER + bool "Use Legacy 8254 Timer" + default y if PAYLOAD_SEABIOS || VGA_ROM_RUN + default n + help + This sets the FSP UPD to enable Legacy 8254 clock gating. As per + the FSP Integration guide Legacy 8254 timer clock gating UPD needs + to be disabled in order to boot SeaBIOS or run OpRom, + but should otherwise be enabled. diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 028f6b2c31..72596c46e2 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -204,8 +204,6 @@ struct soc_intel_icelake_config { /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; - /* Statically clock gate 8254 PIT. */ - uint8_t clock_gate_8254; /* Enable C6 DRAM */ uint8_t enable_c6dram; /* diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index a4b6d80aa9..a98821c903 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -199,16 +199,6 @@ static void pch_misc_init(void) outb((1 << 7), 0x70); }; -static void clock_gate_8254(const struct device *dev) -{ - const config_t *config = dev->chip_info; - - if (!config->clock_gate_8254) - return; - - itss_clock_gate_8254(); -} - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ @@ -229,7 +219,6 @@ void lpc_soc_init(struct device *dev) soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); - clock_gate_8254(dev); soc_mirror_dmi_pcr_io_dec(); } diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 8b65a89731..03b00d94fb 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -124,6 +124,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGatingOnS3 = 1; + /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 7f28340ba4..7fbe9e519c 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -237,6 +237,9 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->SlowSlewRateForSa = config->SlowSlewRateForSa; params->FastPkgCRampDisable = config->FastPkgCRampDisable; + /* Legacy 8254 timer support */ + params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER; + soc_irq_settings(params); } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 9c8e2bfaa9..da941dc643 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -513,9 +513,6 @@ struct soc_intel_skylake_config { /* Enable/Disable host reads to PMC XRAM registers */ u8 PchPmPmcReadDisable; - /* Statically clock gate 8254 PIT. */ - u8 clock_gate_8254; - /* * Use SD card detect GPIO with default config: * - Edge triggered diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 08f5d79349..a1fced293d 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -315,6 +315,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + /* Legacy 8254 timer support */ + params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER; + memcpy(params->SerialIoDevMode, config->SerialIoDevMode, sizeof(params->SerialIoDevMode)); diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 8d6228c096..d8e5ccc6c0 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -96,16 +96,6 @@ static const struct reg_script pch_misc_init_script[] = { REG_SCRIPT_END }; -static void clock_gate_8254(struct device *dev) -{ - const config_t *config = dev->chip_info; - - if (!config->clock_gate_8254) - return; - - itss_clock_gate_8254(); -} - void lpc_soc_init(struct device *dev) { const config_t *const config = dev->chip_info; @@ -125,5 +115,4 @@ void lpc_soc_init(struct device *dev) soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); - clock_gate_8254(dev); } From b8501c7c5f00a664ff644324af363d43c5af1bc2 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 9 Jul 2019 14:22:46 -0700 Subject: [PATCH 165/231] mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L) HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since it needs to trigger on both edges. With GPIO IRQ, it is necessary to configure the trigger type in coreboot to match the ACPI configuration. This is because: 1. ACPI configuration is used by intel-pinctrl driver in Linux kernel to re-configure the trigger type for the pad in GPIO DW0 config register. This is done when kernel driver probes and requests irq for its device. 2. On resume from S3, the pad configuration gets reset and coreboot sets the trigger type to LEVEL. However, kernel driver does not probe again. This results in the trigger type being configured incorrectly. This change updates the GPIO configuration for GPP_H0 to set the same trigger type as advertised in ACPI for the kernel. BUG=b:132672011 TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0 works fine on boot as well as after suspend/resume. Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/34181 Reviewed-by: Paul Fagerburg Reviewed-by: Tim Wawrzynczak Reviewed-by: Sathya Prakash M R Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/baseboard/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 1da3d756e2..a466972048 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -329,7 +329,7 @@ static const struct pad_config gpio_table[] = { /* * H0 : HP_INT_L */ - PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, LEVEL), + PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, EDGE_BOTH), /* H1 : CNV_RF_RESET_L */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* H2 : CNV_CLKREQ0 */ From 1ceac4efcfa3a9ccc0d44f77855f4949f59305b5 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 9 Jul 2019 14:27:28 -0700 Subject: [PATCH 166/231] soc/intel/common: Check bios_size and window_size after MIN operation Clang Static Analyzer version 8.0.0 detects that the result of log2_ceil(bios_size) and log2_ceil(window_size) is undefined if the value of bios_size and window_size are negative. Add negative value Check for bios_size and window_size after MIN operation. Change-Id: I28577b6e0ba0ab45bb7804c17ba1f26c4b078b15 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/34182 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/common/block/fast_spi/fast_spi.c | 2 +- src/soc/intel/common/block/lpc/lpc_lib.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index e40b84493e..5c29addcc9 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -241,7 +241,7 @@ void fast_spi_cache_bios_region(void) * protection, so limit the cached bios region to be no more than 16MB. * */ bios_size = MIN(bios_size, 16 * MiB); - if (!bios_size) + if (bios_size <= 0) return; /* Round to power of two */ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index b31c799a6a..975e4300bf 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -80,7 +80,7 @@ void lpc_open_pmio_window(uint16_t base, uint16_t size) /* Each IO range register can only open a 256-byte window. */ window_size = MIN(size, LPC_LGIR_MAX_WINDOW_SIZE); - if (!window_size) + if (window_size <= 0) return; /* Window size must be a power of two for the AMASK to work. */ From 565b0aada93a0ef40b022b9b78b1bcefdf5193bb Mon Sep 17 00:00:00 2001 From: Lean Sheng Tan Date: Mon, 27 May 2019 13:36:31 +0800 Subject: [PATCH 167/231] mb/intel/coffeelake_rvp: Add cpu count for CFL S62 Increases CPU max core count to 16 for coffeelake Refresh-S Platform. TEST: boot to linux OS on CFL-S refresh Intel RVP and verified the output of cat /proc/cpuinfo shows no of processor=16. Signed-off-by: Lean Sheng Tan Change-Id: I579ff6ae8227844741406c503d3994408ec2b617 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34156 Reviewed-by: Boon Tiong Teo Reviewed-by: Furquan Shaikh Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/intel/coffeelake_rvp/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index e75fe2ab6d..13e55b3f93 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -53,7 +53,8 @@ config CHROMEOS config MAX_CPUS int - default 12 if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 + default 12 if BOARD_INTEL_COFFEELAKE_RVP11 + default 16 if BOARD_INTEL_COFFEELAKE_RVP8 default 8 config UART_FOR_CONSOLE From 20cfc87ca07ce1ac07c47480e1a6a5bc0a1e1090 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 9 Jul 2019 13:39:44 -0600 Subject: [PATCH 168/231] soc/intel/cannonlake: Make EC S0ix notification optional in LPIT Only call the \_SB.PCI0.LPCB.EC0.S0IX method if it exists. Change-Id: Idf465f8ad7cb016f3ad3d9710b46e35f66f8939b Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/34178 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Furquan Shaikh Reviewed-by: Shaunak Saha Reviewed-by: Duncan Laurie Reviewed-by: Subrata Banik --- src/soc/intel/cannonlake/acpi/lpit.asl | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index 93bce2644e..74d4fe6396 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -15,6 +15,7 @@ */ External(\_SB.MS0X, MethodObj) +External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj) scope(\_SB) { @@ -34,7 +35,7 @@ scope(\_SB) ) } /* - * Function 1. + * Function 1 - Get Device Constraints */ If(Arg2 == 1) { Return(Package(5) { @@ -42,7 +43,7 @@ scope(\_SB) ) } /* - * Function 2. + * Function 2 - Get Crash Dump Device */ If(Arg2 == 2) { Return(Buffer(One) { @@ -50,30 +51,38 @@ scope(\_SB) ) } /* - * Function 3. + * Function 3 - Display Off Notification */ If(Arg2 == 3) { } /* - * Function 4. + * Function 4 - Display On Notification */ If(Arg2 == 4) { } /* - * Function 5. + * Function 5 - Low Power S0 Entry Notification */ If(Arg2 == 5) { - \_SB.PCI0.LPCB.EC0.S0IX(1) + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(1) + } + /* provide board level s0ix hook */ If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X(1) } } /* - * Function 6. + * Function 6 - Low Power S0 Exit Notification */ If(Arg2 == 6) { - \_SB.PCI0.LPCB.EC0.S0IX(0) + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(0) + } + /* provide board level s0ix hook */ If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X(0) From 145748bf25b658da1d2951201413ba9b0c68a266 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 9 Jul 2019 13:33:04 -0600 Subject: [PATCH 169/231] mb/google/hatch: Disable GPIO community dynamic clock gating The dynamic clock gating is causing boards to miss interrupts whose pulses are shorter than 4us. Disable it using FSP UPDs. BUG=b:130764684 BRANCH=none TEST=Compiles Change-Id: I8f1ec8f7c31192bce2a761ec99b86638435dc27c Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/34176 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Furquan Shaikh Reviewed-by: Evan Green Reviewed-by: Subrata Banik --- .../google/hatch/variants/baseboard/devicetree.cb | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 9a9125396c..a4700321a4 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -95,12 +95,12 @@ chip soc/intel/cannonlake register "gpio_override_pm" = "1" # GPIO community PM configuration - register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - # Disable clock gating on this community so that cr50's short irq - # pulses won't be missed. + # Disable dynamic clock gating; with bits 0-5 set in these registers, + # some short interrupt pulses were missed (esp. cr50 irq) + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" device cpu_cluster 0 on From 489c722dccbf7b57cab6f1b0e17a14e889d9da4e Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 9 Jul 2019 13:30:30 -0600 Subject: [PATCH 170/231] mb/google/hatch: Enable LPIT inclusion in DSDT Include the lpit.asl file in Hatch's DSDT definition. BUG=b:130764684 BRANCH=none TEST=S3 suspend/resume and S0ix entry/exit work correctly. Ran > 200 iterations of suspend_stress_test and no issues found. Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/34175 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Subrata Banik Reviewed-by: Paul Fagerburg --- src/mainboard/google/hatch/dsdt.asl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 243c6270e2..87e98ea925 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -51,6 +51,9 @@ DefinitionBlock( /* Chipset specific sleep states */ #include + /* Low power idle table */ + #include + /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { From 69d73e4d75f3a133a7307f2daea8773ec7038af5 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 9 Jul 2019 13:35:11 -0600 Subject: [PATCH 171/231] soc/intel/intelblocks/gpio: Always expose GPIO PM constants These constants are needed in some ASL files, even when __ACPI__ is defined. Change-Id: I0f4f00b93d5d45794b7c9e0f72b51f3191eb3902 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/34177 Reviewed-by: Lance Zhao Reviewed-by: Subrata Banik Reviewed-by: Paul Fagerburg Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/include/intelblocks/gpio.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index a2cccc7cd2..9b351a938f 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -20,9 +20,6 @@ #include #include "gpio_defs.h" -#ifndef __ACPI__ -#include - /* GPIO community IOSF sideband clock gating */ #define MISCCFG_GPSIDEDPCGEN (1 << 5) /* GPIO community RCOMP clock gating */ @@ -40,6 +37,9 @@ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN) +#ifndef __ACPI__ +#include + /* * GPIO numbers may not be contiguous and instead will have a different * starting pin number for each pad group. From a17242577add6dfd54d1ff8d0e46958b758e3718 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 10 Jul 2019 09:12:05 -0600 Subject: [PATCH 172/231] soc/intel/cannonlake: Add GPID and CGPM methods to GPIO ASL The GPID method returns the PCR Port ID of the given GPIO community. The CGPM method alters the given GPIO community's PM bits, given in Arg1. Change-Id: I098ee08573eb4f8a45d9b5ae84f2d85ce525c9b8 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/34179 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/acpi/gpio.asl | 50 ++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index 9df1cf7d42..65332ad7c0 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -16,6 +16,7 @@ #include #include #include +#include #include "gpio_op.asl" Device (GPIO) @@ -107,3 +108,52 @@ Method (GADD, 1, NotSerialized) Add (Local2, PAD_CFG_BASE, Local2) Return (Add (Local2, Multiply (Local1, 16))) } + +/* + * Return PCR Port ID of GPIO Communities + * + * Arg0: GPIO Community (0-4) + */ +Method (GPID, 1, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (0) { + Store (PID_GPIOCOM0, Local0) + } + Case (1) { + Store (PID_GPIOCOM1, Local0) + } + Case (2) { + Store (PID_GPIOCOM2, Local0) + } + Case (3) { + Store (PID_GPIOCOM3, Local0) + } + Case (4) { + Store (PID_GPIOCOM4, Local0) + } + Default { + Return (0) + } + } + + Return (Local0) +} + +/* + * Configure GPIO Power Management bits + * + * Arg0: GPIO community (0-4) + * Arg1: PM bits in MISCCFG + */ +Method (CGPM, 2, Serialized) +{ + Store (GPID (Arg0), Local0) + If (LNotEqual (Local0, 0)) { + /* Mask off current PM bits */ + PCRA (Local0, GPIO_MISCCFG, Not (MISCCFG_ENABLE_GPIO_PM_CONFIG)) + /* Mask in requested bits */ + PCRO (Local0, GPIO_MISCCFG, And (Arg1, MISCCFG_ENABLE_GPIO_PM_CONFIG)) + } +} From c5651568ea63aedc92669c5447c0c9755e726244 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 10 Jul 2019 09:13:55 -0600 Subject: [PATCH 173/231] mb/google/hatch: Enable/disable GPIO clock gating Before the system enters S0ix or S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off. BUG=b:130764684 BRANCH=none TEST=Used dut-power to verify that the clock gating is enabled in S0ix and S3. Also used Store(..., Debug) statements in the ASL code to verify it was getting called. Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/dsdt.asl | 3 ++ src/mainboard/google/hatch/mainboard.asl | 57 ++++++++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 src/mainboard/google/hatch/mainboard.asl diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 87e98ea925..e2959a788a 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -41,6 +41,9 @@ DefinitionBlock( #include #include } + + /* Mainboard hooks */ + #include "mainboard.asl" } #if CONFIG(CHROMEOS) diff --git a/src/mainboard/google/hatch/mainboard.asl b/src/mainboard/google/hatch/mainboard.asl new file mode 100644 index 0000000000..dff1a75959 --- /dev/null +++ b/src/mainboard/google/hatch/mainboard.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +Method (LOCL, 1, Serialized) +{ + For (Local0 = 0, Local0 < 5, Local0++) + { + \_SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + LOCL (0) +} + +/* + * S0ix Entry/Exit Notifications + * Called from \_SB.LPID._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* S0ix Entry */ + LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) + } Else { + /* S0ix Exit */ + LOCL (0) + } +} From 125b48d1d59b4732c0580e982d925f41fefaf2cd Mon Sep 17 00:00:00 2001 From: Frank_Chu Date: Tue, 2 Jul 2019 11:13:56 +0800 Subject: [PATCH 174/231] mb/google/hatch/variants: Fix nonworking touch pad Correct ELAN Touch pad IRQ GPIO to GPP_A21 BUG=b:135507215 BRANCH=none TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Frank_Chu Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33954 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/helios/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 405f85f210..3f71c99db1 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -72,7 +72,7 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A20_IRQ)" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" device i2c 15 on end end From ff423f749a5c74f6a4dda59b996fcbed72c94e94 Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Mon, 9 Apr 2018 12:30:34 -0700 Subject: [PATCH 175/231] sdm845: Add AOP firmware support TEST=build & run Change-Id: I9845c8638e4b905de5d6985dc9f1fddd8b1a8942 Signed-off-by: T Michael Turney Reviewed-on: https://review.coreboot.org/c/coreboot/+/25210 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/soc/qualcomm/sdm845/Makefile.inc | 3 ++ src/soc/qualcomm/sdm845/aop_load_reset.c | 43 +++++++++++++++++++ src/soc/qualcomm/sdm845/clock.c | 8 +++- .../qualcomm/sdm845/include/soc/addressmap.h | 1 - src/soc/qualcomm/sdm845/include/soc/aop.h | 21 +++++++++ src/soc/qualcomm/sdm845/include/soc/clock.h | 6 --- .../qualcomm/sdm845/include/soc/memlayout.ld | 16 +++++++ src/soc/qualcomm/sdm845/include/soc/symbols.h | 2 + src/soc/qualcomm/sdm845/mmu.c | 5 +++ src/soc/qualcomm/sdm845/soc.c | 3 +- 10 files changed, 98 insertions(+), 10 deletions(-) create mode 100644 src/soc/qualcomm/sdm845/aop_load_reset.c create mode 100644 src/soc/qualcomm/sdm845/include/soc/aop.h diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc index 78b3568a8b..c20be142b6 100644 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -39,6 +39,9 @@ ramstage-y += gpio.c ramstage-y += clock.c ramstage-$(CONFIG_SDM845_QSPI) += qspi.c ramstage-y += usb.c +ramstage-y += gpio.c +ramstage-y += clock.c +ramstage-y += aop_load_reset.c ################################################################################ diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c new file mode 100644 index 0000000000..02217f9bd3 --- /dev/null +++ b/src/soc/qualcomm/sdm845/aop_load_reset.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void aop_fw_load_reset(void) +{ + bool aop_fw_entry; + + struct prog aop_fw_prog = + PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop"); + + if (prog_locate(&aop_fw_prog)) + die("SOC image: AOP_FW not found"); + + aop_fw_entry = selfload(&aop_fw_prog); + if (!aop_fw_entry) + die("SOC image: AOP load failed"); + + clock_reset_aop(); + + printk(BIOS_DEBUG, "\nSOC:AOP brought out of reset.\n"); +} diff --git a/src/soc/qualcomm/sdm845/clock.c b/src/soc/qualcomm/sdm845/clock.c index addac5ef40..e55495b86e 100644 --- a/src/soc/qualcomm/sdm845/clock.c +++ b/src/soc/qualcomm/sdm845/clock.c @@ -17,10 +17,13 @@ #include #include #include +#include #include #define DIV(div) (2*div - 1) +#define AOP_LOADED_SIGNAL_FLAG 0x11223344 + struct clock_config qup_cfg[] = { { .hz = 7372800, @@ -146,9 +149,10 @@ static int clock_enable(void *cbcr_addr) void clock_reset_aop(void) { - /* Bring AOP out of RESET */ - clrbits_le32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT)); + uint32_t *mailbox; + mailbox = (uint32_t *)_aop_ss_msg_ram_drv15; + *mailbox = AOP_LOADED_SIGNAL_FLAG; } void clock_configure_qspi(uint32_t hz) diff --git a/src/soc/qualcomm/sdm845/include/soc/addressmap.h b/src/soc/qualcomm/sdm845/include/soc/addressmap.h index bf4b30b32b..70caa169aa 100644 --- a/src/soc/qualcomm/sdm845/include/soc/addressmap.h +++ b/src/soc/qualcomm/sdm845/include/soc/addressmap.h @@ -23,7 +23,6 @@ #define TLMM_NORTH_TILE_BASE 0x03900000 #define TLMM_SOUTH_TILE_BASE 0x03D00000 #define GCC_BASE 0x00100000 -#define AOSS_CC_BASE 0x0C2F0000 /* * USB BASE ADDRESSES diff --git a/src/soc/qualcomm/sdm845/include/soc/aop.h b/src/soc/qualcomm/sdm845/include/soc/aop.h new file mode 100644 index 0000000000..cadf21b7bd --- /dev/null +++ b/src/soc/qualcomm/sdm845/include/soc/aop.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SDM845_AOP_H__ +#define _SOC_QUALCOMM_SDM845_AOP_H__ + +void aop_fw_load_reset(void); + +#endif // _SOC_QUALCOMM_SDM845_AOP_H__ diff --git a/src/soc/qualcomm/sdm845/include/soc/clock.h b/src/soc/qualcomm/sdm845/include/soc/clock.h index ea4d87d812..1f79d95195 100644 --- a/src/soc/qualcomm/sdm845/include/soc/clock.h +++ b/src/soc/qualcomm/sdm845/include/soc/clock.h @@ -123,11 +123,6 @@ check_member(sdm845_gcc, usb3_phy_sec_bcr, 0x5000c); check_member(sdm845_gcc, usb3phy_phy_sec_bcr, 0x50010); check_member(sdm845_gcc, apcs_clk_br_en1, 0x5200c); -struct sdm845_aoss { - u8 _res[0x2c]; - u32 aoss_cc_apcs_misc; -}; - enum clk_ctl_gpll_user_ctl { CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2, CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0, @@ -201,7 +196,6 @@ struct clock_config { }; static struct sdm845_gcc *const gcc = (void *)GCC_BASE; -static struct sdm845_aoss *const aoss = (void *)AOSS_CC_BASE; void clock_init(void); void clock_reset_aop(void); diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index b1b633317f..b0d2d43f4b 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -24,8 +24,24 @@ #define BSRAM_START(addr) SYMBOL(bsram, addr) #define BSRAM_END(addr) SYMBOL(ebsram, addr) +/* AOP : 0x0B000000 - 0x0B100000 */ +#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) +#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) + +/* AOPMSG : 0x0C300000 - 0x0C400000 */ +#define AOPMSG_START(addr) SYMBOL(aopmsg, addr) +#define AOPMSG_END(addr) SYMBOL(eaopmsg, addr) + SECTIONS { + AOPSRAM_START(0x0B000000) + REGION(aop, 0x0B000000, 0x100000, 4096) + AOPSRAM_END(0x0B100000) + + AOPMSG_START(0x0C300000) + REGION(aop_ss_msg_ram_drv15, 0x0C3F0000, 0x400, 0x100) + AOPMSG_END(0x0C400000) + SSRAM_START(0x14680000) OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) DMA_COHERENT(0x14699000, 8K) diff --git a/src/soc/qualcomm/sdm845/include/soc/symbols.h b/src/soc/qualcomm/sdm845/include/soc/symbols.h index e7bf1b2aea..f01f245a92 100644 --- a/src/soc/qualcomm/sdm845/include/soc/symbols.h +++ b/src/soc/qualcomm/sdm845/include/soc/symbols.h @@ -24,5 +24,7 @@ DECLARE_REGION(dram_reserved) DECLARE_REGION(dcb); DECLARE_REGION(pmic); DECLARE_REGION(limits_cfg); +DECLARE_REGION(aop); +DECLARE_REGION(aop_ss_msg_ram_drv15); #endif // _SOC_QUALCOMM_SDM845_SYMBOLS_H_ diff --git a/src/soc/qualcomm/sdm845/mmu.c b/src/soc/qualcomm/sdm845/mmu.c index ec5fa55de2..e63bfed690 100644 --- a/src/soc/qualcomm/sdm845/mmu.c +++ b/src/soc/qualcomm/sdm845/mmu.c @@ -32,3 +32,8 @@ void sdm845_mmu_init(void) mmu_enable(); } + +void soc_mmu_dram_config_post_dram_init(void) +{ + mmu_config_range((void *)_aop, REGION_SIZE(aop), CACHED_RAM); +} diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c index ef283c0eae..14394f78c2 100644 --- a/src/soc/qualcomm/sdm845/soc.c +++ b/src/soc/qualcomm/sdm845/soc.c @@ -18,6 +18,7 @@ #include #include #include +#include static void soc_read_resources(struct device *dev) { @@ -29,7 +30,7 @@ static void soc_read_resources(struct device *dev) static void soc_init(struct device *dev) { - + aop_fw_load_reset(); } static struct device_operations soc_ops = { From 447badd1cfbf70a26f3e6fb0b84d8166dc732bc4 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Tue, 9 Jul 2019 16:38:36 +0800 Subject: [PATCH 176/231] board/kukui: Remove ADC tolerance from boardid The tolerance of ADC is +-10mV, but the resistors may also introduce 1% variation, and causing the final measured voltage to vary around 5%. By the advisory from hardware team, checking the tolerance seems not really solving or helping anything so we should just ignore that and try to find best matched ID (this also aligns to what Gru did). BUG=b:136990271 TEST=Booted on Krane and no longer seeing ADC out of range BRANCH=None Change-Id: Ie02ca5aaafbcfa8f411d973ad0266eee385d6878 Signed-off-by: Hung-Te Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/34161 Reviewed-by: Paul Menzel Reviewed-by: Julius Werner Reviewed-by: Yu-Ping Wu Reviewed-by: You-Cheng Syu Tested-by: build bot (Jenkins) --- src/mainboard/google/kukui/boardid.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index 71f051f312..ad066666cb 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -82,15 +82,7 @@ static uint32_t get_adc_index(unsigned int channel) for (id = 0; id < ADC_LEVELS - 1; id++) if (value < (voltages[id] + voltages[id + 1]) / 2) break; - - /* The last level is NC and may be larger than standard tolerance. */ - const int tolerance = 10000; /* 10,000 uV */ - if (id < ADC_LEVELS - 1 && ABS(value - voltages[id]) > tolerance) { - printk(BIOS_ERR, "ADC channel %u value out of range: %d\n", - channel, value); - assert(0); - } - + printk(BIOS_DEBUG, "ADC[%d]: Raw value=%d ID=%d\n", channel, value, id); return id; } From e13a65c5ffd066272f1a224120bbc5788f56106c Mon Sep 17 00:00:00 2001 From: Tristan Shieh Date: Wed, 10 Jul 2019 15:02:39 +0800 Subject: [PATCH 177/231] mediatek: Fill in input_hertz to coreboot table Set input_hertz to 26 MHz. BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: I7f9c329ae5d610f2516e60f06b2ac96ebbeaa897 Signed-off-by: Tristan Shieh Reviewed-on: https://review.coreboot.org/c/coreboot/+/34191 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/mediatek/common/uart.c | 4 +++- src/soc/mediatek/mt8183/include/soc/pll.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c index 20ec8766c4..8905c55528 100644 --- a/src/soc/mediatek/common/uart.c +++ b/src/soc/mediatek/common/uart.c @@ -20,6 +20,7 @@ #include #include +#include struct mtk_uart { union { @@ -84,7 +85,7 @@ static int mtk_uart_tst_byte(void); static void mtk_uart_init(void) { /* Use a hardcoded divisor for now. */ - const unsigned int uartclk = 26 * MHz; + const unsigned int uartclk = UART_HZ; const unsigned int baudrate = get_uart_baudrate(); const uint8_t line_config = UART8250_LCR_WLS_8; /* 8n1 */ unsigned int highspeed, quot, divisor, remainder; @@ -177,6 +178,7 @@ void uart_fill_lb(void *data) struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = UART0_BASE; + serial.input_hertz = UART_HZ; serial.baud = get_uart_baudrate(); serial.regwidth = 4; lb_add_serial(&serial, data); diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h index 3807e0087e..5a24e75692 100644 --- a/src/soc/mediatek/mt8183/include/soc/pll.h +++ b/src/soc/mediatek/mt8183/include/soc/pll.h @@ -268,6 +268,7 @@ enum { /* top_mux rate */ enum { SPI_HZ = MAINPLL_D5_D2_HZ, + UART_HZ = CLK26M_HZ, }; enum { From badbcde5425b587fe23f8bd6ce02c740913fdd1d Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Wed, 10 Jul 2019 15:55:24 +0800 Subject: [PATCH 178/231] google/kukui: Adjust LCM ID voltages Currently some of the LCM ID voltage gaps are below 100mV. For example, the voltage difference between ID 2 and 3 is 503-440=63mV. To reduce the risk of misrecognition from the hardware level, the voltages are adjusted so that all the voltage gaps are larger than 100mV. The RD2 resistor values are also updated. BUG=b:136987483 TEST=emerge-kukui coreboot Change-Id: Ib5c1f927fb54d8c9579f030e42eeec5a27daaceb Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/34192 Reviewed-by: You-Cheng Syu Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/mainboard/google/kukui/boardid.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index ad066666cb..ad7fb364df 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -51,15 +51,15 @@ static const int lcm_voltages[ADC_LEVELS] = { /* ID : Voltage (unit: uV) */ /* 0 : */ 0, /* 1 : */ 283000, - /* 2 : */ 440000, + /* 2 : */ 394000, /* 3 : */ 503000, /* 4 : */ 608000, - /* 5 : */ 703000, - /* 6 : */ 830000, - /* 7 : */ 865000, - /* 8 : */ 953000, - /* 9 : */ 1079000, - /* 10 : */ 1128000, + /* 5 : */ 712000, + /* 6 : */ 823000, + /* 7 : */ 937000, + /* 8 : */ 1046000, + /* 9 : */ 1155000, + /* 10 : */ 1277000, /* 11 : */ 1434000, }; From 1f21a96c842c285308fd0b433a578ce101483aa1 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Wed, 10 Jul 2019 13:15:54 +0200 Subject: [PATCH 179/231] mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed mode We need to reduce the eMMC bus speed for these Apollo Lake mainboards because of a limitation on Intel side for industry use cases. Change-Id: Ide6a1a302001c0752d149bfdab175a27c8f8cc35 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/34196 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb | 2 +- src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb | 2 +- src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb | 2 +- src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb | 2 +- src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index 55e610565f..d65ac4e0a4 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -44,7 +44,7 @@ chip soc/intel/apollolake register "emmc_rx_cmd_data_cntl2" = "0x10008" # 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index a627e3e4aa..bee531f2fa 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -45,7 +45,7 @@ chip soc/intel/apollolake register "emmc_rx_cmd_data_cntl2" = "0x10008" # 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1" # Enable Vtd feature register "enable_vtd" = "1" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index a03f3836ac..e1e79b44ae 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -44,7 +44,7 @@ chip soc/intel/apollolake register "emmc_rx_cmd_data_cntl2" = "0x10008" # 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1" device domain 0 on device pci 00.0 on end # - Host Bridge diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 50207e0e54..fc9885ce7f 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -45,7 +45,7 @@ chip soc/intel/apollolake register "emmc_rx_cmd_data_cntl2" = "0x10008" # 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1" device domain 0 on device pci 00.0 on end # - Host Bridge diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 5f1c9857d4..3b28a26396 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -44,7 +44,7 @@ chip soc/intel/apollolake register "emmc_rx_cmd_data_cntl2" = "0x10008" # 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1" # Enable Vtd feature register "enable_vtd" = "1" From 6c7857411c9a7572f5bdb29cc6e1ffd01d023cb2 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Wed, 10 Jul 2019 14:34:50 +0200 Subject: [PATCH 180/231] mb/siemens/{baseboard,mc_apl3,mc_apl4,mc_apl5}: Fix GPIO_168 This GPIO is corrected with reference to the Apollo Lake SoC EDS Vol 4 revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be used in Function 0 (GPIO) mode. Change-Id: I98628ade3a1e19730ca6e6b4a63c28e6816176ce Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/34197 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c | 2 +- src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c | 2 +- src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c | 2 +- src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c index 5ca91efece..91a30bfe0e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c @@ -49,7 +49,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */ PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* SDIO_D0 */ /* Configure SDIO to enable power gating. */ - PAD_CFG_GPI(GPIO_168, NONE, DEEP), /* SDIO_D1 */ + PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */ PAD_CFG_GPI(GPIO_169, NONE, DEEP), /* SDIO_D2 */ PAD_CFG_GPI(GPIO_170, NONE, DEEP), /* SDIO_D3 */ PAD_CFG_GPI(GPIO_171, NONE, DEEP), /* SDIO_CMD */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c index acf276c01c..9159ba1b50 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c @@ -49,7 +49,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */ PAD_CFG_GPI(GPIO_167, UP_20K, DEEP), /* SDIO_D0 */ /* Configure SDIO to enable power gating. */ - PAD_CFG_GPI(GPIO_168, UP_20K, DEEP), /* SDIO_D1 */ + PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */ PAD_CFG_GPI(GPIO_169, UP_20K, DEEP), /* SDIO_D2 */ PAD_CFG_GPI(GPIO_170, UP_20K, DEEP), /* SDIO_D3 */ PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c index 2bd56b89da..c7262cad9e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c @@ -47,7 +47,7 @@ static const struct pad_config gpio_table[] = { /* SDIO - unused */ PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), PAD_CFG_GPI(GPIO_167, DN_20K, DEEP), - PAD_CFG_GPI(GPIO_168, DN_20K, DEEP), + PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), PAD_CFG_GPI(GPIO_169, DN_20K, DEEP), PAD_CFG_GPI(GPIO_170, DN_20K, DEEP), PAD_CFG_GPI(GPIO_171, DN_20K, DEEP), diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c index f9b258d199..1fb0c89b78 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c @@ -49,7 +49,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */ PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* SDIO_D0 */ /* Configure SDIO to enable power gating. */ - PAD_CFG_GPI(GPIO_168, NONE, DEEP), /* SDIO_D1 */ + PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */ PAD_CFG_GPI(GPIO_169, NONE, DEEP), /* SDIO_D2 */ PAD_CFG_GPI(GPIO_170, NONE, DEEP), /* SDIO_D3 */ PAD_CFG_GPI(GPIO_171, NONE, DEEP), /* SDIO_CMD */ From b62c1e392bf411a8fbc693efa9d2abf6f7b64d47 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 10 Jul 2019 00:50:43 +0200 Subject: [PATCH 181/231] mb/asus/p8h61-m_pro: Add comment about PCH GPIO46 GPIO46 is wired to a tiny switch on the board labelled "GPU Boost". Since coreboot could make use of it, add a comment about it on gpio.c. Change-Id: I0efa85e6d8235711521b10e56b7c89a25c4b2b7f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/34185 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel --- src/mainboard/asus/p8h61-m_pro/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/p8h61-m_pro/gpio.c b/src/mainboard/asus/p8h61-m_pro/gpio.c index 1cf848f0b1..b1b819eca0 100644 --- a/src/mainboard/asus/p8h61-m_pro/gpio.c +++ b/src/mainboard/asus/p8h61-m_pro/gpio.c @@ -105,7 +105,7 @@ static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio43 = GPIO_MODE_NATIVE, .gpio44 = GPIO_MODE_NATIVE, .gpio45 = GPIO_MODE_NATIVE, - .gpio46 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, /* wired to GPU Boost switch */ .gpio47 = GPIO_MODE_NATIVE, .gpio48 = GPIO_MODE_NATIVE, .gpio49 = GPIO_MODE_GPIO, From e211b9ed59bca44e51b4fa12be03f9393b444b89 Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Mon, 10 Jun 2019 22:50:39 +0530 Subject: [PATCH 182/231] mb/google/hatch: Update AC/DC loadline values Update the AC/DC loadline values for all domains. Using the same values as in arcada. BUG=None BRANCH=None TEST=Build and Boot hatch EVT Change-Id: If8ea48794d11dc68e40e6504c0d46a2b273a8ab6 Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/c/coreboot/+/33371 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar Reviewed-by: Furquan Shaikh --- .../hatch/variants/baseboard/devicetree.cb | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index a4700321a4..6ff90f8d9d 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -47,6 +47,82 @@ chip soc/intel/cannonlake # Unlock GPIO pads register "PchUnlockGpioPads" = "1" + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 70A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(70), + .voltage_limit = 1520, + .ac_loadline = 180, + .dc_loadline = 180, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + register "PchPmSlpS3MinAssert" = "2" # 50ms register "PchPmSlpS4MinAssert" = "1" # 1s register "PchPmSlpSusMinAssert" = "1" # 500ms From b16fda22a423c8315e2347fe4ec8e2ef897fc359 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 10 Jul 2019 13:09:34 +0300 Subject: [PATCH 183/231] cpu/x86: Declare smi_release_lock() static MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I535ff1b16b1fa7c3c8c14b2be7eac32568f16077 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34194 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/cpu/x86/smm/smihandler.c | 2 +- src/include/cpu/x86/smm.h | 4 ---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 0ffa46537c..bc01522291 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -47,7 +47,7 @@ static int smi_obtain_lock(void) return (ret == SMI_UNLOCKED); } -void smi_release_lock(void) +static void smi_release_lock(void) { asm volatile ( "movb %1, %%al\n" diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index ffcc2a1958..3071106080 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -501,10 +501,6 @@ void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); -#if !CONFIG(SMM_TSEG) -void smi_release_lock(void); -#endif - /* This is the SMM handler. */ extern unsigned char _binary_smm_start[]; extern unsigned char _binary_smm_end[]; From 8da51ca2c36f9219a91a48540e673fbd04753345 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 10 Jul 2019 18:20:46 +0530 Subject: [PATCH 184/231] Kconfig: Remove HAVE_RAMSTAGE dependency from RELOCATABLE_RAMSTAGE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CONFIG_RELOCATABLE_RAMSTAGE is something more than ramstage specific kconfig hence its better to remove HAVE_RAMSTAGE dependency till stage_cache cleaner implementation lands here. Change-Id: I3c238d727dc13014e2b77544d05099be95c22bab Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/34198 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index b64fdca4ee..2bb5bfeab0 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -241,7 +241,6 @@ config NO_RELOCATABLE_RAMSTAGE config RELOCATABLE_RAMSTAGE bool - depends on HAVE_RAMSTAGE default !NO_RELOCATABLE_RAMSTAGE select RELOCATABLE_MODULES help From c19d6a6ce59873f2326b14bb4af69048cceb9300 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 4 Jul 2019 21:39:28 +0300 Subject: [PATCH 185/231] device/pci: Replace use of dev_find_slot() for IRQs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I48c0de73338430282ce1a4442bbeb7c867dc174c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34079 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/arch/x86/pirq_routing.c | 2 +- src/device/pci_device.c | 29 ++++++++----------- src/include/device/pci.h | 3 +- .../emulation/qemu-i440fx/mainboard.c | 2 +- src/mainboard/emulation/qemu-q35/mainboard.c | 4 +-- 5 files changed, 17 insertions(+), 23 deletions(-) diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 5f80c9d56c..9d1f5910e9 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -177,7 +177,7 @@ static void pirq_route_irqs(unsigned long addr) } /* Bus, device, slots IRQs for {A,B,C,D}. */ - pci_assign_irqs(bus, devfn >> 3, irq_slot); + pci_assign_irqs(pcidev_path_on_bus(bus, devfn), irq_slot); } for (i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index a2af0ec999..2c724aad50 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1499,27 +1499,24 @@ int get_pci_irq_pins(struct device *dev, struct device **parent_bdg) * * This function should be called for each PCI slot in your system. * - * @param bus Pointer to the bus structure. - * @param slot TODO + * @param dev Pointer to dev structure. * @param pIntAtoD An array of IRQ #s that are assigned to PINTA through PINTD * of this slot. The particular IRQ #s that are passed in depend on the * routing inside your southbridge and on your board. */ -void pci_assign_irqs(unsigned bus, unsigned slot, - const unsigned char pIntAtoD[4]) +void pci_assign_irqs(struct device *dev, const unsigned char pIntAtoD[4]) { - unsigned int funct; - struct device *pdev; - u8 line, irq; + u8 slot, line, irq; - /* Each slot may contain up to eight functions. */ - for (funct = 0; funct < 8; funct++) { - pdev = dev_find_slot(bus, (slot << 3) + funct); + /* Each device may contain up to eight functions. */ + slot = dev->path.pci.devfn >> 3; - if (!pdev) - continue; + for (; dev ; dev = dev->sibling) { - line = pci_read_config8(pdev, PCI_INTERRUPT_PIN); + if (dev->path.pci.devfn >> 3 != slot) + break; + + line = pci_read_config8(dev, PCI_INTERRUPT_PIN); /* PCI spec says all values except 1..4 are reserved. */ if ((line < 1) || (line > 4)) @@ -1527,11 +1524,9 @@ void pci_assign_irqs(unsigned bus, unsigned slot, irq = pIntAtoD[line - 1]; - printk(BIOS_DEBUG, "Assigning IRQ %d to %d:%x.%d\n", - irq, bus, slot, funct); + printk(BIOS_DEBUG, "Assigning IRQ %d to %s\n", irq, dev_path(dev)); - pci_write_config8(pdev, PCI_INTERRUPT_LINE, - pIntAtoD[line - 1]); + pci_write_config8(dev, PCI_INTERRUPT_LINE, pIntAtoD[line - 1]); #ifdef PARANOID_IRQ_ASSIGNMENTS irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE); diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 5f72b55cff..c08b30af6f 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -98,8 +98,7 @@ unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev); const char *pin_to_str(int pin); int get_pci_irq_pins(struct device *dev, struct device **parent_bdg); -void pci_assign_irqs(unsigned int bus, unsigned int slot, - const unsigned char pIntAtoD[4]); +void pci_assign_irqs(struct device *dev, const unsigned char pIntAtoD[4]); const char *get_pci_class_name(struct device *dev); const char *get_pci_subclass_name(struct device *dev); diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index 4886fe1830..0b3689731e 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -41,7 +41,7 @@ static void qemu_nb_init(struct device *dev) /* setup IRQ routing */ for (i = 0; i < 32; i++) - pci_assign_irqs(0, i, qemu_i440fx_irqs + (i % 4)); + pci_assign_irqs(pcidev_on_root(i, 0), qemu_i440fx_irqs + (i % 4)); } static struct device_operations nb_operations = { diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index 90a32f4000..ae3f96a158 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -61,10 +61,10 @@ static void qemu_nb_init(struct device *dev) /* setup IRQ routing for pci slots */ for (i = 0; i < 25; i++) - pci_assign_irqs(0, i, qemu_q35_irqs + (i % 4)); + pci_assign_irqs(pcidev_on_root(i, 0), qemu_q35_irqs + (i % 4)); /* setup IRQ routing southbridge devices */ for (i = 25; i < 32; i++) - pci_assign_irqs(0, i, qemu_q35_irqs); + pci_assign_irqs(pcidev_on_root(i, 0), qemu_q35_irqs); } static void qemu_nb_read_resources(struct device *dev) From ab275f0915f2ba8abffed8f1384aa5353287c5ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 4 Jul 2019 07:16:59 +0300 Subject: [PATCH 186/231] device/pci: Declare pcidev_path_on_bus() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is recommended to never reference PCI busses using a static number. There is exception with OPROM execution, where we want to translate the bus number captured from the actual IO operation into a matching device node in the devicetree. Change-Id: I733c645ac5581c000b4cd6cdc05829cd039324d5 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34077 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/device/device_const.c | 18 ++++++++++++++++++ src/include/device/device.h | 1 + 2 files changed, 19 insertions(+) diff --git a/src/device/device_const.c b/src/device/device_const.c index 1853b4c4d2..c1b0b063ff 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -183,6 +183,24 @@ DEVTREE_CONST struct device *pcidev_path_behind( return find_dev_path(parent, &path); } +DEVTREE_CONST struct device *pcidev_path_on_bus(unsigned int bus, pci_devfn_t devfn) +{ + DEVTREE_CONST struct bus *parent = pci_root_bus(); + DEVTREE_CONST struct device *dev = parent->children; + + /* FIXME: Write the loop with topology links. */ + while (dev) { + if (dev->path.type != DEVICE_PATH_PCI) { + dev = dev->next; + continue; + } + if (dev->bus->secondary == bus) + return pcidev_path_behind(dev->bus, devfn); + dev = dev->next; + } + return NULL; +} + DEVTREE_CONST struct bus *pci_root_bus(void) { DEVTREE_CONST struct device *pci_domain; diff --git a/src/include/device/device.h b/src/include/device/device.h index a200de0876..007c51f629 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -288,6 +288,7 @@ DEVTREE_CONST struct device *dev_bus_each_child(const struct bus *parent, DEVTREE_CONST struct device *pcidev_path_behind(const struct bus *parent, pci_devfn_t devfn); DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn); +DEVTREE_CONST struct device *pcidev_path_on_bus(unsigned int bus, pci_devfn_t devfn); DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn); DEVTREE_CONST struct bus *pci_root_bus(void); From 129bc4c0e08102ed9bdb000b8cb04fc2c07cb375 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 14 May 2019 13:17:28 +0200 Subject: [PATCH 187/231] soc/intel/common: Add CM246 LPC device id Change-Id: Ic57ccf48988afbbba256172a7540bb02b88d1bbd Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/34163 Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 1 + src/soc/intel/cannonlake/bootblock/report_platform.c | 1 + src/soc/intel/common/block/lpc/lpc.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 35c457a636..92283ac958 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2730,6 +2730,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370 0xa306 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370 0xa30c +#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246 0xa30e #define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI 0x3480 #define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0 0x3481 #define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI 0x3482 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index e0c91945fe..20ad26bdcc 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -76,6 +76,7 @@ static struct { { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, "Cannonlake-H Q370" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, "Cannonlake-H QM370" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246, "Cannonlake-H CM246" }, { PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC, "Cometlake-U Super" }, { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC, "Cometlake-Y Premium" }, { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, "Cometlake-U Premium" }, diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 54c7706f6e..43ac8444a9 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -156,6 +156,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, + PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246, PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, From ff3c9647c32cd5bd9ac8614670bee660522d37fb Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 14 May 2019 13:18:05 +0200 Subject: [PATCH 188/231] soc/intel/common: Add Coffee Lake H 6+2 Xeon graphics id Change-Id: Ibf72a8db2e4292e5d5bb67b8778e1d1ebfa19632 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/34164 Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 1 + src/soc/intel/cannonlake/bootblock/report_platform.c | 1 + src/soc/intel/common/block/graphics/graphics.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 92283ac958..ac18aacf03 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3043,6 +3043,7 @@ #define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5 #define PCI_DEVICE_ID_INTEL_CFL_H_GT2 0x3e9b #define PCI_DEVICE_ID_INTEL_CFL_S_GT2 0x3e92 +#define PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2 0x3e94 #define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT 0x8A70 #define PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT 0x8A71 #define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT 0x8A40 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 20ad26bdcc..1cbbd6384d 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -100,6 +100,7 @@ static struct { { PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1, "Whiskeylake ULT GT1" }, { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, "Coffeelake-H Xeon GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index ed9ae00bf8..e4ccccb013 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -151,6 +151,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM, PCI_DEVICE_ID_INTEL_CFL_H_GT2, PCI_DEVICE_ID_INTEL_CFL_S_GT2, + PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, PCI_DEVICE_ID_INTEL_ICL_GT0_ULT, PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT, PCI_DEVICE_ID_INTEL_ICL_GT1_ULT, From e2f39e23e8982a239f4ec063d823ad3414e1ba66 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 10 Jul 2019 18:36:09 +0200 Subject: [PATCH 189/231] pci_ids: Drop a block of unused, redundant definitions These didn't align with the usual naming conventions and contained some errors beside. Change-Id: I45033d4cb998a85fc0bec00c54e207226f42de4e Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/34209 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/include/device/pci_ids.h | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ac18aacf03..0c846c64d9 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3196,17 +3196,6 @@ /* Intel EMMC device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b -/* Intel PCH Ids */ -#define PCH_CNL_LP_M_SUPER 0x9d80 -#define PCH_CNL_LP_M_SUPER_UNLOCK 0x9d81 -#define PCH_CNL_LP_M_SUPER_LOCK 0x9d82 -#define PCH_CNL_LP_Y_PREMIUM 0x9d83 -#define PCH_CNL_LP_U_PREMIUM 0x9d84 -#define PCH_CNL_LP_U_BASE 0x9d85 -#define PCH_CNL_H_DT_SUPER 0xa280 -#define PCH_CNP_H_MOBILE_Q370 0xa306 -#define PCH_CNP_H_MOBILE_QM370 0xa30c - /* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 #define PCI_DEVICE_ID_6005_SERIES_WIFI 0x0085 From 98d19572b175ad44a83614cdf2c57ed0ba94a733 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 4 Jul 2019 13:15:01 +0300 Subject: [PATCH 190/231] device/oprom: Replace uses of dev_find_slot() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The call to dev_find_slot() may return PCI devices that are disabled or unaccessible, as PCI enumeration does not remove nodes from all_devices linked list. Use PCI topology search instead. Change-Id: I00233177e5572ca79002a7d141cda1b94b966330 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34083 Reviewed-by: Mike Banon Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/device/oprom/realmode/x86_interrupts.c | 2 +- src/device/oprom/yabel/interrupt.c | 4 ++-- src/device/oprom/yabel/io.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/device/oprom/realmode/x86_interrupts.c b/src/device/oprom/realmode/x86_interrupts.c index 2629ab9166..8e3a51e450 100644 --- a/src/device/oprom/realmode/x86_interrupts.c +++ b/src/device/oprom/realmode/x86_interrupts.c @@ -174,7 +174,7 @@ int int1a_handler(void) devfn = X86_EBX & 0xff; bus = X86_EBX >> 8; reg = X86_EDI; - dev = dev_find_slot(bus, devfn); + dev = pcidev_path_on_bus(bus, devfn); if (!dev) { printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn); // Or are we supposed to return PCIBIOS_NODEV? diff --git a/src/device/oprom/yabel/interrupt.c b/src/device/oprom/yabel/interrupt.c index 2bc238e75a..338156f8ed 100644 --- a/src/device/oprom/yabel/interrupt.c +++ b/src/device/oprom/yabel/interrupt.c @@ -409,8 +409,8 @@ handleInt1a(void) if ((bus == bios_device.bus) && (devfn == bios_device.devfn)) { dev = bios_device.dev; } else if (CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES)) { - dev = dev_find_slot(bus, devfn); - DEBUG_PRINTF_INTR("%s(): function: %x: dev_find_slot() returned: %s\n", + dev = pcidev_path_on_bus(bus, devfn); + DEBUG_PRINTF_INTR("%s(): function: %x: pcidev_path_on_bus() returned: %s\n", __func__, M.x86.R_AX, dev_path(dev)); } diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index 8ae91d46e0..e8c41ce24a 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -435,8 +435,8 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size) if ((bus == bios_device.bus) && (devfn == bios_device.devfn)) { dev = bios_device.dev; } else if (CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES)) { - dev = dev_find_slot(bus, devfn); - DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", + dev = pcidev_path_on_bus(bus, devfn); + DEBUG_PRINTF_INTR("%s(): pcidev_path_on_bus() returned: %s\n", __func__, dev_path(dev)); } From ac14a40d0e17571ad3495d45216842044def289e Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Thu, 11 Jul 2019 12:47:19 +0200 Subject: [PATCH 191/231] util/sconfig: Fix compile error with older glibc-headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In patch e29a6ac16a9f478fc00ce7cb83f3779954e3168d (util/sconfig: Add commonlib/helpers.h) helpers.h has been added to the include-list. In headers.h we have a definition for __unused: On a host system environment where glibc-headers-2.12-1.212 is installed, a file included by called bits/stat.h have the following content on line 105 and onwards: long int __unused[3]; where the mentioned part is part of the structure called struct stat. If we include commonlib/helpers.h _before_ , the symbol for __unused will be defined by the preprocessor to be '__attribute__((unused))', therefore the above mentioned structure member will be expanded by the preprocessor to be 'long int __attribute__((unused))[3];', which is not a valid C syntax and therefore produces a compile error for sconfig tool. To handle this case we need to make sure commonlib/helpers.h is included _after_ . As the needed part of stat.h (which is struct stat) is only used in main.c it is safe to move the include from sconfig.h directly into main.c while taking care of the order. Change-Id: I9e6960a318d3dd999e1e9c1df326d67094f3b5ce Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/34236 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Patrick Georgi --- util/sconfig/main.c | 2 ++ util/sconfig/sconfig.h | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 385ced16ab..85e0d8ea7f 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -15,6 +15,8 @@ */ #include +/* stat.h needs to be included before commonlib/helpers.h to avoid errors.*/ +#include #include #include "sconfig.h" #include "sconfig.tab.h" diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index e6363dea83..eea2a14e40 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -18,7 +18,6 @@ #include #include #include -#include #include #include From aae7552b2415154f818c1c66de6f2f2a01cdad69 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Thu, 11 Jul 2019 14:26:46 +0300 Subject: [PATCH 192/231] util/superiotool/aspeed: fix SUART number Change-Id: I20c4436d414bc6b9a3ff5138d6fd59ead8fd4a47 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/34237 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Paul Menzel --- util/superiotool/aspeed.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/superiotool/aspeed.c b/util/superiotool/aspeed.c index 6d49c16e9a..454e5c5baa 100644 --- a/util/superiotool/aspeed.c +++ b/util/superiotool/aspeed.c @@ -28,7 +28,7 @@ static const struct superio_registers reg_table[] = { {0x02, "SUART1", {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, {0x00,0x03,0xf8,0x04,0x02,RSVD,EOT}}, - {0x03, "SUART1", + {0x03, "SUART2", {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, {0x00,0x02,0xf8,0x03,0x02,0x00,EOT}}, {0x04, "SWC", From b14f3b8b0b005a5de8f5bcbb84d44fce9d0bc6b8 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 10 Jul 2019 23:18:46 +0200 Subject: [PATCH 193/231] vendorcode/amd/agesa/f15tn: Fix condition that has identical branches MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixed function is never used. Change-Id: Ia004756a0b301278f813067ab0ea580c5ea837d3 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/34225 Reviewed-by: Martin Roth Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- .../amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c index b1aa92b6ba..b60eb51e16 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c @@ -1035,7 +1035,7 @@ F15HtPhyOverrideDllCompensation ( for (Sublink = 0; Sublink < 2; Sublink++) { CapabilitySet = StartingCapabilitySet; Link = 0; - DesiredLinkFeats.HtPhyLinkValue = ((Sublink == 0) ? HTPHY_LINKTYPE_SL0_HT3 : HTPHY_LINKTYPE_SL0_HT3); + DesiredLinkFeats.HtPhyLinkValue = ((Sublink == 0) ? HTPHY_LINKTYPE_SL0_HT3 : HTPHY_LINKTYPE_SL1_HT3); while (FamilySpecificServices->NextLinkHasHtPhyFeats ( FamilySpecificServices, &CapabilitySet, From 56352e1f8055c3495c71e1856f0d26923be44ed0 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Thu, 11 Jul 2019 14:31:34 +0200 Subject: [PATCH 194/231] mb/siemens/mc_apl3: Enable LPSS UART 1 By setting the GPIOs 42 and 43 to native function 1 the LPSS UART 1 is activated. Change-Id: I74abd1b6fb5459cf11a5bdee182c99462f613b7a Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/34238 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c index 9159ba1b50..e0fec7c786 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c @@ -325,8 +325,9 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ PAD_CFG_GPI(GPIO_41, UP_20K, DEEP), /* LPSS_UART0_CTS - unused */ - PAD_CFG_GPI(GPIO_42, UP_20K, DEEP), /* LPSS_UART1_RXD - unused */ - PAD_CFG_GPI(GPIO_43, DN_20K, DEEP), /* LPSS_UART1_TXD - unused */ + PAD_CFG_NF(GPIO_42, UP_20K, DEEP, NF1), /* LPSS_UART1_RXD */ + /* LPSS_UART1_TXD */ + PAD_CFG_NF_IOSSTATE(GPIO_43, NATIVE, DEEP, NF1, Tx1RxDCRx0), PAD_CFG_GPI(GPIO_44, UP_20K, DEEP), /* LPSS_UART1_RTS - unused */ PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - unused */ PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), /* LPSS_UART2_RXD */ From 276d46ac05b59c1c4536cbce20808d0a96f7fea5 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 16 Jun 2019 11:08:25 +0200 Subject: [PATCH 195/231] src: Add missing include Change-Id: Iae73fc1557fb310dacbbf8bc486dc3cc5249d9e7 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33526 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/amd/family_10h-family_15h/fidvid.c | 1 + src/northbridge/via/vx900/early_host_bus_ctl.c | 2 ++ src/northbridge/via/vx900/pci_util.c | 1 + src/soc/intel/quark/acpi.c | 1 + src/southbridge/amd/sb800/early_setup.c | 1 + src/southbridge/broadcom/bcm5785/early_setup.c | 1 + src/southbridge/nvidia/ck804/early_setup_car.c | 1 + src/southbridge/nvidia/mcp55/early_setup_car.c | 1 + 8 files changed, 9 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 2c6e08cf0a..c5d523a74c 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -91,6 +91,7 @@ b.- prep_fid_change(...) #include #include +#include #include #include diff --git a/src/northbridge/via/vx900/early_host_bus_ctl.c b/src/northbridge/via/vx900/early_host_bus_ctl.c index 92bb44dda0..1ef29449fd 100644 --- a/src/northbridge/via/vx900/early_host_bus_ctl.c +++ b/src/northbridge/via/vx900/early_host_bus_ctl.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include + #include "early_vx900.h" static void vx900_cpu_bus_preram_setup(void) diff --git a/src/northbridge/via/vx900/pci_util.c b/src/northbridge/via/vx900/pci_util.c index 07a9a71f73..e6eb91ac95 100644 --- a/src/northbridge/via/vx900/pci_util.c +++ b/src/northbridge/via/vx900/pci_util.c @@ -15,6 +15,7 @@ */ #include +#include #include "vx900.h" diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index 2cb5adf4f2..ffcd91f13d 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -16,6 +16,7 @@ */ #include +#include #include #include diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index eaa47e3c2c..b549c5e17c 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -18,6 +18,7 @@ #include #include +#include #include #include #include diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index a8a38f2bc9..8ea776f76e 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include "bcm5785.h" diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index e7a06f9dc7..e2cc40a986 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -18,6 +18,7 @@ #include #include +#include #include #include diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 908cdd595f..69d12bfad7 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -18,6 +18,7 @@ #include #include #include +#include #ifdef UNUSED_CODE int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val); From 0c4ed4bd7edf3c0a131af717eb6dc8aeec44b47e Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Thu, 4 Jul 2019 12:55:35 -0600 Subject: [PATCH 196/231] arch, include, soc: Use common stdint.h There are only minimal differences between the architecture specific stdint.h implementations, so let's tidy them up and merge them together into a single file. In particular, - Use 'unsigned long' for uintptr_t. This was already the case for x86 and riscv, while arm and mips used 'unsigned int', and arm64 and ppc64 used 'unsigned long long'. This change allows using a single integer type for uintptr_t across all architectures, and brings it into consistency with the rest of the code base, which generally uses 'unsigned long' for memory addresses anyway. This change required fixing several assumptions about integer types in the arm code. - Use _Bool as the boolean type. This is a specialized boolean type that was introduced in C99, and is preferrable over hacking booleans using integers. romcc sadly does not support _Bool, so for that we stick with the old uint8_t. - Drop the least and fast integer types. They aren't used anywhere in the code base and are an unnecessary maintenance burden. Using the standard fixed width types is essentially always better anyway. - Drop the UINT64_C() macro. It also isn't used anywhere and doesn't provide anything that a (uint64_t) cast doesn't. - Implement the rest of the MIN and MAX numerical limits. - Use static assertions to check that the integer widths are correct. Change-Id: I6b52f37793151041b7bdee9ec3708bfad69617b2 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/34075 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Julius Werner Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/arch/arm/armv7/mmu.c | 2 +- src/arch/arm/include/stdint.h | 110 --------------------- src/arch/arm64/include/stdint.h | 86 ---------------- src/arch/mips/include/stdint.h | 100 ------------------- src/arch/ppc64/include/stdint.h | 76 --------------- src/arch/riscv/include/stdint.h | 79 --------------- src/arch/x86/include/stdint.h | 113 --------------------- src/include/stdint.h | 119 +++++++++++++++++++++++ src/soc/nvidia/tegra124/lp0/Makefile | 2 +- src/soc/nvidia/tegra210/lp0/Makefile | 2 +- src/soc/nvidia/tegra210/mmu_operations.c | 2 +- 11 files changed, 123 insertions(+), 568 deletions(-) delete mode 100644 src/arch/arm/include/stdint.h delete mode 100644 src/arch/arm64/include/stdint.h delete mode 100644 src/arch/mips/include/stdint.h delete mode 100644 src/arch/ppc64/include/stdint.h delete mode 100644 src/arch/riscv/include/stdint.h delete mode 100644 src/arch/x86/include/stdint.h create mode 100644 src/include/stdint.h diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index b3133a08b7..e9d10e2a3d 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -165,7 +165,7 @@ static pte_t *mmu_create_subtable(pte_t *pgd_entry) /* We assume that *pgd_entry must already be a valid block mapping. */ uintptr_t start_addr = (uintptr_t)(*pgd_entry & BLOCK_MASK); - printk(BIOS_DEBUG, "Creating new subtable @%p for [%#.8x:%#.8lx)\n", + printk(BIOS_DEBUG, "Creating new subtable @%p for [%#.8lx:%#.8lx)\n", table, start_addr, start_addr + BLOCK_SIZE); /* Initialize the new subtable with entries of the same attributes diff --git a/src/arch/arm/include/stdint.h b/src/arch/arm/include/stdint.h deleted file mode 100644 index ede0ec9aef..0000000000 --- a/src/arch/arm/include/stdint.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ARM_STDINT_H -#define ARM_STDINT_H - -#if defined(__GNUC__) -#define __HAVE_LONG_LONG__ 1 -#else -#define __HAVE_LONG_LONG__ 0 -#endif - -/* Exact integral types */ -typedef unsigned char uint8_t; -typedef signed char int8_t; - -typedef unsigned short uint16_t; -typedef signed short int16_t; - -typedef unsigned int uint32_t; -typedef signed int int32_t; - -#if __HAVE_LONG_LONG__ -typedef unsigned long long uint64_t; -typedef signed long long int64_t; -#endif - -/* Small types */ -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; - -typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; - -typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; - -#if __HAVE_LONG_LONG__ -typedef unsigned long long uint_least64_t; -typedef signed long long int_least64_t; -#endif - -/* Fast Types */ -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; - -typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; - -typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; - -#if __HAVE_LONG_LONG__ -typedef unsigned long long uint_fast64_t; -typedef signed long long int_fast64_t; -#endif - -/* Types for `void *' pointers. */ -typedef int intptr_t; -typedef unsigned int uintptr_t; - -/* Largest integral types */ -#if __HAVE_LONG_LONG__ -typedef long long int intmax_t; -typedef unsigned long long uintmax_t; -#else -typedef long int intmax_t; -typedef unsigned long int uintmax_t; -#endif - -typedef uint8_t u8; -typedef uint16_t u16; -typedef uint32_t u32; -#if __HAVE_LONG_LONG__ -typedef uint64_t u64; -#endif -typedef int8_t s8; -typedef int16_t s16; -typedef int32_t s32; - -typedef uint8_t bool; -#define true 1 -#define false 0 - -#ifndef UINT32_MAX -#define UINT32_MAX (4294967295U) -#endif -#ifndef UINT64_MAX -# define UINT64_MAX (18446744073709551615ULL) -#endif -#ifndef UINT64_C -#define UINT64_C(c) c ## ULL -#endif -#ifndef PRIu64 -#define PRIu64 "llu" -#endif - -#undef __HAVE_LONG_LONG__ - -#endif /* ARM_STDINT_H */ diff --git a/src/arch/arm64/include/stdint.h b/src/arch/arm64/include/stdint.h deleted file mode 100644 index cb07a07c86..0000000000 --- a/src/arch/arm64/include/stdint.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ARM64_STDINT_H -#define ARM64_STDINT_H - -/* Exact integral types */ -typedef unsigned char uint8_t; -typedef signed char int8_t; - -typedef unsigned short uint16_t; -typedef signed short int16_t; - -typedef unsigned int uint32_t; -typedef signed int int32_t; - -typedef unsigned long long uint64_t; -typedef signed long long int64_t; - -/* Small types */ -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; - -typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; - -typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; - -typedef unsigned long long uint_least64_t; -typedef signed long long int_least64_t; - -/* Fast Types */ -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; - -typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; - -typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; - -typedef unsigned long long uint_fast64_t; -typedef signed long long int_fast64_t; - -typedef long long int intmax_t; -typedef unsigned long long uintmax_t; - -typedef uint8_t u8; -typedef uint16_t u16; -typedef uint32_t u32; -typedef uint64_t u64; -typedef int8_t s8; -typedef int16_t s16; -typedef int32_t s32; -typedef int64_t s64; - -typedef uint8_t bool; -#define true 1 -#define false 0 - -/* Types for `void *' pointers. */ -typedef s64 intptr_t; -typedef u64 uintptr_t; - -#ifndef UINT32_MAX -#define UINT32_MAX (4294967295U) -#endif -#ifndef UINT64_MAX -# define UINT64_MAX (18446744073709551615ULL) -#endif -#ifndef PRIu64 -#define PRIu64 "llu" -#endif - -#endif /* ARM64_STDINT_H */ diff --git a/src/arch/mips/include/stdint.h b/src/arch/mips/include/stdint.h deleted file mode 100644 index cdfea2e8fc..0000000000 --- a/src/arch/mips/include/stdint.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Based on src/arch/armv7/include/stdint.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_STDINT_H -#define __MIPS_STDINT_H - -#if defined(__GNUC__) -#define __HAVE_LONG_LONG__ 1 -#else -#define __HAVE_LONG_LONG__ 0 -#endif - -/* Exact integral types */ -typedef unsigned char uint8_t; -typedef signed char int8_t; - -typedef unsigned short uint16_t; -typedef signed short int16_t; - -typedef unsigned int uint32_t; -typedef signed int int32_t; - -#if __HAVE_LONG_LONG__ -typedef unsigned long long uint64_t; -typedef signed long long int64_t; -#endif - -/* Small types */ -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; - -typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; - -typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; - -#if __HAVE_LONG_LONG__ -typedef unsigned long long uint_least64_t; -typedef signed long long int_least64_t; -#endif - -/* Fast Types */ -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; - -typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; - -typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; - -#if __HAVE_LONG_LONG__ -typedef unsigned long long uint_fast64_t; -typedef signed long long int_fast64_t; -#endif - -/* Types for `void *' pointers. */ -typedef int intptr_t; -typedef unsigned int uintptr_t; - -/* Largest integral types */ -#if __HAVE_LONG_LONG__ -typedef long long int intmax_t; -typedef unsigned long long uintmax_t; -#else -typedef long int intmax_t; -typedef unsigned long int uintmax_t; -#endif - -typedef uint8_t u8; -typedef uint16_t u16; -typedef uint32_t u32; -#if __HAVE_LONG_LONG__ -typedef uint64_t u64; -#endif -typedef int8_t s8; -typedef int16_t s16; -typedef int32_t s32; - -typedef uint8_t bool; -#define true 1 -#define false 0 - - -#undef __HAVE_LONG_LONG__ - -#endif /* __MIPS_STDINT_H */ diff --git a/src/arch/ppc64/include/stdint.h b/src/arch/ppc64/include/stdint.h deleted file mode 100644 index 6425824439..0000000000 --- a/src/arch/ppc64/include/stdint.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef PPC64_STDINT_H -#define PPC64_STDINT_H - -/* Exact integral types */ -typedef unsigned char uint8_t; -typedef signed char int8_t; - -typedef unsigned short uint16_t; -typedef signed short int16_t; - -typedef unsigned int uint32_t; -typedef signed int int32_t; - -typedef unsigned long long uint64_t; -typedef signed long long int64_t; - -/* Small types */ -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; - -typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; - -typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; - -typedef unsigned long long uint_least64_t; -typedef signed long long int_least64_t; - -/* Fast Types */ -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; - -typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; - -typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; - -typedef unsigned long long uint_fast64_t; -typedef signed long long int_fast64_t; - -typedef long long int intmax_t; -typedef unsigned long long uintmax_t; - -typedef uint8_t u8; -typedef uint16_t u16; -typedef uint32_t u32; -typedef uint64_t u64; -typedef int8_t s8; -typedef int16_t s16; -typedef int32_t s32; -typedef int64_t s64; - -typedef uint8_t bool; -#define true 1 -#define false 0 - -/* Types for `void *' pointers. */ -typedef s64 intptr_t; -typedef u64 uintptr_t; - -#endif /* PPC64_STDINT_H */ diff --git a/src/arch/riscv/include/stdint.h b/src/arch/riscv/include/stdint.h deleted file mode 100644 index 76f0d1b778..0000000000 --- a/src/arch/riscv/include/stdint.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef RISCV_STDINT_H -#define RISCV_STDINT_H - -/* Exact integral types */ -typedef unsigned char uint8_t; -typedef signed char int8_t; - -typedef unsigned short uint16_t; -typedef signed short int16_t; - -typedef unsigned int uint32_t; -typedef signed int int32_t; - -typedef unsigned long long uint64_t; -typedef signed long long int64_t; - -/* Small types */ -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; - -typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; - -typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; - -typedef unsigned long long uint_least64_t; -typedef signed long long int_least64_t; - -/* Fast Types */ -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; - -typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; - -typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; - -typedef unsigned long long uint_fast64_t; -typedef signed long long int_fast64_t; - -typedef long long int intmax_t; -typedef unsigned long long uintmax_t; - -typedef uint8_t u8; -typedef uint16_t u16; -typedef uint32_t u32; -typedef uint64_t u64; -typedef int8_t s8; -typedef int16_t s16; -typedef int32_t s32; -typedef int64_t s64; - -typedef uint8_t bool; -#define true 1 -#define false 0 - -/* Types for `void *' pointers. */ -typedef long intptr_t; -typedef unsigned long uintptr_t; - -/* FIXME: This is used in some print code and may be removed in the future. */ -#define PRIu64 "llu" - -#endif /* RISCV_STDINT_H */ diff --git a/src/arch/x86/include/stdint.h b/src/arch/x86/include/stdint.h deleted file mode 100644 index 6c400021b0..0000000000 --- a/src/arch/x86/include/stdint.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef X86_STDINT_H -#define X86_STDINT_H - -#if defined(__GNUC__) -#define __HAVE_LONG_LONG__ 1 -#else -#define __HAVE_LONG_LONG__ 0 -#endif - -/* Exact integral types */ -typedef unsigned char uint8_t; -typedef signed char int8_t; - -typedef unsigned short uint16_t; -typedef signed short int16_t; - -typedef unsigned int uint32_t; -typedef signed int int32_t; - -#if __HAVE_LONG_LONG__ -typedef unsigned long long uint64_t; -typedef signed long long int64_t; -#endif - -/* Small types */ -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; - -typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; - -typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; - -#if __HAVE_LONG_LONG__ -typedef unsigned long long uint_least64_t; -typedef signed long long int_least64_t; -#endif - -/* Fast Types */ -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; - -typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; - -typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; - -#if __HAVE_LONG_LONG__ -typedef unsigned long long uint_fast64_t; -typedef signed long long int_fast64_t; -#endif - -/* Types for `void *' pointers. */ -typedef long intptr_t; -typedef unsigned long uintptr_t; - -/* Largest integral types */ -#if __HAVE_LONG_LONG__ -typedef long long int intmax_t; -typedef unsigned long long uintmax_t; -#else -typedef long int intmax_t; -typedef unsigned long int uintmax_t; -#endif - -typedef uint8_t u8; -typedef uint16_t u16; -typedef uint32_t u32; -#if __HAVE_LONG_LONG__ -typedef uint64_t u64; -#endif -typedef int8_t s8; -typedef int16_t s16; -typedef int32_t s32; - -typedef uint8_t bool; -#define true 1 -#define false 0 - -#ifndef UINT32_MAX -#define UINT32_MAX (4294967295U) -#endif -#ifndef UINT64_MAX -# define UINT64_MAX (18446744073709551615ULL) -#endif - -#ifndef UINT64_C -#define UINT64_C(c) c ## ULL -#endif -#ifndef PRIu64 -#define PRIu64 "llu" - -#endif - - -#undef __HAVE_LONG_LONG__ - -#endif /* X86_STDINT_H */ diff --git a/src/include/stdint.h b/src/include/stdint.h new file mode 100644 index 0000000000..f363aab08a --- /dev/null +++ b/src/include/stdint.h @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef STDINT_H +#define STDINT_H + +/* romcc does not support long long, _Static_assert, or _Bool, so we must ifdef that code out. + Also, GCC can provide its own implementation of stdint.h, so in theory we could use that + instead of this custom file once romcc is no more. */ + +/* Fixed width integer types */ +typedef signed char int8_t; +typedef unsigned char uint8_t; + +typedef signed short int16_t; +typedef unsigned short uint16_t; + +typedef signed int int32_t; +typedef unsigned int uint32_t; + +#ifndef __ROMCC__ +typedef signed long long int64_t; +typedef unsigned long long uint64_t; +#endif + +/* Types for 'void *' pointers */ +typedef signed long intptr_t; +typedef unsigned long uintptr_t; + +/* Ensure that the widths are all correct */ +#ifndef __ROMCC__ +_Static_assert(sizeof(int8_t) == 1, "Size of int8_t is incorrect"); +_Static_assert(sizeof(uint8_t) == 1, "Size of uint8_t is incorrect"); + +_Static_assert(sizeof(int16_t) == 2, "Size of int16_t is incorrect"); +_Static_assert(sizeof(uint16_t) == 2, "Size of uint16_t is incorrect"); + +_Static_assert(sizeof(int32_t) == 4, "Size of int32_t is incorrect"); +_Static_assert(sizeof(uint32_t) == 4, "Size of uint32_t is incorrect"); + +_Static_assert(sizeof(int64_t) == 8, "Size of int64_t is incorrect"); +_Static_assert(sizeof(uint64_t) == 8, "Size of uint64_t is incorrect"); + +_Static_assert(sizeof(intptr_t) == sizeof(void *), "Size of intptr_t is incorrect"); +_Static_assert(sizeof(uintptr_t) == sizeof(void *), "Size of uintptr_t is incorrect"); +#endif + +/* Maximum width integer types */ +#ifndef __ROMCC__ +typedef int64_t intmax_t; +typedef uint64_t uintmax_t; +#endif + +/* Convenient typedefs */ +typedef int8_t s8; +typedef uint8_t u8; + +typedef int16_t s16; +typedef uint16_t u16; + +typedef int32_t s32; +typedef uint32_t u32; + +#ifndef __ROMCC__ +typedef int64_t s64; +typedef uint64_t u64; +#endif + +/* Limits of integer types */ +#define INT8_MIN ((int8_t)0x80) +#define INT8_MAX ((int8_t)0x7F) +#define UINT8_MAX ((uint8_t)0xFF) + +#define INT16_MIN ((int16_t)0x8000) +#define INT16_MAX ((int16_t)0x7FFF) +#define UINT16_MAX ((uint16_t)0xFFFF) + +#define INT32_MIN ((int32_t)0x80000000) +#define INT32_MAX ((int32_t)0x7FFFFFFF) +#define UINT32_MAX ((uint32_t)0xFFFFFFFF) + +#ifndef __ROMCC__ +#define INT64_MIN ((int64_t)0x8000000000000000) +#define INT64_MAX ((int64_t)0x7FFFFFFFFFFFFFFF) +#define UINT64_MAX ((uint64_t)0xFFFFFFFFFFFFFFFF) +#endif + +#ifndef __ROMCC__ +#define INTMAX_MIN INT64_MIN +#define INTMAX_MAX INT64_MAX +#define UINTMAX_MAX UINT64_MAX +#endif + +/* TODO: move into stdbool.h */ +#ifdef __ROMCC__ +typedef uint8_t bool; +#else +typedef _Bool bool; +#endif +#define true 1 +#define false 0 + +/* TODO: move into inttypes.h */ +#ifndef __ROMCC__ +#define PRIu64 "llu" +#define PRIxPTR "lx" +#endif + +#endif /* STDINT_H */ diff --git a/src/soc/nvidia/tegra124/lp0/Makefile b/src/soc/nvidia/tegra124/lp0/Makefile index 884f8b2768..e82edaa8c8 100644 --- a/src/soc/nvidia/tegra124/lp0/Makefile +++ b/src/soc/nvidia/tegra124/lp0/Makefile @@ -34,7 +34,7 @@ all: tegra_lp0_resume.fw tegra_lp0_resume.elf: tegra_lp0_resume.ld tegra_lp0_resume.c $(CC) -marm -march=armv4t -mno-unaligned-access -nostdlib -static \ -Os -fpie -Wl,--build-id=none -ggdb3 -T tegra_lp0_resume.ld \ - -include ../../../../arch/arm/include/stdint.h \ + -include ../../../../include/stdint.h \ -include ../../../../commonlib/include/commonlib/compiler.h \ -o $@ $(filter %.c,$+) diff --git a/src/soc/nvidia/tegra210/lp0/Makefile b/src/soc/nvidia/tegra210/lp0/Makefile index 884f8b2768..e82edaa8c8 100644 --- a/src/soc/nvidia/tegra210/lp0/Makefile +++ b/src/soc/nvidia/tegra210/lp0/Makefile @@ -34,7 +34,7 @@ all: tegra_lp0_resume.fw tegra_lp0_resume.elf: tegra_lp0_resume.ld tegra_lp0_resume.c $(CC) -marm -march=armv4t -mno-unaligned-access -nostdlib -static \ -Os -fpie -Wl,--build-id=none -ggdb3 -T tegra_lp0_resume.ld \ - -include ../../../../arch/arm/include/stdint.h \ + -include ../../../../include/stdint.h \ -include ../../../../commonlib/include/commonlib/compiler.h \ -o $@ $(filter %.c,$+) diff --git a/src/soc/nvidia/tegra210/mmu_operations.c b/src/soc/nvidia/tegra210/mmu_operations.c index 9cee6b2f29..86328a32b2 100644 --- a/src/soc/nvidia/tegra210/mmu_operations.c +++ b/src/soc/nvidia/tegra210/mmu_operations.c @@ -23,7 +23,7 @@ static void tegra210_mmu_config(void) { - uint64_t start,end; + uintptr_t start, end; const unsigned long devmem = MA_DEV | MA_S | MA_RW; const unsigned long cachedmem = MA_MEM | MA_NS | MA_RW; const unsigned long secure_mem = MA_MEM | MA_S | MA_RW; From 8417485f95b07aa76d81d7006fa5097d018d6df2 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 28 Jun 2019 16:12:47 +0200 Subject: [PATCH 197/231] soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSP We got rid of the dangerous reconfiguration of arbitrary pads in coreboot, but FSP still overrode that. Make sure that it doesn't enable a UART for debug output when it isn't configured in core- boot. This, again, shows how dangerous it is to leave any FSP UPD at its binary default. Change-Id: I7280a80f71ddddbe78352eb696e6f5844d2df0b2 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/34167 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/soc/intel/cannonlake/fsp_params.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index a58a97c060..2367045bdb 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -285,6 +285,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Set Debug serial port */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; +#if !CONFIG(SOC_INTEL_COMETLAKE) + params->SerialIoEnableDebugUartAfterPost = CONFIG_INTEL_LPSS_UART_FOR_CONSOLE; +#endif /* Enable CNVi Wifi if enabled in device tree */ dev = pcidev_path_on_root(PCH_DEVFN_CNViWIFI); From 3555389a8cdb4cb10deeafd2e116a387aa6ec5d4 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 6 Jul 2019 09:53:01 +0200 Subject: [PATCH 198/231] payloads: Update GRUB stable from 2.02 to 2.04 GRUB 2.04 was released on July 5th, 2019, so update. The only change-log is the git history. Some coreboot related changes are listed below. 1. coreboot: Changed cbmemc to support updated console format from coreboot. 2. ahci: Increase time-out from 10 s to 32 s 3. normal/menu: Do not treat error values as key presses When building from the git repository, `./bootstrap.sh` needs to be run to set up Gnulib. Ignore the exit code, as older versions might not have this script. Change-Id: Iab0b87164ed86f15d3415af935998b59e0d76c45 Signed-off-by: Pablo <42.pablo.ms@gmail.com> Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/34104 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- payloads/external/GRUB2/Kconfig | 2 +- payloads/external/GRUB2/Makefile | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/payloads/external/GRUB2/Kconfig b/payloads/external/GRUB2/Kconfig index c4edab9d11..552f06a523 100644 --- a/payloads/external/GRUB2/Kconfig +++ b/payloads/external/GRUB2/Kconfig @@ -5,7 +5,7 @@ choice default GRUB2_STABLE config GRUB2_STABLE - bool "2.02" + bool "2.04" help Stable GRUB2 version diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile index 31c40665fe..43da597eb7 100644 --- a/payloads/external/GRUB2/Makefile +++ b/payloads/external/GRUB2/Makefile @@ -1,9 +1,9 @@ TAG-$(CONFIG_GRUB2_MASTER)= TAG-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID) -TAG-$(CONFIG_GRUB2_STABLE)=e54c99aaff5e5f6f5d3b06028506c57e66d8ef77 +TAG-$(CONFIG_GRUB2_STABLE)=grub-2.04 NAME-$(CONFIG_GRUB2_MASTER)=HEAD NAME-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID) -NAME-$(CONFIG_GRUB2_STABLE)=2.02 +NAME-$(CONFIG_GRUB2_STABLE)=2.04 project_git_repo=https://git.savannah.gnu.org/git/grub.git/ project_dir=grub2 @@ -28,7 +28,7 @@ grub2/build/config.h: $(CONFIG_DEP) | checkout echo " CONFIG GRUB2 $(NAME-y)" rm -rf grub2/build mkdir grub2/build - cd grub2 && ./autogen.sh + cd grub2 && ./bootstrap.sh ; ./autogen.sh cd grub2/build && ../configure CC="$(HOSTCC)" LD="$(LD)" \ FREETYPE="pkg-config freetype2" BUILD_FREETYPE="pkg-config freetype2" \ TARGET_CC="$(CC)" TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" \ From 55b7263ed825fa668f2a21d66cec57f01eccebe5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 8 Jul 2019 22:36:38 +0300 Subject: [PATCH 199/231] intel/e7505,i82801dx: Fix SMM_ASEG lock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In our codebase, this is only coupled with intel/e7505. The PCI registers reference here were for intel/i945. Also aseg_smm_lock() was previously not called. Change-Id: I21d991c8c2f5c2dde1f148fd80963e39d9836d3c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34149 Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/intel/e7505/e7505.h | 2 ++ src/northbridge/intel/e7505/memmap.c | 8 ++++++++ src/southbridge/intel/i82801dx/i82801dx.h | 3 +++ src/southbridge/intel/i82801dx/lpc.c | 6 ++++++ src/southbridge/intel/i82801dx/smi.c | 19 ++++++------------- 5 files changed, 25 insertions(+), 13 deletions(-) diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index b80d8a8a52..faf91440e8 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -42,6 +42,8 @@ #define DRC 0x7C /* DRAM Controller Mode register, 32 bit */ #define DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */ #define CKDIS 0x8C /* Clock disable register, 8 bit */ +#define SMRAMC 0x9D +#define ESMRAMC 0x9E #define APSIZE 0xB4 #define TOLM 0xC4 /* Top of Low Memory register, 16 bit */ #define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */ diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index d45006566e..b954c6af74 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -35,6 +35,14 @@ void *cbmem_top(void) return (void *)tolm; } +void northbridge_write_smram(u8 smram); + +void northbridge_write_smram(u8 smram) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, SMRAMC, smram); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 678d5d78b9..ac53ae13a3 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -37,6 +37,9 @@ extern void i82801dx_enable(struct device *dev); void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); #endif + +void aseg_smm_lock(void); + #endif #define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 3c74e98f59..94d8e14eb3 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -299,6 +299,12 @@ static void lpc_init(struct device *dev) /* Initialize the High Precision Event Timers */ enable_hpet(dev); + + /* Don't allow evil boot loaders, kernels, or + * userspace applications to deceive us: + */ + if (CONFIG(HAVE_SMI_HANDLER)) + aseg_smm_lock(); } static void i82801dx_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index b977e32cd2..7dfed9d946 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -26,8 +26,10 @@ #include #include "i82801dx.h" -/* I945 */ -#define SMRAM 0x90 + +void northbridge_write_smram(u8 smram); + +/* For intel/e7505. */ #define D_OPEN (1 << 6) #define D_CLS (1 << 5) #define D_LCK (1 << 4) @@ -317,18 +319,10 @@ static void smm_relocate(void) static void smm_install(void) { - /* enable the SMM memory window */ - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_OPEN | G_SMRAME | C_BASE_SEG); - /* copy the real SMM handler */ memcpy((void *)0xa0000, _binary_smm_start, _binary_smm_end - _binary_smm_start); wbinvd(); - - /* close the SMM memory window and enable normal SMM */ - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - G_SMRAME | C_BASE_SEG); } void smm_init(void) @@ -348,15 +342,14 @@ void smm_init_completion(void) restore_default_smm_area(default_smm_area); } -void smm_lock(void) +void aseg_smm_lock(void) { /* LOCK the SMM memory window and enable normal SMM. * After running this function, only a full reset can * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); + northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) From d4e140dae7fb102c24ecd3165ce540c0b9b93dd0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 8 Jul 2019 23:25:05 +0300 Subject: [PATCH 200/231] cpu/x86: Move smm_lock() prototype MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The function implementations are in local platform scopes. Change-Id: I7a3025398b15fe6d2c5a13cdb65f3e62a49c0bc6 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34151 Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/arch/x86/include/arch/cpu.h | 3 ++- src/cpu/intel/haswell/haswell.h | 1 + src/cpu/intel/smm/gen1/smi.h | 1 + src/soc/intel/broadwell/include/soc/smm.h | 1 + src/soc/intel/cannonlake/include/soc/smm.h | 1 + src/soc/intel/fsp_broadwell_de/include/soc/smm.h | 1 + src/soc/intel/icelake/include/soc/smm.h | 1 + src/soc/intel/skylake/include/soc/smm.h | 1 + 8 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 32717ba5b3..293ca02158 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -203,9 +203,10 @@ static inline unsigned int cpuid_edx(unsigned int op) unsigned int cpu_cpuid_extended_level(void); int cpu_have_cpuid(void); +/* Only with !PARALLEL_MP. */ void smm_init(void); void smm_init_completion(void); -void smm_lock(void); + void smm_setup_structures(void *gnvs, void *tcg, void *smi1); static inline bool cpu_is_amd(void) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 4ebbe183b7..cd8d5cb52b 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -166,6 +166,7 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); void smm_initialize(void); void smm_relocate(void); +void smm_lock(void); struct bus; void bsp_init_and_start_aps(struct bus *cpu_bus); /* Determine if HyperThreading is disabled. The variable is not valid until diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h index 05c507c09c..3d5149a430 100644 --- a/src/cpu/intel/smm/gen1/smi.h +++ b/src/cpu/intel/smm/gen1/smi.h @@ -31,3 +31,4 @@ void southbridge_smm_clear_state(void); void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_relocate(void); +void smm_lock(void); diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h index 75e78337c2..d3e1cddb81 100644 --- a/src/soc/intel/broadwell/include/soc/smm.h +++ b/src/soc/intel/broadwell/include/soc/smm.h @@ -59,6 +59,7 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); void smm_initialize(void); void smm_relocate(void); +void smm_lock(void); /* These helpers are for performing SMM relocation. */ void southbridge_trigger_smi(void); diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index e1c819ba14..c0ab82f0b7 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -56,5 +56,6 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); void smm_initialize(void); void smm_relocate(void); +void smm_lock(void); #endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h index 505feaf66d..72aa7fa4f2 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h @@ -60,6 +60,7 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); void smm_initialize(void); void smm_relocate(void); +void smm_lock(void); /* These helpers are for performing SMM relocation. */ void southbridge_trigger_smi(void); diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index 3c66f57d43..991c593f72 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -55,5 +55,6 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); void smm_initialize(void); void smm_relocate(void); +void smm_lock(void); #endif diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 7114a80b08..0c5e9766c0 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -54,5 +54,6 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); void smm_initialize(void); void smm_relocate(void); +void smm_lock(void); #endif From d1c1c9a76e929ea61c023adbcbb550d077d08e01 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 12 Jul 2019 01:29:46 +0300 Subject: [PATCH 201/231] drivers/elog: Fix ELOG_GSMI dependency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SMM_TSEG is a qualifier between TSEG and ASEG only, while HAVE_SMI_HANDLER currently tells if SMM will be installed. Move rest of the file under same 'if ELOG' block. Change-Id: I620d3ce5aa9632d862d6480922144f002cf6423b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34195 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/drivers/elog/Kconfig | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/drivers/elog/Kconfig b/src/drivers/elog/Kconfig index da8a5fa220..4a66e788bb 100644 --- a/src/drivers/elog/Kconfig +++ b/src/drivers/elog/Kconfig @@ -42,10 +42,8 @@ config ELOG_PRERAM help This option will enable event logging from the preram stage. -endif - config ELOG_GSMI - depends on ELOG && SMM_TSEG + depends on HAVE_SMI_HANDLER bool "SMI interface to write and clear event log" select SPI_FLASH_SMM if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP default n @@ -55,7 +53,6 @@ config ELOG_GSMI kernel reset/shutdown messages to the event log. config ELOG_BOOT_COUNT - depends on ELOG bool "Maintain a monotonic boot number in CMOS" default n help @@ -64,9 +61,11 @@ config ELOG_BOOT_COUNT counter will be logged as part of the System Boot event. config ELOG_BOOT_COUNT_CMOS_OFFSET - depends on ELOG && ELOG_BOOT_COUNT && !USE_OPTION_TABLE + depends on ELOG_BOOT_COUNT && !USE_OPTION_TABLE int "Offset in CMOS to store the boot count" default 0 help This value must be greater than 16 bytes so as not to interfere with the standard RTC region. Requires 8 bytes. + +endif From 09e2f6e1ba10b5d75385541266117f2e6b6b975b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 12 Jul 2019 08:02:35 +0300 Subject: [PATCH 202/231] intel/fsp_rangeley: Avoid preprocessor with HAVE_SMI_HANDLER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Id9abc239a92fa7d3e29738f08f2ccdaf3232dfb6 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34253 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/fsp_rangeley/acpi.c | 3 --- src/southbridge/intel/fsp_rangeley/lpc.c | 6 +++--- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index e0b3cb985c..aeb2d9b3bb 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -23,9 +23,6 @@ #include #include -#if CONFIG(HAVE_SMI_HANDLER) -#include -#endif /** * Fill in the FADT with generic values that can be overridden later. diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index ba5e04bd3c..af2e411584 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -421,10 +421,10 @@ static void southbridge_inject_dsdt(struct device *dev) if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); -#if CONFIG(HAVE_SMI_HANDLER) + /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); -#endif + if (CONFIG(HAVE_SMI_HANDLER)) + smm_setup_structures(gnvs, NULL, NULL); /* Add it to DSDT. */ acpigen_write_scope("\\"); From b4905625eb863b0d3263ec3e2ea3dfe61d11d49d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 12 Jul 2019 08:02:35 +0300 Subject: [PATCH 203/231] soc,southbridge/intel: Avoid preprocessor with HAVE_SMI_HANDLER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Id375999adad71d95d4968398e90bc3c07f65ea83 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34254 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp1_1/raminit.c | 20 +++++++++----------- src/soc/intel/broadwell/lpc.c | 4 +--- src/soc/intel/denverton_ns/romstage.c | 13 +++++-------- src/soc/intel/skylake/cpu.c | 5 ++--- src/southbridge/intel/lynxpoint/lpc.c | 4 +--- 5 files changed, 18 insertions(+), 28 deletions(-) diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index bcc8eca962..e71c9a2ddf 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -53,6 +53,8 @@ void raminit(struct romstage_params *params) UPD_DATA_REGION *upd_ptr; int fsp_verification_failure = 0; EFI_PEI_HOB_POINTERS hob_ptr; + char *smm_base; + size_t smm_size; /* * Find and copy the UPD region to the stack so the platform can modify @@ -145,14 +147,11 @@ void raminit(struct romstage_params *params) } /* Display SMM area */ -#if CONFIG(HAVE_SMI_HANDLER) - char *smm_base; - size_t smm_size; - - smm_region((void **)&smm_base, &smm_size); - printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); - printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); -#endif + if (CONFIG(HAVE_SMI_HANDLER)) { + smm_region((void **)&smm_base, &smm_size); + printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); + printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); + } /* Migrate CAR data */ printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); @@ -237,8 +236,8 @@ void raminit(struct romstage_params *params) (unsigned int)fsp_reserved_memory_area))) { fsp_verification_failure = 1; printk(BIOS_ERR, "ERROR - Reserving FSP memory area!\n"); -#if CONFIG(HAVE_SMI_HANDLER) - if (cbmem_root != NULL) { + + if (CONFIG(HAVE_SMI_HANDLER) && cbmem_root != NULL) { size_t delta_bytes = (unsigned int)smm_base - cbmem_root->PhysicalStart - cbmem_root->ResourceLength; @@ -248,7 +247,6 @@ void raminit(struct romstage_params *params) die_with_post_code(POST_INVALID_VENDOR_BINARY, "Please verify the chipset reserved size\n"); } -#endif } /* Verify the FSP 1.1 HOB interface */ diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 7679724ece..df1d857a2d 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -428,13 +428,11 @@ static void pch_cg_init(struct device *dev) static void pch_set_acpi_mode(void) { -#if CONFIG(HAVE_SMI_HANDLER) - if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); } -#endif /* CONFIG_HAVE_SMI_HANDLER */ } static void lpc_init(struct device *dev) diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 6d8eaab9b1..2ad78a02df 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -141,12 +141,9 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; uintptr_t top_of_ram; - -#if CONFIG(HAVE_SMI_HANDLER) void *smm_base; size_t smm_size; uintptr_t tseg_base; -#endif console_init(); @@ -177,7 +174,6 @@ asmlinkage void car_stage_entry(void) /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); -#if CONFIG(HAVE_SMI_HANDLER) /* * Cache the TSEG region at the top of ram. This region is * not restricted to SMM mode until SMM has been relocated. @@ -185,10 +181,11 @@ asmlinkage void car_stage_entry(void) * when relocating the SMM handler as well as using the TSEG * region for other purposes. */ - smm_region(&smm_base, &smm_size); - tseg_base = (uintptr_t)smm_base; - postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); -#endif + if (CONFIG(HAVE_SMI_HANDLER)) { + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); + } run_postcar_phase(&pcf); } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index a63809bd7e..df08959cc8 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -487,9 +487,8 @@ static void post_mp_init(void) smm_southbridge_enable(GBL_EN); /* Lock down the SMRAM space. */ -#if CONFIG(HAVE_SMI_HANDLER) - smm_lock(); -#endif + if (CONFIG(HAVE_SMI_HANDLER)) + smm_lock(); mp_run_on_all_cpus(vmx_configure, NULL, 2 * USECS_PER_MSEC); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4efb83e05e..84032cadd2 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -491,8 +491,7 @@ static void enable_lp_clock_gating(struct device *dev) static void pch_set_acpi_mode(void) { -#if CONFIG(HAVE_SMI_HANDLER) - if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); @@ -503,7 +502,6 @@ static void pch_set_acpi_mode(void) printk(BIOS_DEBUG, "done.\n"); #endif } -#endif /* CONFIG_HAVE_SMI_HANDLER */ } static void pch_disable_smm_only_flashing(struct device *dev) From 8a77454e3318e937875512b28f85de3b1808fc7e Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 12 Jul 2019 16:34:53 +0530 Subject: [PATCH 204/231] soc/intel/cannonlake: Remove unused header files from southbridge.asl Change-Id: I1f970db22f87e8eba0129ca049f75d16539644a5 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/34270 Tested-by: build bot (Jenkins) Reviewed-by: Bora Guvendik Reviewed-by: Furquan Shaikh Reviewed-by: HAOUAS Elyes Reviewed-by: Subrata Banik --- src/soc/intel/cannonlake/acpi/southbridge.asl | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index d9ff70b6bc..8ba3d89b0f 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -15,11 +15,6 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include - /* PCI IRQ assignment */ #include "pci_irqs.asl" From f6410baaabd4a68a11112c021cecb48b83b131c1 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 10 Jul 2019 13:16:40 -0700 Subject: [PATCH 205/231] fit_payload: Always set DT size CB:32870 changed FIT loading code to make an FDT mandatory (because the platforms that can use FIT images always need an FDT). Remove one left-over conditional that is now dead code. Found by Coverity. Change-Id: Ia7765d45f068ab4bdc720ea7ae87dcc62a4b7d3d Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/34224 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/lib/fit_payload.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index 8e75915806..a4d370540e 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -228,7 +228,7 @@ void fit_payload(struct prog *payload) /* Collect infos for fit_payload_arch */ kernel.size = config->kernel->size; - fdt.size = dt ? dt_flat_size(dt) : 0; + fdt.size = dt_flat_size(dt); initrd.size = config->ramdisk ? config->ramdisk->size : 0; /* Invoke arch specific payload placement and fixups */ From 3c2e287b7ca9706cb29bd2c34b42af7e4c0a2981 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 11 Jul 2019 12:54:12 -0600 Subject: [PATCH 206/231] console/Kconfig - only print UART addresses for I/O based UARTs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It doesn't make sense to print these values for memory-mapped UARTs. Change-Id: Ie2d9cf95f0b0fdcf601e74de799b1390c08f2335 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/c/coreboot/+/34247 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Kyösti Mälkki --- src/console/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 61ba667d59..4cb407e785 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -79,13 +79,13 @@ config TTYS0_BASE Map the COM port number to the respective I/O port. comment "Serial port base address = 0x3f8" -depends on UART_FOR_CONSOLE = 0 +depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 0 comment "Serial port base address = 0x2f8" -depends on UART_FOR_CONSOLE = 1 +depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 1 comment "Serial port base address = 0x3e8" -depends on UART_FOR_CONSOLE = 2 +depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 2 comment "Serial port base address = 0x2e8" -depends on UART_FOR_CONSOLE = 3 +depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 3 config UART_OVERRIDE_BAUDRATE boolean From 237f1789e3156f7e72776d3cf79801cfd6517ff5 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 11 Jul 2019 09:46:37 +0200 Subject: [PATCH 207/231] soc/qualcomm: Remove unneeded '#include ' Change-Id: I39db73014c0a4456750210c002787abf9bc79fce Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/34232 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/qualcomm/qcs405/usb.c | 1 - src/soc/qualcomm/sdm845/usb.c | 1 - 2 files changed, 2 deletions(-) diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c index 49eac72da5..a94973ff2b 100644 --- a/src/soc/qualcomm/qcs405/usb.c +++ b/src/soc/qualcomm/qcs405/usb.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c index c7d65e6b42..8e2b9119ae 100644 --- a/src/soc/qualcomm/sdm845/usb.c +++ b/src/soc/qualcomm/sdm845/usb.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include From 8b9a3ec93a5b941b62bac3f4176d05dc3f45bd55 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 11 Jul 2019 12:24:09 +0200 Subject: [PATCH 208/231] soc/rockchip/rk3288/include/soc: Add missing include Change-Id: Ibde48d7cff582c91f55ad5f1328aac64d018b3c5 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/34235 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/soc/rockchip/rk3288/include/soc/sdram.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/rockchip/rk3288/include/soc/sdram.h b/src/soc/rockchip/rk3288/include/soc/sdram.h index 5a26a0ae06..3ad51b6fa5 100644 --- a/src/soc/rockchip/rk3288/include/soc/sdram.h +++ b/src/soc/rockchip/rk3288/include/soc/sdram.h @@ -16,6 +16,8 @@ #ifndef __SOC_ROCKCHIP_RK3288_SDRAM_H__ #define __SOC_ROCKCHIP_RK3288_SDRAM_H__ +#include + enum { DDR3 = 3, LPDDR3 = 6, From 3b50c05bb203dc8f302881be38c7566917b34e0e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 6 Jul 2019 09:51:58 +0300 Subject: [PATCH 209/231] intel/haswell: Replace monotonic timer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove implementation of 24 MHz clock, available only on Haswell ULT SKUs. Use TSC_MONOTONIC_TIMER instead for all boards. Change-Id: Ic4aeb084d1b0913368f5eaa46e1bd68411435517 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34114 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/cpu/intel/haswell/Kconfig | 1 + src/cpu/intel/haswell/Makefile.inc | 8 ---- src/cpu/intel/haswell/monotonic_timer.c | 58 ----------------------- src/mainboard/asrock/h81m-hds/Kconfig | 1 - src/mainboard/supermicro/x10slm-f/Kconfig | 1 - 5 files changed, 1 insertion(+), 68 deletions(-) delete mode 100644 src/cpu/intel/haswell/monotonic_timer.c diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index cb8bc77335..8f91b60953 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_TSC select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index a472da2d5e..f9606486c2 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -16,14 +16,6 @@ postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c smm-y += finalize.c smm-y += tsc_freq.c -ifneq ($(CONFIG_TSC_MONOTONIC_TIMER),y) -bootblock-y += monotonic_timer.c -romstage-y += monotonic_timer.c -postcar-y += monotonic_timer.c -ramstage-y += monotonic_timer.c -smm-y += monotonic_timer.c -endif - bootblock-y += ../car/non-evict/cache_as_ram.S bootblock-y += ../car/bootblock.c bootblock-y += ../../x86/early_reset.S diff --git a/src/cpu/intel/haswell/monotonic_timer.c b/src/cpu/intel/haswell/monotonic_timer.c deleted file mode 100644 index 63500a4d26..0000000000 --- a/src/cpu/intel/haswell/monotonic_timer.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include -#include - -#define MSR_COUNTER_24_MHz 0x637 -static struct monotonic_counter { - int initialized; - struct mono_time time; - uint32_t last_value; -} mono_counter; - -static inline uint32_t read_counter_msr(void) -{ - /* Even though the MSR is 64-bit it is assumed that the hardware - * is polled frequently enough to only use the lower 32-bits. */ - msr_t counter_msr; - - counter_msr = rdmsr(MSR_COUNTER_24_MHz); - - return counter_msr.lo; -} - -void timer_monotonic_get(struct mono_time *mt) -{ - uint32_t current_tick; - uint32_t usecs_elapsed; - - if (!mono_counter.initialized) { - mono_counter.last_value = read_counter_msr(); - mono_counter.initialized = 1; - } - - current_tick = read_counter_msr(); - usecs_elapsed = (current_tick - mono_counter.last_value) / 24; - - /* Update current time and tick values only if a full tick occurred. */ - if (usecs_elapsed) { - mono_time_add_usecs(&mono_counter.time, usecs_elapsed); - mono_counter.last_value = current_tick; - } - - /* Save result. */ - *mt = mono_counter.time; -} diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 928a01042e..6974cda95f 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_NUVOTON_NCT6776 select SUPERIO_NUVOTON_NCT6776_COM_A - select TSC_MONOTONIC_TIMER config CBFS_SIZE hex diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig index 430bed379a..3945c090cc 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm-f/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_NUVOTON_NCT6776 select SUPERIO_NUVOTON_NCT6776_COM_A - select TSC_MONOTONIC_TIMER config CBFS_SIZE hex From 7fbed223c73aa65d57e881c8450a38855291f5e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 11 Jul 2019 08:14:07 +0300 Subject: [PATCH 210/231] intel/i945: Fix udelay() prototypes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia157c6417bdd9c4ffbdf07683c51d0680e9356c9 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34228 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/getac/p470/romstage.c | 1 + src/mainboard/kontron/986lcd-m/romstage.c | 1 + src/mainboard/lenovo/t60/romstage.c | 1 + src/mainboard/lenovo/x60/romstage.c | 1 + src/mainboard/lenovo/z61t/romstage.c | 1 + src/mainboard/roda/rk886ex/romstage.c | 1 + src/northbridge/intel/i945/raminit.c | 1 + src/northbridge/intel/i945/raminit.h | 1 - 8 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index aaa3422c02..d14b1c8719 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 85a82c5acb..b51e4b44d0 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 820cd5265e..cfe2d237db 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -19,6 +19,7 @@ #include #include +#include #include #include #include diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index b66ef66871..fc0c678b77 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -19,6 +19,7 @@ #include #include +#include #include #include #include diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 716be16dad..c31301e4d1 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -19,6 +19,7 @@ #include #include +#include #include #include #include diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 2bdad276c1..efd739c52e 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 281e7b2679..c42c34cf39 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index e9e66d13e1..d417169c62 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -68,5 +68,4 @@ struct sys_info { void receive_enable_adjust(struct sys_info *sysinfo); void sdram_initialize(int boot_path, const u8 *sdram_addresses); int fixup_i945_errata(void); -void udelay(u32 us); #endif /* RAMINIT_H */ From 0921962e4410577ffb1b15109ec6dc2deb015d37 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Fri, 5 Jul 2019 14:56:41 +0900 Subject: [PATCH 211/231] mb/google/octopus: Add custom SAR values for Bluebird Bluebird needs to use different SAR values than Casta. Bluebird sku id is 2. CQ-DEPEND=CL:*1435310 BUG=b:129725065 BRANCH=octopus TEST=build Change-Id: I107a8519832fcf906b94f958a3dc508d19bb4727 Signed-off-by: Seunghwan Kim Reviewed-on: https://review.coreboot.org/c/coreboot/+/34080 Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- .../octopus/variants/casta/Makefile.inc | 1 + .../google/octopus/variants/casta/variant.c | 28 +++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 src/mainboard/google/octopus/variants/casta/variant.c diff --git a/src/mainboard/google/octopus/variants/casta/Makefile.inc b/src/mainboard/google/octopus/variants/casta/Makefile.inc index 9fb63f5f43..ba865e9f82 100644 --- a/src/mainboard/google/octopus/variants/casta/Makefile.inc +++ b/src/mainboard/google/octopus/variants/casta/Makefile.inc @@ -1,3 +1,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/octopus/variants/casta/variant.c b/src/mainboard/google/octopus/variants/casta/variant.c new file mode 100644 index 0000000000..89b1033886 --- /dev/null +++ b/src/mainboard/google/octopus/variants/casta/variant.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + uint32_t sku_id = get_board_sku(); + + if (sku_id == 2) + filename = "wifi_sar-bluebird.hex"; + + return filename; +} From 328c8bbd23284527a9d54697a4631c8bda95fd89 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 11 Jul 2019 17:46:40 -0700 Subject: [PATCH 212/231] mb/google/hatch: Fix trackpad configuration in overridetree Hatch and variants use GPP_A21 for trackpad IRQ and wake. Fix overridetree.cb to advertise the right IRQ. Change-Id: Ib87c858b89e8726c3bc80f83be0729ef4625268e Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/34248 Reviewed-by: Philip Chen Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Fagerburg Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/hatch/overridetree.cb | 2 +- src/mainboard/google/hatch/variants/helios/overridetree.cb | 2 +- src/mainboard/google/hatch/variants/kindred/overridetree.cb | 4 ++-- src/mainboard/google/hatch/variants/kohaku/overridetree.cb | 6 ++---- 4 files changed, 6 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 18878cee4a..e40a566482 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -63,7 +63,7 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" device i2c 15 on end end diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 3f71c99db1..1907289621 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -72,7 +72,7 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" device i2c 15 on end end diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index 89937068d5..becfc49cae 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -55,7 +55,7 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" register "probed" = "1" device i2c 15 on end @@ -63,7 +63,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" register "generic.wake" = "GPE0_DW0_21" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index cf422ed01d..18cc1d4b36 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -64,11 +64,9 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - # TODO: enable this when b/123967687 is fixed. - # register "generic.wake" = "GPE0_DW2_27" - # also set next line to ACPI_IRQ_WAKE_EDGE_LOW - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" register "generic.probed" = "1" + register "generic.wake" = "GPE0_DW0_21" register "hid_desc_reg_offset" = "0x20" device i2c 0x20 on end end From fd5d788f5e8139b387314d453644d9e58b1a654f Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 29 May 2019 15:09:42 -0600 Subject: [PATCH 213/231] drivers/wifi: Add generic WiFi driver Add generic WiFi driver to support common device operations across multiple types of WiFi controller. BUG=None BRANCH=None TEST=Boot to ChromeOS. Ensure that the SSDT table contains SAR tables and wakeup GPE information. Ensure that the SSDT table is same after the change. Change-Id: Ica5edf95a37c8ed60f7e159d94fd58af5d41c0ef Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/33155 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/intel/wifi/Kconfig | 47 +----- src/drivers/intel/wifi/chip.h | 23 +-- src/drivers/intel/wifi/wifi.c | 195 ++----------------------- src/drivers/wifi/Kconfig | 57 ++++++++ src/drivers/wifi/Makefile.inc | 1 + src/drivers/wifi/generic.c | 245 ++++++++++++++++++++++++++++++++ src/drivers/wifi/generic_wifi.h | 51 +++++++ 7 files changed, 367 insertions(+), 252 deletions(-) create mode 100644 src/drivers/wifi/Kconfig create mode 100644 src/drivers/wifi/Makefile.inc create mode 100644 src/drivers/wifi/generic.c create mode 100644 src/drivers/wifi/generic_wifi.h diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig index 4dc4d7faeb..fc8700fa82 100644 --- a/src/drivers/intel/wifi/Kconfig +++ b/src/drivers/intel/wifi/Kconfig @@ -2,52 +2,7 @@ config DRIVERS_INTEL_WIFI bool "Support Intel PCI-e WiFi adapters" depends on ARCH_X86 default y if PCIEXP_PLUGIN_SUPPORT + select DRIVERS_GENERIC_WIFI if HAVE_ACPI_TABLES help When enabled, add identifiers in ACPI and SMBIOS tables to make OS drivers work with certain Intel PCI-e WiFi chipsets. - -config USE_SAR - bool - default n - help - Enable it when wifi driver uses SAR configuration feature. - VPD entry "wifi_sar" is read to get SAR settings, if its - not found driver may look into CBFS for default settigs. - WIFI_SAR_CBFS is option to enable CBFS lookup. - -config SAR_ENABLE - bool - default n - depends on USE_SAR - -config DSAR_ENABLE - bool - default n - depends on USE_SAR - -config GEO_SAR_ENABLE - bool - default n - depends on USE_SAR - -config WIFI_SAR_CBFS - bool "Enable SAR table addition to CBFS" - default n - depends on USE_SAR - help - wifi driver would look for "wifi_sar" vpd key and load SAR settings from - it, if the vpd key is not found then the driver tries to look for sar - settings from CBFS with file name wifi_sar_defaults.hex. - So OEM/ODM can override wifi sar with VPD. - -config WIFI_SAR_CBFS_FILEPATH - string "The cbfs file which has WIFI SAR defaults" - depends on WIFI_SAR_CBFS - default "src/mainboard/$(MAINBOARDDIR)/wifi_sar_defaults.hex" - -config DSAR_SET_NUM - hex "Number of SAR sets when D-SAR is enabled" - default 0x3 - depends on USE_SAR - help - There can be up to 3 optional SAR table sets. diff --git a/src/drivers/intel/wifi/chip.h b/src/drivers/intel/wifi/chip.h index 1b3c2a5834..21803108ca 100644 --- a/src/drivers/intel/wifi/chip.h +++ b/src/drivers/intel/wifi/chip.h @@ -13,26 +13,11 @@ * GNU General Public License for more details. */ -#ifndef _WIFI_CHIP_H_ -#define _WIFI_CHIP_H_ - -/* WRDS Spec Revision */ -#define WRDS_REVISION 0x0 - -/* EWRD Spec Revision */ -#define EWRD_REVISION 0x0 - -/* WRDS Domain type */ -#define WRDS_DOMAIN_TYPE_WIFI 0x7 - -/* EWRD Domain type */ -#define EWRD_DOMAIN_TYPE_WIFI 0x7 - -/* WGDS Domain type */ -#define WGDS_DOMAIN_TYPE_WIFI 0x7 +#ifndef _INTEL_WIFI_CHIP_H_ +#define _INTEL_WIFI_CHIP_H_ struct drivers_intel_wifi_config { - unsigned wake; /* Wake pin for ACPI _PRW */ + unsigned int wake; /* Wake pin for ACPI _PRW */ }; -#endif /* _WIFI_CHIP_H_ */ +#endif /* _INTEL_WIFI_CHIP_H_ */ diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index 83cfaa925c..926905c26b 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -15,19 +15,16 @@ * GNU General Public License for more details. */ -#include -#include #include #include #include #include #include #include -#include #include #include -#include #include "chip.h" +#include "drivers/wifi/generic_wifi.h" #define PMCS_DR 0xcc #define PME_STS (1 << 15) @@ -65,194 +62,18 @@ static int smbios_write_wifi(struct device *dev, int *handle, } #endif -__weak -int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) -{ - return -1; -} - #if CONFIG(HAVE_ACPI_TABLES) -static void emit_sar_acpi_structures(void) -{ - int i, j, package_size; - struct wifi_sar_limits sar_limits; - struct wifi_sar_delta_table *wgds; - - /* Retrieve the sar limits data */ - if (get_wifi_sar_limits(&sar_limits) < 0) { - printk(BIOS_ERR, "Error: failed from getting SAR limits!\n"); - return; - } - - /* - * Name ("WRDS", Package () { - * Revision, - * Package () { - * Domain Type, // 0x7:WiFi - * WiFi SAR BIOS, // BIOS SAR Enable/disable - * SAR Table Set // Set#1 of SAR Table (10 bytes) - * } - * }) - */ - acpigen_write_name("WRDS"); - acpigen_write_package(2); - acpigen_write_dword(WRDS_REVISION); - /* Emit 'Domain Type' + 'WiFi SAR BIOS' + 10 bytes for Set#1 */ - package_size = 1 + 1 + BYTES_PER_SAR_LIMIT; - acpigen_write_package(package_size); - acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI); - acpigen_write_dword(CONFIG(SAR_ENABLE)); - for (i = 0; i < BYTES_PER_SAR_LIMIT; i++) - acpigen_write_byte(sar_limits.sar_limit[0][i]); - acpigen_pop_len(); - acpigen_pop_len(); - - /* - * Name ("EWRD", Package () { - * Revision, - * Package () { - * Domain Type, // 0x7:WiFi - * Dynamic SAR Enable, // Dynamic SAR Enable/disable - * Extended SAR sets, // Number of optional SAR table sets - * SAR Table Set, // Set#2 of SAR Table (10 bytes) - * SAR Table Set, // Set#3 of SAR Table (10 bytes) - * SAR Table Set // Set#4 of SAR Table (10 bytes) - * } - * }) - */ - acpigen_write_name("EWRD"); - acpigen_write_package(2); - acpigen_write_dword(EWRD_REVISION); - /* - * Emit 'Domain Type' + "Dynamic SAR Enable' + 'Extended SAR sets' - * + number of bytes for Set#2 & 3 & 4 - */ - package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT; - acpigen_write_package(package_size); - acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI); - acpigen_write_dword(CONFIG(DSAR_ENABLE)); - acpigen_write_dword(CONFIG_DSAR_SET_NUM); - for (i = 1; i < NUM_SAR_LIMITS; i++) - for (j = 0; j < BYTES_PER_SAR_LIMIT; j++) - acpigen_write_byte(sar_limits.sar_limit[i][j]); - acpigen_pop_len(); - acpigen_pop_len(); - - - if (!CONFIG(GEO_SAR_ENABLE)) - return; - - /* - * Name ("WGDS", Package() { - * Revision, - * Package() { - * DomainType, // 0x7:WiFi - * WgdsWiFiSarDeltaGroup1PowerMax1, // Group 1 FCC 2400 Max - * WgdsWiFiSarDeltaGroup1PowerChainA1, // Group 1 FCC 2400 A Offset - * WgdsWiFiSarDeltaGroup1PowerChainB1, // Group 1 FCC 2400 B Offset - * WgdsWiFiSarDeltaGroup1PowerMax2, // Group 1 FCC 5200 Max - * WgdsWiFiSarDeltaGroup1PowerChainA2, // Group 1 FCC 5200 A Offset - * WgdsWiFiSarDeltaGroup1PowerChainB2, // Group 1 FCC 5200 B Offset - * WgdsWiFiSarDeltaGroup2PowerMax1, // Group 2 EC Jap 2400 Max - * WgdsWiFiSarDeltaGroup2PowerChainA1, // Group 2 EC Jap 2400 A Offset - * WgdsWiFiSarDeltaGroup2PowerChainB1, // Group 2 EC Jap 2400 B Offset - * WgdsWiFiSarDeltaGroup2PowerMax2, // Group 2 EC Jap 5200 Max - * WgdsWiFiSarDeltaGroup2PowerChainA2, // Group 2 EC Jap 5200 A Offset - * WgdsWiFiSarDeltaGroup2PowerChainB2, // Group 2 EC Jap 5200 B Offset - * WgdsWiFiSarDeltaGroup3PowerMax1, // Group 3 ROW 2400 Max - * WgdsWiFiSarDeltaGroup3PowerChainA1, // Group 3 ROW 2400 A Offset - * WgdsWiFiSarDeltaGroup3PowerChainB1, // Group 3 ROW 2400 B Offset - * WgdsWiFiSarDeltaGroup3PowerMax2, // Group 3 ROW 5200 Max - * WgdsWiFiSarDeltaGroup3PowerChainA2, // Group 3 ROW 5200 A Offset - * WgdsWiFiSarDeltaGroup3PowerChainB2, // Group 3 ROW 5200 B Offset - * } - * }) - */ - - wgds = &sar_limits.wgds; - acpigen_write_name("WGDS"); - acpigen_write_package(2); - acpigen_write_dword(wgds->version); - /* Emit 'Domain Type' + - * Group specific delta of power (6 bytes * NUM_WGDS_SAR_GROUPS) - */ - package_size = sizeof(sar_limits.wgds.group) + 1; - acpigen_write_package(package_size); - acpigen_write_dword(WGDS_DOMAIN_TYPE_WIFI); - for (i = 0; i < SAR_NUM_WGDS_GROUPS; i++) { - acpigen_write_byte(wgds->group[i].power_max_2400mhz); - acpigen_write_byte(wgds->group[i].power_chain_a_2400mhz); - acpigen_write_byte(wgds->group[i].power_chain_b_2400mhz); - acpigen_write_byte(wgds->group[i].power_max_5200mhz); - acpigen_write_byte(wgds->group[i].power_chain_a_5200mhz); - acpigen_write_byte(wgds->group[i].power_chain_b_5200mhz); - } - - acpigen_pop_len(); - acpigen_pop_len(); -} - static void intel_wifi_fill_ssdt(struct device *dev) { struct drivers_intel_wifi_config *config = dev->chip_info; - const char *path = acpi_device_path(dev->bus->dev); - u32 address; + struct generic_wifi_config generic_config; - if (!path || !dev->enabled) - return; - - /* Device */ - acpigen_write_scope(path); - acpigen_write_device(acpi_device_name(dev)); - acpigen_write_name_integer("_UID", 0); - if (dev->chip_ops) - acpigen_write_name_string("_DDN", dev->chip_ops->name); - - /* Address */ - address = PCI_SLOT(dev->path.pci.devfn) & 0xffff; - address <<= 16; - address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff; - acpigen_write_name_dword("_ADR", address); - - /* Wake capabilities */ - if (config && config->wake) - acpigen_write_PRW(config->wake, 3); - - /* Fill regulatory domain structure */ - if (CONFIG(HAVE_REGULATORY_DOMAIN)) { - /* - * Name ("WRDD", Package () { - * WRDD_REVISION, // Revision - * Package () { - * WRDD_DOMAIN_TYPE_WIFI, // Domain Type, 7:WiFi - * wifi_regulatory_domain() // Country Identifier - * } - * }) - */ - acpigen_write_name("WRDD"); - acpigen_write_package(2); - acpigen_write_integer(WRDD_REVISION); - acpigen_write_package(2); - acpigen_write_dword(WRDD_DOMAIN_TYPE_WIFI); - acpigen_write_dword(wifi_regulatory_domain()); - acpigen_pop_len(); - acpigen_pop_len(); + if (config) { + generic_config.wake = config->wake; + /* By default, all intel wifi chips wake from S3 */ + generic_config.maxsleep = 3; } - - /* Fill Wifi sar related ACPI structures */ - if (CONFIG(USE_SAR)) - emit_sar_acpi_structures(); - - acpigen_pop_len(); /* Device */ - acpigen_pop_len(); /* Scope */ - - printk(BIOS_INFO, "%s.%s: %s %s\n", path, acpi_device_name(dev), - dev->chip_ops ? dev->chip_ops->name : "", dev_path(dev)); -} - -static const char *intel_wifi_acpi_name(const struct device *dev) -{ - return "WIFI"; + generic_wifi_fill_ssdt(dev, config ? &generic_config : NULL); } #endif @@ -282,7 +103,7 @@ struct device_operations device_ops = { #endif .ops_pci = &pci_ops, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = intel_wifi_acpi_name, + .acpi_name = generic_wifi_acpi_name, .acpi_fill_ssdt_generator = intel_wifi_fill_ssdt, #endif }; diff --git a/src/drivers/wifi/Kconfig b/src/drivers/wifi/Kconfig new file mode 100644 index 0000000000..9b87f844f6 --- /dev/null +++ b/src/drivers/wifi/Kconfig @@ -0,0 +1,57 @@ +config DRIVERS_GENERIC_WIFI + bool + default n + depends on HAVE_ACPI_TABLES + help + When enabled, add identifiers in ACPI tables that are common + to WiFi chipsets from multiple vendors. + +if DRIVERS_GENERIC_WIFI + +config USE_SAR + bool + default n + help + Enable it when wifi driver uses SAR configuration feature. + VPD entry "wifi_sar" is read to get SAR settings, if its + not found driver may look into CBFS for default settigs. + WIFI_SAR_CBFS is option to enable CBFS lookup. + +config SAR_ENABLE + bool + default n + depends on USE_SAR + +config DSAR_ENABLE + bool + default n + depends on USE_SAR + +config GEO_SAR_ENABLE + bool + default n + depends on USE_SAR + +config WIFI_SAR_CBFS + bool "Enable SAR table addition to CBFS" + default n + depends on USE_SAR + help + wifi driver would look for "wifi_sar" vpd key and load SAR settings from + it, if the vpd key is not found then the driver tries to look for sar + settings from CBFS with file name wifi_sar_defaults.hex. + So OEM/ODM can override wifi sar with VPD. + +config WIFI_SAR_CBFS_FILEPATH + string "The cbfs file which has WIFI SAR defaults" + depends on WIFI_SAR_CBFS + default "src/mainboard/$(MAINBOARDDIR)/wifi_sar_defaults.hex" + +config DSAR_SET_NUM + hex "Number of SAR sets when D-SAR is enabled" + default 0x3 + depends on USE_SAR + help + There can be up to 3 optional SAR table sets. + +endif # DRIVERS_GENERIC_WIFI diff --git a/src/drivers/wifi/Makefile.inc b/src/drivers/wifi/Makefile.inc new file mode 100644 index 0000000000..d37015c7d3 --- /dev/null +++ b/src/drivers/wifi/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_WIFI) += generic.c diff --git a/src/drivers/wifi/generic.c b/src/drivers/wifi/generic.c new file mode 100644 index 0000000000..b593ffe8bc --- /dev/null +++ b/src/drivers/wifi/generic.c @@ -0,0 +1,245 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or (at your option) + * any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "generic_wifi.h" + +/* WRDS Spec Revision */ +#define WRDS_REVISION 0x0 + +/* EWRD Spec Revision */ +#define EWRD_REVISION 0x0 + +/* WRDS Domain type */ +#define WRDS_DOMAIN_TYPE_WIFI 0x7 + +/* EWRD Domain type */ +#define EWRD_DOMAIN_TYPE_WIFI 0x7 + +/* WGDS Domain type */ +#define WGDS_DOMAIN_TYPE_WIFI 0x7 + +/* + * WIFI ACPI NAME = "WF" + hex value of last 8 bits of dev_path_encode + '\0' + * The above representation returns unique and consistent name every time + * generate_wifi_acpi_name is invoked. The last 8 bits of dev_path_encode is + * chosen since it contains the bus address of the device. + */ +#define WIFI_ACPI_NAME_MAX_LEN 5 + +__weak +int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) +{ + return -1; +} + +static void emit_sar_acpi_structures(void) +{ + int i, j, package_size; + struct wifi_sar_limits sar_limits; + struct wifi_sar_delta_table *wgds; + + /* Retrieve the sar limits data */ + if (get_wifi_sar_limits(&sar_limits) < 0) { + printk(BIOS_ERR, "Error: failed from getting SAR limits!\n"); + return; + } + + /* + * Name ("WRDS", Package () { + * Revision, + * Package () { + * Domain Type, // 0x7:WiFi + * WiFi SAR BIOS, // BIOS SAR Enable/disable + * SAR Table Set // Set#1 of SAR Table (10 bytes) + * } + * }) + */ + acpigen_write_name("WRDS"); + acpigen_write_package(2); + acpigen_write_dword(WRDS_REVISION); + /* Emit 'Domain Type' + 'WiFi SAR BIOS' + 10 bytes for Set#1 */ + package_size = 1 + 1 + BYTES_PER_SAR_LIMIT; + acpigen_write_package(package_size); + acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI); + acpigen_write_dword(CONFIG(SAR_ENABLE)); + for (i = 0; i < BYTES_PER_SAR_LIMIT; i++) + acpigen_write_byte(sar_limits.sar_limit[0][i]); + acpigen_pop_len(); + acpigen_pop_len(); + + /* + * Name ("EWRD", Package () { + * Revision, + * Package () { + * Domain Type, // 0x7:WiFi + * Dynamic SAR Enable, // Dynamic SAR Enable/disable + * Extended SAR sets, // Number of optional SAR table sets + * SAR Table Set, // Set#2 of SAR Table (10 bytes) + * SAR Table Set, // Set#3 of SAR Table (10 bytes) + * SAR Table Set // Set#4 of SAR Table (10 bytes) + * } + * }) + */ + acpigen_write_name("EWRD"); + acpigen_write_package(2); + acpigen_write_dword(EWRD_REVISION); + /* + * Emit 'Domain Type' + "Dynamic SAR Enable' + 'Extended SAR sets' + * + number of bytes for Set#2 & 3 & 4 + */ + package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT; + acpigen_write_package(package_size); + acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI); + acpigen_write_dword(CONFIG(DSAR_ENABLE)); + acpigen_write_dword(CONFIG_DSAR_SET_NUM); + for (i = 1; i < NUM_SAR_LIMITS; i++) + for (j = 0; j < BYTES_PER_SAR_LIMIT; j++) + acpigen_write_byte(sar_limits.sar_limit[i][j]); + acpigen_pop_len(); + acpigen_pop_len(); + + + if (!CONFIG(GEO_SAR_ENABLE)) + return; + + /* + * Name ("WGDS", Package() { + * Revision, + * Package() { + * DomainType, // 0x7:WiFi + * WgdsWiFiSarDeltaGroup1PowerMax1, // Group 1 FCC 2400 Max + * WgdsWiFiSarDeltaGroup1PowerChainA1, // Group 1 FCC 2400 A Offset + * WgdsWiFiSarDeltaGroup1PowerChainB1, // Group 1 FCC 2400 B Offset + * WgdsWiFiSarDeltaGroup1PowerMax2, // Group 1 FCC 5200 Max + * WgdsWiFiSarDeltaGroup1PowerChainA2, // Group 1 FCC 5200 A Offset + * WgdsWiFiSarDeltaGroup1PowerChainB2, // Group 1 FCC 5200 B Offset + * WgdsWiFiSarDeltaGroup2PowerMax1, // Group 2 EC Jap 2400 Max + * WgdsWiFiSarDeltaGroup2PowerChainA1, // Group 2 EC Jap 2400 A Offset + * WgdsWiFiSarDeltaGroup2PowerChainB1, // Group 2 EC Jap 2400 B Offset + * WgdsWiFiSarDeltaGroup2PowerMax2, // Group 2 EC Jap 5200 Max + * WgdsWiFiSarDeltaGroup2PowerChainA2, // Group 2 EC Jap 5200 A Offset + * WgdsWiFiSarDeltaGroup2PowerChainB2, // Group 2 EC Jap 5200 B Offset + * WgdsWiFiSarDeltaGroup3PowerMax1, // Group 3 ROW 2400 Max + * WgdsWiFiSarDeltaGroup3PowerChainA1, // Group 3 ROW 2400 A Offset + * WgdsWiFiSarDeltaGroup3PowerChainB1, // Group 3 ROW 2400 B Offset + * WgdsWiFiSarDeltaGroup3PowerMax2, // Group 3 ROW 5200 Max + * WgdsWiFiSarDeltaGroup3PowerChainA2, // Group 3 ROW 5200 A Offset + * WgdsWiFiSarDeltaGroup3PowerChainB2, // Group 3 ROW 5200 B Offset + * } + * }) + */ + + wgds = &sar_limits.wgds; + acpigen_write_name("WGDS"); + acpigen_write_package(2); + acpigen_write_dword(wgds->version); + /* Emit 'Domain Type' + + * Group specific delta of power (6 bytes * NUM_WGDS_SAR_GROUPS) + */ + package_size = sizeof(sar_limits.wgds.group) + 1; + acpigen_write_package(package_size); + acpigen_write_dword(WGDS_DOMAIN_TYPE_WIFI); + for (i = 0; i < SAR_NUM_WGDS_GROUPS; i++) { + acpigen_write_byte(wgds->group[i].power_max_2400mhz); + acpigen_write_byte(wgds->group[i].power_chain_a_2400mhz); + acpigen_write_byte(wgds->group[i].power_chain_b_2400mhz); + acpigen_write_byte(wgds->group[i].power_max_5200mhz); + acpigen_write_byte(wgds->group[i].power_chain_a_5200mhz); + acpigen_write_byte(wgds->group[i].power_chain_b_5200mhz); + } + + acpigen_pop_len(); + acpigen_pop_len(); +} + +void generic_wifi_fill_ssdt(struct device *dev, + const struct generic_wifi_config *config) +{ + const char *path; + u32 address; + + if (!dev->enabled) + return; + + path = acpi_device_path(dev->bus->dev); + if (!path) + return; + + /* Device */ + acpigen_write_scope(path); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_integer("_UID", 0); + if (dev->chip_ops) + acpigen_write_name_string("_DDN", dev->chip_ops->name); + + /* Address */ + address = PCI_SLOT(dev->path.pci.devfn) & 0xffff; + address <<= 16; + address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff; + acpigen_write_name_dword("_ADR", address); + + /* Wake capabilities */ + if (config) + acpigen_write_PRW(config->wake, config->maxsleep); + + /* Fill regulatory domain structure */ + if (CONFIG(HAVE_REGULATORY_DOMAIN)) { + /* + * Name ("WRDD", Package () { + * WRDD_REVISION, // Revision + * Package () { + * WRDD_DOMAIN_TYPE_WIFI, // Domain Type, 7:WiFi + * wifi_regulatory_domain() // Country Identifier + * } + * }) + */ + acpigen_write_name("WRDD"); + acpigen_write_package(2); + acpigen_write_integer(WRDD_REVISION); + acpigen_write_package(2); + acpigen_write_dword(WRDD_DOMAIN_TYPE_WIFI); + acpigen_write_dword(wifi_regulatory_domain()); + acpigen_pop_len(); + acpigen_pop_len(); + } + + /* Fill Wifi sar related ACPI structures */ + if (CONFIG(USE_SAR)) + emit_sar_acpi_structures(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s.%s: %s %s\n", path, acpi_device_name(dev), + dev->chip_ops ? dev->chip_ops->name : "", dev_path(dev)); +} + +const char *generic_wifi_acpi_name(const struct device *dev) +{ + static char wifi_acpi_name[WIFI_ACPI_NAME_MAX_LEN]; + + snprintf(wifi_acpi_name, sizeof(wifi_acpi_name), "WF%02x", + (dev_path_encode(dev) & 0xff)); + return wifi_acpi_name; +} diff --git a/src/drivers/wifi/generic_wifi.h b/src/drivers/wifi/generic_wifi.h new file mode 100644 index 0000000000..5f17c3e297 --- /dev/null +++ b/src/drivers/wifi/generic_wifi.h @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _GENERIC_WIFI_H_ +#define _GENERIC_WIFI_H_ + +/** + * struct generic_wifi_config - Data structure to contain common wifi config + * @wake: Wake pin for ACPI _PRW + * @maxsleep: Maximum sleep state to wake from + */ +struct generic_wifi_config { + unsigned int wake; + unsigned int maxsleep; +}; + +/** + * wifi_fill_ssdt() - Fill ACPI SSDT table for WiFi controller + * @dev: Device structure corresponding to WiFi controller. + * @config: Common wifi config required to fill ACPI SSDT table. + * + * This function implements common device operation to help fill ACPI SSDT + * table for WiFi controller. + */ +void generic_wifi_fill_ssdt(struct device *dev, + const struct generic_wifi_config *config); + +/** + * wifi_acpi_name() - Get ACPI name for WiFi controller + * @dev: Device structure corresponding to WiFi controller. + * + * This function implements common device operation to get the ACPI name for + * WiFi controller. + * + * Return: string representing the ACPI name for WiFi controller. + */ +const char *generic_wifi_acpi_name(const struct device *dev); + +#endif /* _GENERIC_WIFI_H_ */ From d06828da989fd22cf5699887b6bcccbbc8f1e086 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 2 Jul 2019 09:55:01 -0600 Subject: [PATCH 214/231] drivers/intel/wifi: Make Intel wifi driver arch agnostic Mark Intel WiFi driver to depend on PCI and remove the dependency on x86 architecture. BUG=None BRANCH=None TEST=Compile and Boot to ChromeOS. Change-Id: I762007d53b43bbc78924ee8efe236d6a7ff4dc57 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/33959 Reviewed-by: Furquan Shaikh Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/drivers/intel/wifi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig index fc8700fa82..fb60c6fbe1 100644 --- a/src/drivers/intel/wifi/Kconfig +++ b/src/drivers/intel/wifi/Kconfig @@ -1,6 +1,6 @@ config DRIVERS_INTEL_WIFI bool "Support Intel PCI-e WiFi adapters" - depends on ARCH_X86 + depends on PCI default y if PCIEXP_PLUGIN_SUPPORT select DRIVERS_GENERIC_WIFI if HAVE_ACPI_TABLES help From 19398245b498e2ced39f3828f804c94bb82e9a14 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 11 Jul 2019 12:23:35 -0600 Subject: [PATCH 215/231] device/device_util: Fix encoding the USB device path USB device id does not get included because of the logical OR operation. Fix encoding the USB device path. BUG=None BRANCH=None TEST=Boot to ChromeOS. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I79317da6d9c7cd177bd7bbbba1f1ccebe076930a Reviewed-on: https://review.coreboot.org/c/coreboot/+/34245 Reviewed-by: Patrick Georgi Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/device/device_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/device_util.c b/src/device/device_util.c index 11954a1982..7ded1df435 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -145,7 +145,7 @@ u32 dev_path_encode(const struct device *dev) ret |= dev->path.spi.cs; break; case DEVICE_PATH_USB: - ret |= dev->path.usb.port_type << 8 || dev->path.usb.port_id; + ret |= dev->path.usb.port_type << 8 | dev->path.usb.port_id; break; case DEVICE_PATH_NONE: case DEVICE_PATH_MMIO: /* don't care */ From 31af70dd96406c596306f424ae929664e7862fc2 Mon Sep 17 00:00:00 2001 From: Keith Short Date: Thu, 11 Jul 2019 17:54:57 -0600 Subject: [PATCH 216/231] util/testing: Ensure coreboot-gerrit fails if libpayload build fails The JUnit output from the libpayload builds was getting deleted by the coreinfo build. Move the libpayload to later in the coreboot-gerrit job. Also add messages to stdout indicating the various libpayload configs that are built and a message indicating when all libpayload builds are complete. BUG=b:137380189 TEST=Upload test commit that includes a libpayload compile error and verify buildbot fails. Change-Id: I43b55f402216582dcf81be34171437be345572ab Signed-off-by: Keith Short Reviewed-on: https://review.coreboot.org/c/coreboot/+/34183 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- payloads/libpayload/Makefile.inc | 2 ++ util/testing/Makefile.inc | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 7787762b43..1fa07f9a7a 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -130,6 +130,7 @@ junit.xml: echo '' > $@.tmp for i in $(filter-out %.old,$(wildcard configs/*)); do \ $(MAKE) clean; \ + echo "Building libpayload for $$i"; \ cp "$$i" junit_config; \ $(MAKE) olddefconfig DOTCONFIG=junit_config V=$(V) Q=$(Q) 2>/dev/null >/dev/null; \ echo "" >> $@.tmp; \ @@ -146,6 +147,7 @@ junit.xml: echo "" >> $@.tmp; \ done echo "" >> $@.tmp + echo "libpayload build complete, test results in $@" mv $@.tmp $@ test-configs: diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index 2b98730275..80e29efc83 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -85,10 +85,10 @@ what-jenkins-does: util/lint/lint lint-extended --junit util/abuild/abuild -B -J $(if $(V),-v,) $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) -x -X $(top)/abuild-chromeos.xml util/abuild/abuild -B -J $(if $(V),-v,) $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) - (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) $(if $(JENKINS_NOCCACHE),,CONFIG_LP_CCACHE=y) V=$(V) Q=$(Q) junit.xml) $(foreach tool, $(TOOLLIST), $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR="util/$(tool)" BLD="$(tool)" MFLAGS= MAKEFLAGS= MAKETARGET= junit.xml; ) unset COREBOOT_BUILD_DIR;$(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/nvramcui BLD=nvramcui MFLAGS= MAKEFLAGS= MAKETARGET=all junit.xml unset COREBOOT_BUILD_DIR;$(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/coreinfo BLD=coreinfo MFLAGS= MAKEFLAGS= MAKETARGET=defaultbuild junit.xml + (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) $(if $(JENKINS_NOCCACHE),,CONFIG_LP_CCACHE=y) V=$(V) Q=$(Q) junit.xml) $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=util/romcc BLD=romcc MFLAGS= MAKEFLAGS= MAKETARGET=test junit.xml $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=src/soc/nvidia/tegra124/lp0 BLD=tegra124_lp0 MFLAGS= MAKEFLAGS= MAKETARGET=all junit.xml $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=src/soc/nvidia/tegra210/lp0 BLD=tegra120_lp0 MFLAGS= MAKEFLAGS= MAKETARGET=all junit.xml From e99c1985d587a8983917baf4c9a0609178eca109 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Mon, 24 Jun 2019 16:32:19 -0600 Subject: [PATCH 217/231] device/hypertransport.c: Remove dead assignment last_unitid is immediately overwritten in the do loop, so this assignment is not needed. This a relic from old code that commit 13f1c2af8b made obsolete, but was never removed. Change-Id: I2eecddd025f7a64b0a70fc07a61ebb43aba757d6 Signed-off-by: Jacob Garber Found-by: scan-build 8.0.0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34292 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/device/hypertransport.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index ccad5ce5a5..027c3ef1d4 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -291,7 +291,6 @@ static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned min_d prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP; /* If present, assign unitid to a hypertransport chain. */ - last_unitid = min_unitid -1; max_unitid = next_unitid = min_unitid; do { u8 pos; From d9642c3a64c9206df703609e392104fafeb8d258 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Fri, 12 Jul 2019 11:28:00 -0600 Subject: [PATCH 218/231] soc/nvidia/tegra124: Prevent implicit fallthrough SOR_LINK_SPEED_G5_4 is unsupported, but it is not invalid, so it suffices to return here instead of printing the next warning message. Change-Id: Ifca3c52635e9a39af42e6616821d1099c43c237c Signed-off-by: Jacob Garber Found-by: Coverity CID 1293137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34293 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/nvidia/tegra124/sor.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 9188f83abd..3bc50e813e 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -844,6 +844,7 @@ void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor) break; case SOR_LINK_SPEED_G5_4: printk(BIOS_WARNING, "T124 does not support 5.4G link clock.\n"); + return; default: printk(BIOS_WARNING, "Invalid sor link bandwidth: %d\n", sor->link_cfg->link_bw); From 67d2a522148ea537cf87aeb0b369e143b11bb8c5 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Fri, 12 Jul 2019 13:30:47 +0200 Subject: [PATCH 219/231] mb/up/squared: Enable Vtd Change-Id: Ie935f98f84772a53de92f0dd2d13a381f5dbaf89 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/34271 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/mainboard/up/squared/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index a71405f0fe..2a49db6a9e 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -1,5 +1,7 @@ chip soc/intel/apollolake + register "enable_vtd" = "1" + device cpu_cluster 0 on device lapic 0 on end end From 270bb0a4c475057414b80c113648892aede570d0 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 12 Jul 2019 18:11:29 +0530 Subject: [PATCH 220/231] soc/intel/icelake: Make use of PCH_DEVFN_HDA macro Change-Id: I3be530072a6981760e9fe31e43741b4b480d045e Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/34286 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/icelake/romstage/fsp_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 420c427e7a..4801bd9ff9 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -38,7 +38,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->SkipMbpHob = 1; /* If Audio Codec is enabled, enable FSP UPD */ - dev = pcidev_on_root(0x1f, 3); + dev = pcidev_path_on_root(PCH_DEVFN_HDA); if (!dev) m_cfg->PchHdaEnable = 0; else From 9fe5dde68d8f07a1f78785f48fc39e6acdc98e6b Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 12 Jul 2019 18:32:55 +0530 Subject: [PATCH 221/231] soc/intel/icelake: Update FSP UPDs if IGD is disable in devicetree This patch sets required FSP UPDs to skip IGD initialziation if devicetree has disable IGD. Change-Id: I34a02bff112f922cabd48c23bc76370892ec62d9 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/33739 Reviewed-by: Furquan Shaikh Reviewed-by: Aamir Bohra Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/fsp_params.c | 17 ++++++++++++++--- src/soc/intel/icelake/romstage/fsp_params.c | 17 ++++++++++++++--- 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 03b00d94fb..382b1843f4 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -80,9 +80,20 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) mainboard_silicon_init_params(params); - params->PeiGraphicsPeimInit = 1; - params->GtFreqMax = 2; - params->CdClock = 3; + dev = pcidev_path_on_root(SA_DEVFN_IGD); + + if (!dev || !dev->enabled) { + /* + * Skip IGD initialization in FSP in case device is disabled + * in the devicetree.cb. + */ + params->PeiGraphicsPeimInit = 0; + } else { + params->PeiGraphicsPeimInit = 1; + params->GtFreqMax = 2; + params->CdClock = 3; + } + /* Unlock upper 8 bytes of RTC RAM */ params->PchLockDownRtcMemoryLock = 0; diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 4801bd9ff9..89dc99a18a 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -25,11 +25,22 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_icelake_config *config) { unsigned int i; - const struct device *dev; + const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); uint32_t mask = 0; - /* Set IGD stolen size to 60MB. */ - m_cfg->IgdDvmt50PreAlloc = 0xFE; + if (!dev || !dev->enabled) { + /* + * Skip IGD initialization in FSP if device + * is disable in devicetree.cb. + */ + m_cfg->InternalGfx = 0; + m_cfg->IgdDvmt50PreAlloc = 0; + } else { + m_cfg->InternalGfx = 1; + /* Set IGD stolen size to 60MB. */ + m_cfg->IgdDvmt50PreAlloc = 0xFE; + } + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; From b56224408ef6ff152ba1544ea6c38cad26576c97 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 11 Jul 2019 09:22:02 +0200 Subject: [PATCH 222/231] src: Use '#include ' when needed Change-Id: Ic0483982e8115ae99367d08d8ed77b8a316f5405 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/34231 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/drivers/intel/fsp1_1/car.c | 1 - src/lib/bootblock.c | 1 + src/lib/decompressor.c | 1 + src/soc/intel/apollolake/bootblock/bootblock.c | 1 - src/soc/intel/denverton_ns/bootblock/bootblock.c | 1 - src/soc/qualcomm/qcs405/clock.c | 1 - src/soc/qualcomm/qcs405/gpio.c | 1 - src/soc/qualcomm/qcs405/soc.c | 1 - 8 files changed, 2 insertions(+), 6 deletions(-) diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 1e89a8eb89..19eb041eac 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -23,7 +23,6 @@ #include #include #include -#include /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index c28a67aceb..3925e90afe 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -21,6 +21,7 @@ #include #include #include +#include DECLARE_OPTIONAL_REGION(timestamp); diff --git a/src/lib/decompressor.c b/src/lib/decompressor.c index 0529d11390..eb7f16cd88 100644 --- a/src/lib/decompressor.c +++ b/src/lib/decompressor.c @@ -19,6 +19,7 @@ #include #include #include +#include extern u8 compressed_bootblock[]; asm ( diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index ac6903a9d2..7b4eaef430 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -35,7 +35,6 @@ #include #include #include -#include static const struct pad_config tpm_spi_configs[] = { #if CONFIG(SOC_INTEL_GLK) diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index 57e3a2e49b..e9800c8ae5 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -22,7 +22,6 @@ #include #include #include -#include #include const FSPT_UPD temp_ram_init_params = { diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 56824a430a..de42147432 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c index 7b2238d77f..fc58fae7ff 100644 --- a/src/soc/qualcomm/qcs405/gpio.c +++ b/src/soc/qualcomm/qcs405/gpio.c @@ -16,7 +16,6 @@ #include #include #include -#include #include void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c index b3bfb9918a..6735308143 100644 --- a/src/soc/qualcomm/qcs405/soc.c +++ b/src/soc/qualcomm/qcs405/soc.c @@ -15,7 +15,6 @@ #include #include -#include #include #include From 83ea46b933ffe6ae022bf013524c99f6fb99e5d1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 12 Jul 2019 22:50:12 +0200 Subject: [PATCH 223/231] lib/bootmode: Include 'vboot/misc.h' Don't include unneeded 'vendorcode/google/chromeos/chromeos.h', when only 'vboot/misc.h' is used. Change-Id: I99484c29e5a3e13f1fea277f13c2f08a8a46bd88 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/34295 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Joel Kitching --- src/lib/bootmode.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 51bbbe5dc0..083fd9d49d 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -16,7 +16,7 @@ #include #include -#include +#include static int gfx_init_done = -1; From 00ec56334220baba6ef5057a33e17319f91399ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 14 Jul 2019 06:04:11 +0300 Subject: [PATCH 224/231] configs/lenovo: Drop DEBUG_SMM_RELOCATION MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not implemented for TSEG. Change-Id: I279c546a921c0504cafaddcda855bd6ea3de7f8a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34325 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Arthur Heymans --- configs/config.lenovo_t400_all_debug_and_option_table | 1 - configs/config.lenovo_thinkpad_t430_all_debug_and_option_table | 1 - configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi | 1 - 3 files changed, 3 deletions(-) diff --git a/configs/config.lenovo_t400_all_debug_and_option_table b/configs/config.lenovo_t400_all_debug_and_option_table index 0ceee167d5..dc407478c7 100644 --- a/configs/config.lenovo_t400_all_debug_and_option_table +++ b/configs/config.lenovo_t400_all_debug_and_option_table @@ -7,7 +7,6 @@ CONFIG_DEBUG_CBFS=y CONFIG_DEBUG_RAM_SETUP=y CONFIG_DEBUG_SMBUS=y CONFIG_DEBUG_SMI=y -CONFIG_DEBUG_SMM_RELOCATION=y CONFIG_DEBUG_MALLOC=y CONFIG_DEBUG_ACPI=y CONFIG_DEBUG_BOOT_STATE=y diff --git a/configs/config.lenovo_thinkpad_t430_all_debug_and_option_table b/configs/config.lenovo_thinkpad_t430_all_debug_and_option_table index 2c387340cf..cb1da1e619 100644 --- a/configs/config.lenovo_thinkpad_t430_all_debug_and_option_table +++ b/configs/config.lenovo_thinkpad_t430_all_debug_and_option_table @@ -9,7 +9,6 @@ CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y CONFIG_DEBUG_RAM_SETUP=y CONFIG_DEBUG_SMBUS=y CONFIG_DEBUG_SMI=y -CONFIG_DEBUG_SMM_RELOCATION=y CONFIG_DEBUG_SPI_FLASH=y CONFIG_DEBUG_BOOT_STATE=y CONFIG_DEBUG_ADA_CODE=y diff --git a/configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi b/configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi index 697c26db5d..1579aa3e1f 100644 --- a/configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi +++ b/configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi @@ -6,7 +6,6 @@ CONFIG_FATAL_ASSERTS=y CONFIG_DEBUG_CBFS=y CONFIG_DEBUG_SMBUS=y CONFIG_DEBUG_SMI=y -CONFIG_DEBUG_SMM_RELOCATION=y CONFIG_DEBUG_MALLOC=y CONFIG_DEBUG_ACPI=y CONFIG_DEBUG_SPI_FLASH=y From 89463e333e2e8a1eca681f9d0417c230280fc541 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 12 Jul 2019 06:53:04 +0300 Subject: [PATCH 225/231] cpu/x86: Fix DEBUG_SMM_RELOCATION dependency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I8a5bf39203a5de38d03d1b54453b056ea846ca38 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34259 Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/cpu/x86/Kconfig.debug | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/x86/Kconfig.debug b/src/cpu/x86/Kconfig.debug index 1c615f94d4..056934107c 100644 --- a/src/cpu/x86/Kconfig.debug +++ b/src/cpu/x86/Kconfig.debug @@ -14,4 +14,4 @@ config DISPLAY_MTRRS config DEBUG_SMM_RELOCATION bool "Debug SMM relocation code" - depends on HAVE_SMI_HANDLER + depends on HAVE_SMI_HANDLER && SMM_ASEG From 6eccc99b9c652f3221dd1aee875728b2307979aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 13 Jul 2019 10:45:59 +0300 Subject: [PATCH 226/231] intel/cannonlake: Fix indentation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia3ec5fbdbbf2712fe314909e05aab1b135534630 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34301 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/soc/intel/cannonlake/acpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 26c28472e1..dce98c4ea6 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -209,9 +209,9 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) /* CPU core count */ gnvs->pcnt = dev_count_cpu(); - if (CONFIG(CONSOLE_CBMEM)) /* Update the mem console pointer. */ - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); + if (CONFIG(CONSOLE_CBMEM)) + gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ From 96d8e4317835ed490a3999f173c50a2c0a36314a Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 11 Jul 2019 16:21:15 +0200 Subject: [PATCH 227/231] Documentation: Add FSP bugs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As Intel doesn't even document known bugs add a list of FSP bugs here. Change-Id: I07819b83fb0c9437fc237472dfe943f78738347a Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/34239 Reviewed-by: Kyösti Mälkki Reviewed-by: Paul Menzel Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- Documentation/soc/intel/fsp/index.md | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index d7f44c6dee..6269445ff3 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -2,6 +2,39 @@ This section contains documentation about Intel-FSP in public domain. +## Bugs +As Intel doesn't even list known bugs, they are collected here until +those are fixed. If possible a workaround is described here as well. + +### BroadwellDEFsp + +* IA32_FEATURE_CONTROL MSR is locked in FSP-M + * Release MR2 + * Writing the MSR is required in ramstage for Intel TXT + * Workaround: none + * Issue on public tracker: [Issue 10] + +* FSP-S asserts if the thermal PCI device 00:1f.6 is disabled + * Release MR2 + * FSP expects the PCI device to be enabled + * FSP expects BARs to be properly assigned + * Workaround: Don't disable this PCI device + * Issue on public tracker: [Issue 13] + +### KabylakeFsp +* MfgId and ModulePartNum in the DIMM_INFO struct are empty + * Release 3.7.1 + * Those values are typically consumed by SMBIOS type 17 + * Workaround: none + * Issue on public tracker: [Issue 22] + +### BraswellFsp +* Internal UART can't be disabled using PcdEnableHsuart* + * Release MR2 + * Workaround: Disable internal UART manually after calling FSP + * Issue on public tracker: [Issue 10] + + ## Open Source Intel FSP specification * [About Intel FSP](https://firmware.intel.com/learn/fsp/about-intel-fsp) @@ -15,3 +48,13 @@ This section contains documentation about Intel-FSP in public domain. ## Additional Features in FSP 2.1 specification - [PPI](ppi/ppi.md) + +## Official bugtracker + +- [IntelFSP/FSP](https://github.com/IntelFsp/FSP/issues) + +[Issue 10]: https://github.com/IntelFsp/FSP/issues/10 +[Issue 13]: https://github.com/IntelFsp/FSP/issues/13 +[Issue 15]: https://github.com/IntelFsp/FSP/issues/15 +[Issue 22]: https://github.com/IntelFsp/FSP/issues/22 + From cac023161535253675a23f335b3fddedb395d57d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 30 Jun 2019 08:40:04 +0300 Subject: [PATCH 228/231] device: Remove device->ops from early stages MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I7a361187570716df94a3fd441ae78c0f805b1dda Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/33921 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/device/pci_device.c | 5 +++-- src/include/device/device.h | 2 +- src/include/device/pci.h | 9 --------- 3 files changed, 4 insertions(+), 12 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 2c724aad50..9c47085152 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -592,11 +592,12 @@ void pci_dev_set_resources(struct device *dev) void pci_dev_enable_resources(struct device *dev) { - const struct pci_operations *ops; + const struct pci_operations *ops = NULL; u16 command; /* Set the subsystem vendor and device ID for mainboard devices. */ - ops = ops_pci(dev); + if (dev->ops) + ops = dev->ops->ops_pci; if (dev->on_mainboard && ops && ops->set_subsystem) { if (CONFIG_SUBSYSTEM_VENDOR_ID) dev->subsystem_vendor = CONFIG_SUBSYSTEM_VENDOR_ID; diff --git a/src/include/device/device.h b/src/include/device/device.h index 007c51f629..676da65263 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -137,8 +137,8 @@ struct device { */ DEVTREE_CONST struct bus *link_list; - struct device_operations *ops; #if !DEVTREE_EARLY + struct device_operations *ops; struct chip_operations *chip_ops; const char *name; #if CONFIG(GENERATE_SMBIOS_TABLES) diff --git a/src/include/device/pci.h b/src/include/device/pci.h index c08b30af6f..fa695d440f 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -109,15 +109,6 @@ struct msix_entry *pci_msix_get_table(struct device *dev); #define PCI_IO_BRIDGE_ALIGN 4096 #define PCI_MEM_BRIDGE_ALIGN (1024*1024) -static inline const struct pci_operations *ops_pci(struct device *dev) -{ - const struct pci_operations *pops; - pops = 0; - if (dev && dev->ops) - pops = dev->ops->ops_pci; - return pops; -} - #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) From ec933135ceb8cadb64e902b542a00bbc62557a77 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 13 Jul 2019 20:03:34 -0600 Subject: [PATCH 229/231] util/amdfwtool: Do misc cleanup - Correct command line argument for microcode patches from -u to -O - Add #if PSP_COMBO around new_combo_dir() as it's only called when that's enabled. - Remove unused variable in integrate_bios_firmwares() - Correct enum type from amd_fw_type to amd_bios_type in register_fw_addr() Signed-off-by: Martin Roth Change-Id: I51c6dbe700505bc2e32443000ae55cb644051e42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34303 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- util/amdfwtool/amdfwtool.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index e8ac0b1ae9..b1d3d2ec79 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -211,7 +211,7 @@ static void usage(void) printf("-H | --apob-nv-size Size of S3 resume data\n"); printf("-y | --pmu-inst Add PMU firmware instruction portion\n"); printf("-G | --pmu-data Add PMU firmware data portion\n"); - printf("-u | --ucode Add microcode patch\n"); + printf("-O | --ucode Add microcode patch\n"); printf("-X | --mp2-config Add MP2 configuration\n"); printf("-V | --bios-bin Add compressed image; auto source address\n"); printf("-e | --bios-bin-src Address in flash of source if -V not used\n"); @@ -493,6 +493,7 @@ static void *new_psp_dir(context *ctx, int multi) return ptr; } +#if PSP_COMBO static void *new_combo_dir(context *ctx) { void *ptr; @@ -503,6 +504,7 @@ static void *new_combo_dir(context *ctx) + MAX_COMBO_ENTRIES * sizeof(psp_combo_entry); return ptr; } +#endif static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie) { @@ -800,7 +802,7 @@ static void integrate_bios_firmwares(context *ctx, uint32_t cookie) { ssize_t bytes; - unsigned int i, j, count; + unsigned int i, count; int level; /* This function can create a primary table, a secondary table, or a @@ -1090,7 +1092,7 @@ static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[]) } } -static void register_fw_addr(amd_fw_type type, char *src_str, +static void register_fw_addr(amd_bios_type type, char *src_str, char *dst_str, char *size_str) { int i; From d3ce8c844221bfbcfd64d14e3ed815a5a39fcd72 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 13 Jul 2019 20:13:07 -0600 Subject: [PATCH 230/231] util/amdfwtool: Add option to build verstage binary into the PSP For AMD's Family17h processors, verstage needs to be run in the PSP, before memory is initialized. This adds that binary into the PSP directory. See the Family17h documentation in the coreboot documentation directory for more information. BUG=b:137338769 TEST=Build, add test binary to mandolin board, boot Signed-off-by: Martin Roth Change-Id: I29002a1af51c59a2e6c715e15f3dc63e59cd5729 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34324 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- util/amdfwtool/amdfwtool.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index b1d3d2ec79..1ecb7aaaab 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -203,6 +203,7 @@ static void usage(void) printf("-K | --drv-entry-pts Add PSP driver entry points\n"); printf("-L | --ikek Add Wrapped iKEK\n"); printf("-Y | --s0i3drv Add s0i3 driver\n"); + printf("-Z | --verstage Add verstage\n"); printf("\nBIOS options:\n"); printf("-I | --instance Sets instance field for the next BIOS firmware\n"); printf("-a | --apcb Add AGESA PSP customization block\n"); @@ -290,6 +291,7 @@ typedef enum _amd_fw_type { AMD_ABL7 = 0x37, AMD_FW_PSP_WHITELIST = 0x3a, AMD_FW_L2_PTR = 0x40, + AMD_FW_PSP_VERSTAGE = 0x52, AMD_FW_IMC, AMD_FW_GEC, AMD_FW_XHCI, @@ -345,6 +347,7 @@ static amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 }, + { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH }, { .type = AMD_FW_INVALID }, }; @@ -975,8 +978,8 @@ static void integrate_bios_firmwares(context *ctx, fill_dir_header(biosdir, count, cookie); } - -static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:h"; +// Unused values: CDEPqR +static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:"; static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1008,6 +1011,7 @@ static struct option long_options[] = { {"secdebug", required_argument, 0, 'N' }, {"token-unlock", no_argument, 0, 'U' }, {"whitelist", required_argument, 0, 'W' }, + {"verstage", required_argument, 0, 'Z' }, /* BIOS Directory Table items */ {"instance", required_argument, 0, 'I' }, {"apcb", required_argument, 0, 'a' }, @@ -1322,6 +1326,10 @@ int main(int argc, char **argv) register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg); sub = instance = 0; break; + case 'Z': + register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); + sub = instance = 0; + break; case 'o': output = optarg; break; From 23c923ba727412eb151539c17c92b201316c0324 Mon Sep 17 00:00:00 2001 From: Casper Chang Date: Fri, 12 Jul 2019 22:06:05 +0800 Subject: [PATCH 231/231] mb/google/sarien/variants/arcada: Set data hold time for touchpad Elan's touchpad requires min 0.3us data hold time. To fine tune the data hold time of i2c1 to meet specification of Elan's touchpad. BUG=None BRANCH=None TEST=Verified data hold time of i2c1 is around 320ns Signed-off-by: Casper Chang Change-Id: I0fa9db3b50e74f193261be96bd9e305bb19841e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34288 Tested-by: build bot (Jenkins) Reviewed-by: Nick Crews Reviewed-by: Duncan Laurie --- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index ce960a74c0..cd1925840a 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -175,6 +175,7 @@ chip soc/intel/cannonlake .speed = I2C_SPEED_FAST, .rise_time_ns = 52, .fall_time_ns = 110, + .data_hold_time_ns = 330, }, .i2c[4] = { .early_init = 1,