sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

skylake: update processor power limits configuration

Browse Source 
Update processor power limit configuration parameters based on
common code base support for Intel Skylake SoC based platforms.

BRANCH=None
BUG=None
TEST=Built and tested on nami system

Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sumeet R Pawnikar
2020-05-10 01:24:11 +05:30
committed by Patrick Georgi
parent 19c2ce7639
commit 97c5464443
34 changed files with 121 additions and 260 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/mainboard/google/fizz/mainboard.c
View File

@@ -9,6 +9,7 @@
#include <ec/ec.h>
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <intelblocks/power_limit.h>
#include <variant/gpio.h>
#include <smbios.h>
#include <soc/gpio.h>
@@ -99,7 +100,7 @@ static uint8_t board_sku_id(void)
* | n (U22) | 29 | .9n | .9n | x(43) |
* +-------------+-----+---------+---------+-------+
*/
static void mainboard_set_power_limits(config_t *conf)
static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
{
enum usb_chg_type type;
u32 watts;
@@ -215,9 +216,11 @@ static unsigned long mainboard_write_acpi_tables(
static void mainboard_enable(struct device *dev)
{
struct soc_power_limits_config *soc_conf;
config_t *conf = config_of_soc();
mainboard_set_power_limits(conf);
soc_conf = &conf->power_limits_config;
mainboard_set_power_limits(soc_conf);
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;