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nb/intel/gm45: Enable 64bit support

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This patch does the following:
- Allow selecting 64bit from Kconfig
- Fix up integer to pointer conversion that gcc complains about
- Add a buildtest target in configs

Tested on Thinkpad X200: boots fine to the payload

Change-Id: Icb9c31a28ee231b87109b19c00ce2f8b48b5aefe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans
2022-05-06 12:22:32 +02:00
parent cc0b4527a6
commit 98435ed07a
6 changed files with 15 additions and 13 deletions
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10
src/northbridge/intel/gm45/raminit.c
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@@ -1577,15 +1577,15 @@ static void jedec_init(const timings_t *const timings,
const u32 rankaddr = raminit_get_rank_addr(ch, r);
printk(BIOS_DEBUG, "JEDEC init @0x%08x\n", rankaddr);
mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, DCC_SET_EREGx(2));
read32((u32 *)(rankaddr | WL));
read32p(rankaddr | WL);
mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, DCC_SET_EREGx(3));
read32((u32 *)rankaddr);
read32p(rankaddr);
mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, DCC_SET_EREGx(1));
read32((u32 *)(rankaddr | ODT_120OHMS | ODS_34OHMS));
read32p(rankaddr | ODT_120OHMS | ODS_34OHMS);
mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_SET_MREG);
read32((u32 *)(rankaddr | WR | DLL1 | CAS | INTERLEAVED));
read32p(rankaddr | WR | DLL1 | CAS | INTERLEAVED);
mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_SET_MREG);
read32((u32 *)(rankaddr | WR | CAS | INTERLEAVED));
read32p(rankaddr | WR | CAS | INTERLEAVED);
}
}