diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 82888bc626..3e82bbb4d3 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -197,6 +197,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	/* TODO: CPU RP Configs */
 	for (i = 0; i < 4; i++) {
 		params->CpuPcieRpAdvancedErrorReporting[i] = 0;
+		params->CpuPcieRpPtmEnabled[i] = 0;
 	}
 
 	/* Enable xDCI controller if enabled in devicetree and allowed */