From 9847012bc6f3dd2b6e58aff46881222cf0953402 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Tue, 17 Nov 2020 19:26:27 -0700 Subject: [PATCH] Disable Precision Time Measurement for CPU PCIe ports Change-Id: I007b6825a7d558254f890723ef568b96d9e884bc --- src/soc/intel/tigerlake/fsp_params.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 82888bc626..3e82bbb4d3 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -197,6 +197,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* TODO: CPU RP Configs */ for (i = 0; i < 4; i++) { params->CpuPcieRpAdvancedErrorReporting[i] = 0; + params->CpuPcieRpPtmEnabled[i] = 0; } /* Enable xDCI controller if enabled in devicetree and allowed */