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cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE

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Increase DCACHE_RAM_SIZE to 32kB and remove "NO_CBFS_MCACHE".
It’s quite safe to increase DCACHE_RAM_SIZE. All LGA775 targets
should have at least 256K L2 cache. That is plenty for XIP RO cache of
bootblock + romstage and a 32K CAR.

Change-Id: I393b2727bd90a990c3108a4dbead62b17d7fc531
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Elyes HAOUAS
2021-01-05 14:38:57 +01:00
committed by Arthur Heymans
parent 083702c32e
commit 985821c4f2
4 changed files with 1 additions and 4 deletions
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src/cpu/intel/socket_LGA775/Kconfig
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@ -17,7 +17,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
config DCACHE_RAM_SIZE
hex
default 0x4000 # 16 kB
default 0x8000 # 32 kB
config DCACHE_BSP_STACK_SIZE
hex