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vc/mediatek/mt8195: Remove unused code

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Remove unused drivers and some fast calibration implementations
to align with the latest MTK memory reference code.

TEST=boot to kernel

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I2e6be2e16c139e48c65352fe2eabf16bf9cd550a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57978
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ryan Chuang
2021-09-23 20:35:22 +08:00
committed by Hung-Te Lin
parent 9af3de12f6
commit 98affb68f0
13 changed files with 6 additions and 13577 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c
View File

@ -839,16 +839,6 @@ static void DRAMC_COMMON_Config(DRAMC_CTX_T *p)
vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DBG_IRQ_CTRL7), 0xFFFFFFFF);
}
#if 0
void DVFS_config(DRAMC_CTX_T *p)
{
U8 DVFS_NO_QUEUE_FLASH = 0;
//1. DVFS flow control
//2. Relationship among groups -- Save & Restore
}
#endif
static void IO_Release(DRAMC_CTX_T *p)
{

139
src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c
View File

@ -441,17 +441,6 @@ static void DIG_CONFIG_SHUF_DBI(DRAMC_CTX_T *p, int ch_id, int group_id)
RD_DBI_EN = LP4_temp.DBI_RD;
WR_DBI_EN = LP4_temp.DBI_WR;
}
#if __LP5_COMBO__
else
{//TODO LPDDR5 and other dram type not ready
LP5_DRAM_CONFIG_T LP5_temp;
memset((void *)&LP5_temp, 0, sizeof(LP5_temp));
LP5_DRAM_config(DFS(group_id),&LP5_temp);
RD_DBI_EN = LP5_temp.DBI_RD;
WR_DBI_EN = LP5_temp.DBI_WR;
}
#endif
vSetPHY2ChannelMapping(p, ch_id);
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
@ -504,134 +493,6 @@ static void DIG_CONFIG_SHUF_DVFSWLRL(DRAMC_CTX_T *p, int ch_id, int group_id)
mcSHOW_DBG_MSG6(("[test_sa.c]====>ch_id:%2d, group_id:%2d, DPI_TBA_DVFS_WLRL_setting Exit\n", ch_id, group_id));
}
#if __LP5_COMBO__
void DIG_CONFG_SHU_LP5_WCK(DRAMC_CTX_T *p, int ch_id, int group_id)
{
U8 backup_ch_id = p->channel;
u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
U8 BYTEMODE_EN=0;//TODO
U8 READ_DBI=0;
U8 DVFSC_DIS=0;
U8 WCK_offset_by_UI=0;
U8 tWCKENL_WR=0;
U8 tWCKPRE_WR_Static=0;
U8 tWCKENL_RD_DBION=0;
U8 tWCKENL_RD_DBIOFF=0;
U8 tWCKPRE_RD_Static=0;
U8 tWCKENL_FS=0;
U8 tWCKPRE_FS_Static=0;
U8 WCK_WR_MCK=0;
U8 WCK_RD_MCK=0;
U8 WCK_FS_MCK=0;
U8 WCK_WR_UI=0;
U8 WCK_RD_UI=0;
U8 WCK_FS_UI=0;
U8 irank = 0;
U8 ui_ratio = 2;
//write and FS
if(DFS(group_id)->CKR==2) {
if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_WR =1;tWCKPRE_WR_Static =1;tWCKENL_FS =0;tWCKPRE_FS_Static =1;}
else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_WR =0;tWCKPRE_WR_Static =2;tWCKENL_FS =0;tWCKPRE_FS_Static =2;}
else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_WR =1;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_WR =2;tWCKPRE_WR_Static =3;tWCKENL_FS =1;tWCKPRE_FS_Static =3;}
else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_WR =1;tWCKPRE_WR_Static =4;tWCKENL_FS =1;tWCKPRE_FS_Static =4;}
else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_WR =3;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
} else if (DFS(group_id)->CKR==4){
if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_WR =0;tWCKPRE_WR_Static =1;tWCKENL_FS =0;tWCKPRE_FS_Static =1;}
else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_WR =0;tWCKPRE_WR_Static =1;tWCKENL_FS =0;tWCKPRE_FS_Static =1;}
else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_WR =1;tWCKPRE_WR_Static =1;tWCKENL_FS =1;tWCKPRE_FS_Static =1;}
else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_WR =1;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_WR =1;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_WR =2;tWCKPRE_WR_Static =2;tWCKENL_FS =1;tWCKPRE_FS_Static =2;}
else if(((DFS(group_id)->data_rate)>3200) && (((DFS(group_id)->data_rate)<=3733))) {tWCKENL_WR =2;tWCKPRE_WR_Static =3;tWCKENL_FS =1;tWCKPRE_FS_Static =3;}
else if(((DFS(group_id)->data_rate)>3733) && (((DFS(group_id)->data_rate)<=4267))) {tWCKENL_WR =2;tWCKPRE_WR_Static =3;tWCKENL_FS =1;tWCKPRE_FS_Static =3;}
else if(((DFS(group_id)->data_rate)>4267) && (((DFS(group_id)->data_rate)<=4800))) {tWCKENL_WR =3;tWCKPRE_WR_Static =3;tWCKENL_FS =2;tWCKPRE_FS_Static =3;}
else if(((DFS(group_id)->data_rate)>4800) && (((DFS(group_id)->data_rate)<=5500))) {tWCKENL_WR =3;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
else if(((DFS(group_id)->data_rate)>5500) && (((DFS(group_id)->data_rate)<=6000))) {tWCKENL_WR =4;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
else if(((DFS(group_id)->data_rate)>6000) && (((DFS(group_id)->data_rate)<=6400))) {tWCKENL_WR =4;tWCKPRE_WR_Static =4;tWCKENL_FS =2;tWCKPRE_FS_Static =4;}
} else {
mcSHOW_ERR_MSG(("[DIG_CONFG_SHU_LP5_WCK] ERROR: Unexpected CKR!!! "));
}
//read
if(DVFSC_DIS == 1)
{
if(DFS(group_id)->CKR==2) {
if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =2;}
else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =1;tWCKENL_RD_DBION =BYTEMODE_EN?3:1;tWCKPRE_RD_Static =2;}
else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?4:2;tWCKENL_RD_DBION =4;tWCKPRE_RD_Static =3;}
else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_RD_DBIOFF =3;tWCKENL_RD_DBION =BYTEMODE_EN?5:3;tWCKPRE_RD_Static =4;}
else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?7:5;tWCKENL_RD_DBION =7;tWCKPRE_RD_Static =4;}
} else if (DFS(group_id)->CKR==4){
if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =1;tWCKENL_RD_DBION =BYTEMODE_EN?2:1;tWCKPRE_RD_Static =1;}
else if(((DFS(group_id)->data_rate)>1600) && (((DFS(group_id)->data_rate)<=2133))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?2:1;tWCKENL_RD_DBION =2;tWCKPRE_RD_Static =2;}
else if(((DFS(group_id)->data_rate)>2133) && (((DFS(group_id)->data_rate)<=2750))) {tWCKENL_RD_DBIOFF =2;tWCKENL_RD_DBION =BYTEMODE_EN?3:2;tWCKPRE_RD_Static =2;}
else if(((DFS(group_id)->data_rate)>2750) && (((DFS(group_id)->data_rate)<=3200))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?4:3;tWCKENL_RD_DBION =4;tWCKPRE_RD_Static =2;}
else if(((DFS(group_id)->data_rate)>3200) && (((DFS(group_id)->data_rate)<=3733))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?4:3;tWCKENL_RD_DBION =BYTEMODE_EN?5:4;tWCKPRE_RD_Static =3;}
else if(((DFS(group_id)->data_rate)>3733) && (((DFS(group_id)->data_rate)<=4267))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?5:4;tWCKENL_RD_DBION =BYTEMODE_EN?6:5;tWCKPRE_RD_Static =3;}
else if(((DFS(group_id)->data_rate)>4267) && (((DFS(group_id)->data_rate)<=4800))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?6:5;tWCKENL_RD_DBION =BYTEMODE_EN?7:6;tWCKPRE_RD_Static =3;}
else if(((DFS(group_id)->data_rate)>4800) && (((DFS(group_id)->data_rate)<=5500))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?7:6;tWCKENL_RD_DBION =BYTEMODE_EN?8:7;tWCKPRE_RD_Static =4;}
else if(((DFS(group_id)->data_rate)>5500) && (((DFS(group_id)->data_rate)<=6000))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?7:6;tWCKENL_RD_DBION =BYTEMODE_EN?9:7;tWCKPRE_RD_Static =4;}
else if(((DFS(group_id)->data_rate)>6000) && (((DFS(group_id)->data_rate)<=6400))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?8:7;tWCKENL_RD_DBION =BYTEMODE_EN?10:8;tWCKPRE_RD_Static=4;}
} else {
mcSHOW_ERR_MSG(("[DIG_CONFG_SHU_LP5_WCK] ERROR: Unexpected CKR!!! "));
}
} else {
if(DFS(group_id)->CKR==2) {
if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?2:0;tWCKENL_RD_DBION =2;tWCKPRE_RD_Static =2;}
else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =3;tWCKENL_RD_DBION =BYTEMODE_EN?5:3;tWCKPRE_RD_Static =2;}
} else if (DFS(group_id)->CKR==4){
if(((DFS(group_id)->data_rate)> 40) && (((DFS(group_id)->data_rate)<= 533))) {tWCKENL_RD_DBIOFF =0;tWCKENL_RD_DBION =0;tWCKPRE_RD_Static =1;}
else if(((DFS(group_id)->data_rate)> 533) && (((DFS(group_id)->data_rate)<=1067))) {tWCKENL_RD_DBIOFF =BYTEMODE_EN?1:0;tWCKENL_RD_DBION =1;tWCKPRE_RD_Static =1;}
else if(((DFS(group_id)->data_rate)>1067) && (((DFS(group_id)->data_rate)<=1600))) {tWCKENL_RD_DBIOFF =2;tWCKENL_RD_DBION =BYTEMODE_EN?3:2;tWCKPRE_RD_Static =1;}
} else {
mcSHOW_ERR_MSG(("[DIG_CONFG_SHU_LP5_WCK] ERROR: Unexpected CKR!!! "));
}
}
//=====================================
//Algrithm
//=====================================
WCK_offset_by_UI = (DFS(group_id)->DQ_P2S_RATIO==4) ? 0 :
(DFS(group_id)->DQ_P2S_RATIO==8) ? ((DFS(group_id)->CKR==4) ? 1 : -5) :
(DFS(group_id)->DQ_P2S_RATIO==16) ? -5 : 0;
WCK_WR_UI = ((tWCKENL_WR + tWCKPRE_WR_Static) * DFS(group_id)->CKR * ui_ratio) + WCK_offset_by_UI;
WCK_RD_UI = (((READ_DBI?tWCKENL_RD_DBION:tWCKENL_RD_DBIOFF) + tWCKPRE_RD_Static) * DFS(group_id)->CKR * ui_ratio) + WCK_offset_by_UI;
WCK_FS_UI = ((tWCKENL_FS + tWCKPRE_FS_Static) * DFS(group_id)->CKR * ui_ratio) + WCK_offset_by_UI;
//=====================================
//setting
//=====================================
p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
for(irank = RANK_0; irank < RANK_MAX; irank++)
{
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_WR_MCK), P_Fld(WCK_WR_MCK, SHURK_WCK_WR_MCK_WCK_WR_B0_MCK) \
| P_Fld(WCK_WR_MCK, SHURK_WCK_WR_MCK_WCK_WR_B1_MCK));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_RD_MCK), P_Fld(WCK_RD_MCK, SHURK_WCK_RD_MCK_WCK_RD_B0_MCK) \
| P_Fld(WCK_RD_MCK, SHURK_WCK_RD_MCK_WCK_RD_B1_MCK));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_FS_MCK), P_Fld(WCK_FS_MCK, SHURK_WCK_FS_MCK_WCK_FS_B0_MCK) \
| P_Fld(WCK_FS_MCK, SHURK_WCK_FS_MCK_WCK_FS_B1_MCK));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_WR_UI) , P_Fld(WCK_WR_UI , SHURK_WCK_WR_UI_WCK_WR_B0_UI ) \
| P_Fld(WCK_WR_UI , SHURK_WCK_WR_UI_WCK_WR_B1_UI ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_RD_UI) , P_Fld(WCK_RD_UI , SHURK_WCK_RD_UI_WCK_RD_B0_UI ) \
| P_Fld(WCK_RD_UI , SHURK_WCK_RD_UI_WCK_RD_B1_UI ));
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_WCK_FS_UI) , P_Fld(WCK_FS_UI , SHURK_WCK_FS_UI_WCK_FS_B0_UI ) \
| P_Fld(WCK_FS_UI , SHURK_WCK_FS_UI_WCK_FS_B1_UI ));
}
vSetPHY2ChannelMapping(p, backup_ch_id);
p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
}
#endif
//=================================================
//Jump ratio calculate and setting

31
src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c
View File

@ -278,37 +278,6 @@ void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr)
//[3733:6400] 4
//[400 :3733) 2
#if __LP5_COMBO__
else if (MEM_TYPE == LPDDR5)
{
#if SA_CONFIG_EN
if(p->freq_sel==LP5_DDR4266)
{
(tr->DFS_GP[0])->data_rate = 4266; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 2;
}
else if(p->freq_sel==LP5_DDR5500)
{
(tr->DFS_GP[0])->data_rate = 5500; (tr->DFS_GP[0])->DQ_P2S_RATIO = 16 ; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 2;
}
else
{
(tr->DFS_GP[0])->data_rate = 3200; (tr->DFS_GP[0])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[0]->CKR = 2;tr->DFS_GP[0]->DQSIEN_MODE = 1;
}
#else
(tr->DFS_GP[0])->data_rate = 6400; (tr->DFS_GP[0])->DQ_P2S_RATIO = 16; tr->DFS_GP[0]->CKR = 4;tr->DFS_GP[0]->DQSIEN_MODE = 1;
#endif
(tr->DFS_GP[1])->data_rate = 3200; (tr->DFS_GP[1])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[1]->CKR = 2;tr->DFS_GP[1]->DQSIEN_MODE = 1;
(tr->DFS_GP[2])->data_rate = 1600; (tr->DFS_GP[2])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[2]->CKR = 2;tr->DFS_GP[2]->DQSIEN_MODE = 1;
(tr->DFS_GP[3])->data_rate = 4266; (tr->DFS_GP[3])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[3]->CKR = 4;tr->DFS_GP[3]->DQSIEN_MODE = 1;
(tr->DFS_GP[4])->data_rate = 3733; (tr->DFS_GP[4])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[4]->CKR = 4;tr->DFS_GP[4]->DQSIEN_MODE = 1;
(tr->DFS_GP[5])->data_rate = 1600; (tr->DFS_GP[5])->DQ_P2S_RATIO = 8 ; tr->DFS_GP[5]->CKR = 2;tr->DFS_GP[5]->DQSIEN_MODE = 1;
(tr->DFS_GP[6])->data_rate = 1200; (tr->DFS_GP[6])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[6]->CKR = 2;tr->DFS_GP[6]->DQSIEN_MODE = 1;
(tr->DFS_GP[7])->data_rate = 800 ; (tr->DFS_GP[7])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[7]->CKR = 2;tr->DFS_GP[7]->DQSIEN_MODE = 1;
(tr->DFS_GP[8])->data_rate = 400 ; (tr->DFS_GP[8])->DQ_P2S_RATIO = 4 ; tr->DFS_GP[8]->CKR = 2;tr->DFS_GP[8]->DQSIEN_MODE = 1;
(tr->DFS_GP[9])->data_rate = 5500; (tr->DFS_GP[9])->DQ_P2S_RATIO = 16; tr->DFS_GP[9]->CKR = 4;tr->DFS_GP[9]->DQSIEN_MODE = 1;
LP5_DRAM_config(tr->DFS_GP[0],tr->lp5_init);
}
#endif
ANA_TOP_FUNCTION_CFG(tr->a_cfg,tr->DFS_GP[0]->data_rate);
ANA_CLK_DIV_config(tr->a_opt,tr->DFS_GP[0]);
mcSHOW_DBG_MSG6(("=================================== \n"));

287
src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c
View File

@ -126,291 +126,4 @@ U32 Get_WL_by_MR_LP4(U8 Version, U8 MR_WL_field_value)
return WL;
}
#if __LP5_COMBO__
U32 Get_RL_LP5_DVFSC_DIS( U8 MR_RL_field_value, U8 DBI_EN, U8 BYTE_MODE_EN,U8 CKR)
{
U32 RL=0;
if(CKR == 2)
{
switch(MR_RL_field_value)
{
case 0 : {RL = 6; break;}
case 1 : {RL = 8; break;}
case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 12 : 10 ) : 10); break;}
case 3 : {RL = ((BYTE_MODE_EN == 1) ? ( 14 ) : ((DBI_EN == 1) ? 14 : 12 )); break;}
case 4 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 18 : 16 ) : ( 16 )); break;}
case 5 : {RL = ((BYTE_MODE_EN == 1) ? ( 20 ) : ((DBI_EN == 1) ? 20 : 18 )); break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else if (CKR == 4)
{
switch(MR_RL_field_value)
{
case 0 : {RL = 3; break;}
case 1 : {RL = 4; break;}
case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 6 : 5 ) : ( 5 )); break;}
case 3 : {RL = ((BYTE_MODE_EN == 1) ? 7 : ((DBI_EN == 1) ? 7 : 6 )); break;}
case 4 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 9 : 8 ) : ( 8 )); break;}
case 5 : {RL = ((BYTE_MODE_EN == 1) ? 10 : ((DBI_EN == 1) ? 10 : 9 )); break;}
case 6 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 12 : 11 ) : ((DBI_EN == 1) ? 11 : 10)); break;}
case 7 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 14 : 13 ) : ((DBI_EN == 1) ? 13 : 12)); break;}
case 8 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 15 : 14 ) : ((DBI_EN == 1) ? 14 : 13)); break;}
case 9 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 17 : 16 ) : ((DBI_EN == 1) ? 16 : 15)); break;}
case 10: {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 19 : 17 ) : ((DBI_EN == 1) ? 17 : 16)); break;}
case 11: {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 20 : 18 ) : ((DBI_EN == 1) ? 18 : 17)); break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else
{
mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected CKR:%1d under LPDDR5 \n",CKR));
}
mcSHOW_DBG_MSG(("[ReadLatency GET] DVFSC_DIS:BYTE_MODE_EN:%1d-DBI_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,DBI_EN,MR_RL_field_value,CKR,RL));
return RL;
}
U32 Get_RL_LP5_DVFSC_EN( U8 MR_RL_field_value, U8 DBI_EN, U8 BYTE_MODE_EN,U8 CKR)
{
U32 RL=0;
if(CKR == 2)
{
switch(MR_RL_field_value)
{
case 0 : {RL = 6; break;}
case 1 : {RL = ((BYTE_MODE_EN == 1) ? 10 : ((DBI_EN == 1) ? 10 : 8 )); break;}
case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 14 : 12 ) : 12); break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN: Unexpected MR_RL_field_value:%1d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else if (CKR == 4)
{
switch(MR_RL_field_value)
{
case 0 : {RL = 3; break;}
case 1 : {RL = ((BYTE_MODE_EN == 1) ? 5 : ((DBI_EN == 1) ? 4 : 5 )); break;}
case 2 : {RL = ((BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 7 : 6 ) : 6); break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else
{
mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected CKR:%1d under LPDDR5 \n",CKR));
}
mcSHOW_DBG_MSG(("[ReadLatency GET] DVFSC_EN: BYTE_MODE_EN:%1d-DBI_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,DBI_EN,MR_RL_field_value,CKR,RL));
return RL;
}
//LPDDR5 write Latency Version B not implemented --TODO
U32 Get_WL_LP5_DVFSC_DIS( U8 MR_RL_field_value,U8 BYTE_MODE_EN,U8 CKR)
{
U32 WL=0;
if(CKR == 2)
{
switch(MR_RL_field_value)
{
case 0 : {WL = 4; break;}
case 1 : {WL = 4; break;}
case 2 : {WL = 6; break;}
case 3 : {WL = 8; break;}
case 4 : {WL = 8; break;}
case 5 : {WL = 10; break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%1d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else if (CKR == 4)
{
switch(MR_RL_field_value)
{
case 0 : {WL = 2; break;}
case 1 : {WL = 2; break;}
case 2 : {WL = 3; break;}
case 3 : {WL = 4; break;}
case 4 : {WL = 4; break;}
case 5 : {WL = 5; break;}
case 6 : {WL = 6; break;}
case 7 : {WL = 6; break;}
case 8 : {WL = 7; break;}
case 9 : {WL = 8; break;}
case 10: {WL = 9; break;}
case 11: {WL = 9; break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else
{
mcSHOW_ERR_MSG(("ERROR: DVFSC_DIS:Unexpected CKR:%1d under LPDDR5 \n",CKR));
}
mcSHOW_DBG_MSG(("[WriteLatency GET] DVFSC_DIS:BYTE_MODE_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,MR_RL_field_value,CKR,WL));
return WL;
}
//LPDDR5 write Latency Version B not implemented --TODO
U32 Get_WL_LP5_DVFSC_EN( U8 MR_RL_field_value, U8 BYTE_MODE_EN,U8 CKR)
{
U32 WL=0;
if(CKR == 2)
{
switch(MR_RL_field_value)
{
case 0 : {WL = 4; break;}
case 1 : {WL = 4; break;}
case 2 : {WL = 6; break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN: Unexpected MR_RL_field_value:%1d -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else if (CKR == 4)
{
switch(MR_RL_field_value)
{
case 0 : {WL = 2; break;}
case 1 : {WL = 2; break;}
case 2 : {WL = 3; break;}
default:{mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected MR_RL_field_value:%1x -CKR:%1d under LPDDR5, \n",MR_RL_field_value,CKR));}
}
}
else
{
mcSHOW_ERR_MSG(("ERROR: DVFSC_EN:Unexpected CKR:%1d under LPDDR5 \n",CKR));
}
mcSHOW_DBG_MSG(("[WriteLatency GET] DVFSC_EN: BYTE_MODE_EN:%1d-MR_RL_field_value:%1x-CKR:%2d-RL:%2d\n",BYTE_MODE_EN,MR_RL_field_value,CKR,WL));
return WL;
}
//LP5 dram initial ModeRegister setting
U8 LP5_DRAM_INIT_RLWL_MRfield_config(U32 data_rate)
{
U8 MR2_RLWL=0;
if ((data_rate<=6400) && (data_rate > 6000)) {MR2_RLWL = 11 ;}
else if ((data_rate<=6400) && (data_rate > 5500)) {MR2_RLWL = 10 ;}
else if ((data_rate<=5500) && (data_rate > 4800)) {MR2_RLWL = 9 ;}
else if ((data_rate<=4800) && (data_rate > 4266)) {MR2_RLWL = 8 ;}
else if ((data_rate<=4266) && (data_rate > 3733)) {MR2_RLWL = 7 ;}
else if ((data_rate<=3700) && (data_rate > 3200)) {MR2_RLWL = 6 ;}
else if ((data_rate<=3200) && (data_rate > 2400)) {MR2_RLWL = 5 ;}
else if ((data_rate<=2400) && (data_rate > 1866)) {MR2_RLWL = 4 ;}
else if ((data_rate<=1866) && (data_rate > 1600)) {MR2_RLWL = 3 ;}
else if ((data_rate<=1600) && (data_rate >= 800)) {MR2_RLWL = 2 ;}
else {mcSHOW_ERR_MSG(("ERROR: Unexpected data_rate:%4d under LPDDR5 \n",data_rate));return -1;}
mcSHOW_DBG_MSG(("[ModeRegister RLWL Config] data_rate:%4d-MR2_RLWL:%1x\n",data_rate,MR2_RLWL));
return MR2_RLWL;
}
void LP5_DRAM_config(DRAMC_DVFS_GROUP_CONFIG_T *dfs_tr, LP5_DRAM_CONFIG_T *tr)
{
tr->BYTE_MODE[0] = 0 ;
tr->BYTE_MODE[1] = 0 ;
tr->EX_ROW_EN[0] = 0 ;
tr->EX_ROW_EN[1] = 0 ;
tr->MR_WL = LP5_DRAM_INIT_RLWL_MRfield_config(dfs_tr->data_rate);
tr->MR_RL = tr->MR_WL;
tr->BL = 2;
tr->CK_Mode = (dfs_tr->data_rate>=2133)?0:1; //0:diff 1:SE
tr->RPST = 0;
tr->RD_PRE = 0;
tr->WR_PRE = 1;
tr->WR_PST = (dfs_tr->data_rate>=3200)?1:0 ;
#if SA_CONFIG_EN
tr->DBI_WR = 0;
#if LP5_DDR4266_RDBI_WORKAROUND
tr->DBI_RD = (dfs_tr->data_rate>=3733)?1:0 ;
#else
tr->DBI_RD = 0;
#endif
#else
tr->DBI_WR = (dfs_tr->data_rate>=3733)?1:0 ;
tr->DBI_RD = (dfs_tr->data_rate>=3733)?1:0 ;
#endif
tr->DMI = 1;
tr->OTF = 1;
tr->WCK_PST = (dfs_tr->data_rate>=3733)?1:0 ;
tr->RDQS_PST = 0;
tr->CA_ODT = 0;
tr->DQ_ODT = (dfs_tr->data_rate>=3733)?3:0 ;
tr->CKR = (dfs_tr->CKR==4)?0:1;
tr->WCK_ON = 0; //TODO
#if SA_CONFIG_EN
#if WCK_LEVELING_FM_WORKAROUND
tr->WCK_FM = 0;
#else
tr->WCK_FM = (dfs_tr->data_rate>=2133)?1:0;
#endif
#else
tr->WCK_FM = (dfs_tr->data_rate>=2133)?1:0;
#endif
tr->WCK_ODT = (dfs_tr->CKR==4)?3:0;
tr->DVFSQ = (dfs_tr->data_rate>=3733)?0:1;
tr->DVFSC = (dfs_tr->data_rate>=2133)?0:1;
tr->RDQSmode[0] = EN_both;//TODO --RK0 have to EN_t if SE enable
tr->RDQSmode[1] = EN_both;//TODO --RK1 have to EN_c if SE enable
tr->WCKmode[0] = (dfs_tr->data_rate>=1600)?0:1;
tr->WCKmode[1] = (dfs_tr->data_rate>=1600)?0:2;
tr->RECC = 0;//TODO
tr->WECC = 0;//TODO
tr->BankMode = (dfs_tr->data_rate>=3733)?BG4BK4:BK16;
tr->WORK_FSP = 0;//TODO
switch (dfs_tr->DQSIEN_MODE)
{
case 1: {tr->RDQS_PRE = 0;break;}
case 2: {tr->RDQS_PRE = 1;break;}
case 3: {tr->RDQS_PRE = 3;break;}
case 6: {tr->RDQS_PRE = 1;break;}
case 7: {tr->RDQS_PRE = 3;break;}
default : {mcSHOW_ERR_MSG(("ERROR: Unexpected DQSIEN_MODE :%d \n",dfs_tr->DQSIEN_MODE)); while(1);};
}
mcSHOW_DBG_MSG2(("=================================== \n"));
mcSHOW_DBG_MSG2(("LPDDR5 DRAM CONFIGURATION\n" ));
mcSHOW_DBG_MSG2(("=================================== \n"));
mcSHOW_DBG_MSG2(("MR_WL = 0x%1x\n",tr->MR_WL ));
mcSHOW_DBG_MSG2(("MR_RL = 0x%1x\n",tr->MR_RL ));
mcSHOW_DBG_MSG2(("BL = 0x%1x\n",tr->BL ));
mcSHOW_DBG_MSG2(("CK_Mode = 0x%1x\n",tr->CK_Mode ));
mcSHOW_DBG_MSG2(("RPST = 0x%1x\n",tr->RPST ));
mcSHOW_DBG_MSG2(("RD_PRE = 0x%1x\n",tr->RD_PRE ));
mcSHOW_DBG_MSG2(("RDQS_PRE = 0x%1x\n",tr->RDQS_PRE ));
mcSHOW_DBG_MSG2(("WR_PRE = 0x%1x\n",tr->WR_PRE ));
mcSHOW_DBG_MSG2(("WR_PST = 0x%1x\n",tr->WR_PST ));
mcSHOW_DBG_MSG2(("DBI_WR = 0x%1x\n",tr->DBI_WR ));
mcSHOW_DBG_MSG2(("DBI_RD = 0x%1x\n",tr->DBI_RD ));
mcSHOW_DBG_MSG2(("DMI = 0x%1x\n",tr->DMI ));
mcSHOW_DBG_MSG2(("OTF = 0x%1x\n",tr->OTF ));
mcSHOW_DBG_MSG2(("WCK_PST = 0x%1x\n",tr->WCK_PST ));
mcSHOW_DBG_MSG2(("RDQS_PST = 0x%1x\n",tr->RDQS_PST ));
mcSHOW_DBG_MSG2(("CA_ODT = 0x%1x\n",tr->CA_ODT ));
mcSHOW_DBG_MSG2(("DQ_ODT = 0x%1x\n",tr->DQ_ODT ));
mcSHOW_DBG_MSG2(("CKR = 0x%1x\n",tr->CKR ));
mcSHOW_DBG_MSG2(("WCK_ON = 0x%1x\n",tr->WCK_ON ));
mcSHOW_DBG_MSG2(("WCK_FM = 0x%1x\n",tr->WCK_FM ));
mcSHOW_DBG_MSG2(("WCK_ODT = 0x%1x\n",tr->WCK_ODT ));
mcSHOW_DBG_MSG2(("DVFSQ = 0x%1x\n",tr->DVFSQ ));
mcSHOW_DBG_MSG2(("DVFSC = 0x%1x\n",tr->DVFSC ));
mcSHOW_DBG_MSG2(("RDQSmode[0] = 0x%1x\n",tr->RDQSmode[0] ));
mcSHOW_DBG_MSG2(("RDQSmode[1] = 0x%1x\n",tr->RDQSmode[1] ));
mcSHOW_DBG_MSG2(("WCKmode[0] = 0x%1x\n",tr->WCKmode[0] ));
mcSHOW_DBG_MSG2(("WCKmode[1] = 0x%1x\n",tr->WCKmode[1] ));
mcSHOW_DBG_MSG2(("RECC = 0x%1x\n",tr->RECC ));
mcSHOW_DBG_MSG2(("WECC = 0x%1x\n",tr->WECC ));
mcSHOW_DBG_MSG2(("BankMode = 0x%1x\n",tr->BankMode ));
mcSHOW_DBG_MSG2(("WORK_FSP = 0x%1x\n",tr->WORK_FSP ));
mcSHOW_DBG_MSG2(("=================================== \n"));
}
#endif

1628
src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c
View File

File diff suppressed because it is too large Load Diff

16
src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c
View File

@ -3387,14 +3387,6 @@ void vPrintFinalModeRegisterSetting(DRAMC_CTX_T * p)
mcSHOW_MRW_MSG(("[MR Dump] CH%d Rank%d Fsp%d MR%d =0x%x\n", p->channel, p->rank, gFSPWR_Flag[p->rank], u1MRIdx, u2MRValue));
#if MRW_BACKUP
//MR13(LP4) work around, two RG is not synchronized
#if (__LP5_COMBO__ == TRUE)
if (is_lp5_family(p))
{
if (u1MRIdx==16)
gFSPWR_Flag[p->rank]=u1Backup_Fsp;
}
else
#endif
{
if (u1MRIdx==13)
gFSPWR_Flag[p->rank]=u1Backup_Fsp;
@ -3402,14 +3394,6 @@ void vPrintFinalModeRegisterSetting(DRAMC_CTX_T * p)
DramcMRWriteBackup(p, u1MRIdx, u1RankIdx);
#if (__LP5_COMBO__ == TRUE)
if (is_lp5_family(p))
{
if (u1MRIdx==16)
gFSPWR_Flag[p->rank]=u1FSPIdx;
}
else
#endif
{
if (u1MRIdx==13)
gFSPWR_Flag[p->rank]=u1FSPIdx;

9194
src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c
View File

File diff suppressed because it is too large Load Diff

160
src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c
View File

@ -146,22 +146,6 @@ const U8 uiLPDDR4_MRR_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16] =
},
};
#if (__LP5_COMBO__)
const U8 uiLPDDR5_MRR_Mapping_POP[CHANNEL_NUM][16] =
{
{
8, 9, 10, 11, 12, 15, 14, 13,
0, 1, 2, 3, 4, 7, 6, 5,
},
#if (CHANNEL_NUM>1)
{
8, 9, 10, 11, 12, 15, 14, 13,
0, 1, 2, 3, 4, 7, 6, 5,
},
#endif
};
#endif
//MRR DRAM->DRAMC
U8 uiLPDDR4_MRR_Mapping_POP[CHANNEL_NUM][16] =
@ -195,10 +179,6 @@ U8 uiLPDDR4_MRR_Mapping_POP[CHANNEL_NUM][16] =
#if (fcFOR_CHIP_ID == fc8195)
static void Set_DRAM_Pinmux_Sel(DRAMC_CTX_T *p)
{
#if (__LP5_COMBO__)
if (is_lp5_family(p))
return;
#endif
#if !FOR_DV_SIMULATION_USED
if (is_discrete_lpddr4())
@ -234,11 +214,6 @@ static void Set_MRR_Pinmux_Mapping(DRAMC_CTX_T *p)
{
vSetPHY2ChannelMapping(p, chIdx);
#if (__LP5_COMBO__)
if (is_lp5_family(p))
uiLPDDR_MRR_Mapping = (U8 *)uiLPDDR5_MRR_Mapping_POP[chIdx];
else
#endif
uiLPDDR_MRR_Mapping = (U8 *)uiLPDDR4_MRR_Mapping_POP[chIdx];
//Set MRR pin mux
@ -276,11 +251,6 @@ static void Set_DQO1_Pinmux_Mapping(DRAMC_CTX_T *p)
{
vSetPHY2ChannelMapping(p, chIdx);
#if (__LP5_COMBO__)
if (is_lp5_family(p))
uiLPDDR_DQO1_Mapping = (U8 *)uiLPDDR5_O1_Mapping_POP[chIdx];
else
#endif
uiLPDDR_DQO1_Mapping = (U8 *)uiLPDDR4_O1_Mapping_POP[chIdx];
//Set MRR pin mux
@ -7174,11 +7144,6 @@ void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p)
U8 u1DisImpHw;
U32 u4TermFreq;
#if (__LP5_COMBO__ == TRUE)
if (TRUE == is_lp5_family(p))
u4TermFreq = LP5_MRFSP_TERM_FREQ;
else
#endif
u4TermFreq = LP4_MRFSP_TERM_FREQ;
u1DisImpHw = (p->frequency >= u4TermFreq)? 0: 1;
@ -7282,40 +7247,12 @@ static void SV_BroadcastOn_DramcInit(DRAMC_CTX_T *p)
sv_algorithm_assistance_LP4_400(p);
}
}
#if __LP5_COMBO__
else
{
if(p->freq_sel==LP5_DDR4266)
{
mcSHOW_DBG_MSG2(("CInit_golden_mini_freq_related_vseq_LP5_4266 \n"));
CInit_golden_mini_freq_related_vseq_LP5_4266(p);
}
else if(p->freq_sel==LP5_DDR5500)
{
mcSHOW_DBG_MSG2(("CInit_golden_mini_freq_related_vseq_LP5_5500 \n"));
CInit_golden_mini_freq_related_vseq_LP5_5500(p);
}
else
{
mcSHOW_DBG_MSG2(("CInit_golden_mini_freq_related_vseq_LP5_3200 \n"));
CInit_golden_mini_freq_related_vseq_LP5_3200(p);
CInit_golden_mini_freq_related_vseq_LP5_3200_SHU1(p);
}
}
#endif
RESETB_PULL_DN(p);
ANA_init(p);
DIG_STATIC_SETTING(p);
DIG_CONFIG_SHUF(p,0,0); //temp ch0 group 0
#if __LP5_COMBO__
if(is_lp5_family(p))
{
LP5_UpdateInitialSettings(p);
}
else
#endif
{
LP4_UpdateInitialSettings(p);
}
@ -7355,9 +7292,7 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p)
EnableDramcPhyDCM(p, DCM_OFF); //Let CLK always free-run
vResetDelayChainBeforeCalibration(p);
#if __LP5_COMBO__
if(!is_lp5_family(p))
#endif
DVFSSettings(p);
#if REPLACE_DFS_RG_MODE
@ -7389,13 +7324,6 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p)
mcSHOW_TIME_MSG(("\tDutyCalibration takes %d us\n", CPU_Cycle));
#endif
#if __LP5_COMBO__
if(is_lp5_family(p))
{
LP5_DRAM_INIT(p); // Notice: LP5_DRAM_INIT is Broadcast On
}
else
#endif
{
//LP4_DRAM_INIT(p);
DramcModeRegInit_LP4(p);
@ -7872,16 +7800,7 @@ void DramcHMR4_Presetting(DRAMC_CTX_T *p)
static void SwitchHMR4(DRAMC_CTX_T *p, bool en)
{
#ifdef __LP5_COMBO__
if (is_lp5_family(p))
{
vIO32WriteFldAlign_All(DRAMC_REG_REF_BOUNCE2, 9, REF_BOUNCE2_PRE_MR4INT_TH);
vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL2, 9, REFCTRL2_MR4INT_TH);
}
else
#endif
{
vIO32WriteFldAlign_All(DRAMC_REG_REF_BOUNCE2, 5, REF_BOUNCE2_PRE_MR4INT_TH);
@ -8935,20 +8854,10 @@ static void RODTSettings(DRAMC_CTX_T *p)
if(p->odt_onoff==ODT_ON)
{
#if __LP5_COMBO__
if (p->dram_type==TYPE_LPDDR5)
u1VrefSel = 0x46;//term LP5
else
#endif
u1VrefSel = 0x2c;//term LP4
}
else
{
#if __LP5_COMBO__
if (p->dram_type==TYPE_LPDDR5)
u1VrefSel = 0x37;//unterm LP5
else
#endif
u1VrefSel = 0x37;//unterm LP4
}
@ -9034,21 +8943,6 @@ static void DQSSTBSettings(DRAMC_CTX_T *p)
unsigned int dqsien_mode = 1;
BOOL isLP4_DSC = (p->DRAMPinmux == PINMUX_DSC)?1:0;
#if (__LP5_COMBO__)
U8 rpre_mode = LPDDR5_RPRE_4S_0T;
if (is_lp5_family(p))
{
if (p->frequency > 1600)
rpre_mode = LPDDR5_RPRE_2S_2T;
}
if (rpre_mode == LPDDR5_RPRE_2S_2T)
dqsien_mode = 2;
else if (rpre_mode == LPDDR5_RPRE_XS_4T)
dqsien_mode = 3;
#endif
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL),
dqsien_mode, MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ10),
@ -9217,58 +9111,6 @@ void LP4_UpdateInitialSettings(DRAMC_CTX_T *p)
SetMck8xLowPwrOption(p);
}
#if __LP5_COMBO__
void LP5_UpdateInitialSettings(DRAMC_CTX_T *p)
{
U8 u1RankIdx, u1RankIdxBak;
vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD14, 0x0, SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA); //Let CA and CS be independent
//Set_MRR_Pinmux_Mapping(p); //Update MRR pinmux
//Disable perbyte option
vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ7, P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0)
| P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0)
| P_Fld(0x0, SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0));
vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ7, P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1)
| P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1)
| P_Fld(0x0, SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1));
///TODO: Temp solution. May need to resolve in init flow
vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL5, /* Will cause PI un-adjustable */
P_Fld(0x0, MISC_CG_CTRL5_R_CA_DLY_DCM_EN) |
P_Fld(0x0, MISC_CG_CTRL5_R_CA_PI_DCM_EN) |
P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN) |
P_Fld(0x0, MISC_CG_CTRL5_R_DQ0_PI_DCM_EN) |
P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN) |
P_Fld(0x0, MISC_CG_CTRL5_R_DQ1_PI_DCM_EN));
DQSSTBSettings(p);
RODTSettings(p);
#if SIMULATION_SW_IMPED
#if FSP1_CLKCA_TERM
U8 u1CASwImpFreqRegion = (p->dram_fsp == FSP_0)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
#else
U8 u1CASwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
#endif
U8 u1DQSwImpFreqRegion = (p->frequency <= 1866)? IMP_LOW_FREQ: IMP_HIGH_FREQ;
if (p->dram_type == TYPE_LPDDR5)
DramcSwImpedanceSaveRegister(p, u1CASwImpFreqRegion, u1DQSwImpFreqRegion, DRAM_DFS_REG_SHU0);
#endif
#if RDSEL_TRACKING_EN
vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RDSEL_TRACK, 0, SHU_MISC_RDSEL_TRACK_DMDATLAT_I); //DMDATLAT_I should be set as 0 before set datlat k value, otherwise the status flag wil be set as 1
#endif
#if (!XRTRTR_NEW_CROSS_RK_MODE)
vIO32WriteFldAlign(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, 0x0, SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN);
#endif
SetMck8xLowPwrOption(p);
}
#endif
#define CKGEN_FMETER 0x0
#define ABIST_FMETER 0x1
/*

1807
src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c
View File

File diff suppressed because it is too large Load Diff

21
src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
View File

@ -2337,27 +2337,6 @@ void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_args
#endif // (SIMULATION_RX_RDDQC == 1)
#if (__LP5_COMBO__ == TRUE)
#if (SIMULATION_DUTY_CYC_MONITOR == 1)
if (is_lp5_family(DramConfig) && DramConfig->frequency >= GetFreqBySel(DramConfig,LP5_DDR4266))
{
if (!psra) {
mcSHOW_DBG_MSG6(("\n----->DramcDutyCycleMonitor begin...\n"));
timestamp_show();
DramcDutyCycleMonitor(DramConfig);
timestamp_show();
mcSHOW_DBG_MSG6(("DramcDutyCycleMonitor end<-----\n\n"));
mcSHOW_DBG_MSG6(("\n----->DramcWriteLeveling(DLY) begin...\n"));
timestamp_show();
DramcWriteLeveling(DramConfig, psra->wl_autok, DLY_BASED);
timestamp_show();
mcSHOW_DBG_MSG6(("DramcWriteLeveling(DLY)end<-----\n\n"));
}
}
#endif /* (SIMULATION_DUTY_CYC_MONITOR == 1) */
#endif // (__LP5_COMBO__ == TRUE)
#if (SIMULATION_TX_PERBIT == 1)
if (!psra || psra->tx_perbit) {
mcSHOW_DBG_MSG6(("\n----->DramcTxWindowPerbitCal begin...\n"));

245
src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c
View File

@ -47,35 +47,6 @@ u8 is_heff_mode(DRAMC_CTX_T *p)
return res? TRUE: FALSE;
}
#if __LP5_COMBO__
static u8 lp5heff;
u8 lp5heff_save_disable(DRAMC_CTX_T *p)
{
/* save it */
lp5heff = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0),
SHU_COMMON0_LP5HEFF_MODE);
/* disable it */
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0),
P_Fld(0, SHU_COMMON0_LP5HEFF_MODE));
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RKCFG),
0, RKCFG_CKE2RANK);
return lp5heff;
}
void lp5heff_restore(DRAMC_CTX_T *p)
{
/* restore it */
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0),
P_Fld(lp5heff, SHU_COMMON0_LP5HEFF_MODE));
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RKCFG),
lp5heff, RKCFG_CKE2RANK);
}
#endif
#if FOR_DV_SIMULATION_USED
U8 u1BroadcastOnOff = 0;
#endif
@ -290,11 +261,6 @@ void vSetRankNumber(DRAMC_CTX_T *p)
void vSetFSPNumber(DRAMC_CTX_T *p)
{
#if (__LP5_COMBO__ == TRUE)
if (TRUE == is_lp5_family(p))
p->support_fsp_num = 3;
else
#endif
p->support_fsp_num = 2;
}
@ -304,60 +270,7 @@ static void setFreqGroup(DRAMC_CTX_T *p)
/* Below listed conditions represent freqs that exist in ACTimingTable
* -> Should cover freqGroup settings for all real freq values
*/
#if (__LP5_COMBO__ == TRUE)
if (TRUE == is_lp5_family(p))
{
if (p->frequency <= 400) // DDR800
{
p->freqGroup = 400;
}
else if (p->frequency <= 600) // DDR1200
{
p->freqGroup = 600;
}
else if (p->frequency <= 800) // DDR1600
{
p->freqGroup = 800;
}
else if (p->frequency <= 933) //DDR1866
{
p->freqGroup = 933;
}
else if (p->frequency <= 1200) //DDR2400, DDR2280
{
p->freqGroup = 1200;
}
else if (p->frequency <= 1600) // DDR3200
{
p->freqGroup = 1600;
}
else if (p->frequency <= 1866) // DDR3733
{
p->freqGroup = 1866;
}
else if (p->frequency <= 2133) // DDR4266
{
p->freqGroup = 2133;
}
else if (p->frequency <= 2400) // DDR4800
{
p->freqGroup = 2400;
}
else if (p->frequency <= 2750) // DDR5500
{
p->freqGroup = 2750;
}
else if (p->frequency <= 3000) // DDR6000
{
p->freqGroup = 3000;
}
else // DDR6600
{
p->freqGroup = 3300;
}
}
else
#endif
{
if (p->frequency <= 200) // DDR400
{
@ -719,20 +632,7 @@ void DDRPhyFreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel)
{
p->freq_sel = sel;
p->frequency = GetFreqBySel(p, sel);
#if __LP5_COMBO__
if(is_lp5_family(p))
{
///TODO: Dennis
//p->dram_fsp = (p->frequency < LP5_MRFSP_TERM_FREQ)? FSP_0: FSP_1;
p->dram_fsp = FSP_0;
#if LP5_DDR4266_RDBI_WORKAROUND
if(p->frequency >= 2133)
p->DBI_R_onoff[FSP_0] = DBI_ON;
#endif
p->odt_onoff = (p->frequency < LP5_MRFSP_TERM_FREQ)? ODT_OFF: ODT_ON;
}
else
#endif
{
p->dram_fsp = (p->frequency < LP4_MRFSP_TERM_FREQ)? FSP_0: FSP_1;
p->odt_onoff = (p->frequency < LP4_MRFSP_TERM_FREQ)? ODT_OFF: ODT_ON;
@ -1370,15 +1270,6 @@ DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1Te
P_Fld(test2_1 >> 24, TEST2_A0_TEST2_PAT0) |
P_Fld(test2_2 >> 24, TEST2_A0_TEST2_PAT1));
#if (__LP5_COMBO__ == TRUE)
if (TRUE == is_lp5_family(p))
{
// LP5 TA2 base: 0x0
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1),
test2_1 & 0x00ffffff, RK_TEST2_A1_TEST2_BASE);
}
else
#endif
{
// LP4 TA2 base: 0x10000. It's only TBA constrain, but not HW.
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RK_TEST2_A1),
@ -1984,32 +1875,6 @@ U8 DramcMRWriteBackup(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Rank)
u1Fsp = FSP_0;
#if (__LP5_COMBO__ == TRUE)
if (is_lp5_family(p))
{
switch (u1MRIdx)
{
case 1:
case 2:
case 3:
case 10:
case 11:
case 12:
case 14:
case 15:
case 17:
case 18:
case 19:
case 20:
case 24:
case 30:
case 41:
u1Fsp = gFSPWR_Flag[u1Rank];
break;
}
}
else
#endif
{
switch (u1MRIdx)
{
@ -2392,17 +2257,6 @@ void DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T *p, U8 *u1Rank, U8 *u1MRIdx, U8 *
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
1, SWCMD_EN_RTMRWEN);
#if __LP5_COMBO__
#if WORKAROUND_LP5_HEFF
if (is_heff_mode(p))
{
mcDELAY_US(1);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
1, CKECTRL_CKE2RANK_OPT6);
}
#endif
#endif
u4TimeCnt = TIME_OUT_CNT;
do {
@ -2417,81 +2271,10 @@ void DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T *p, U8 *u1Rank, U8 *u1MRIdx, U8 *
mcSHOW_ERR_MSG(("[LP5 RT MRW ] Resp fail (time out) Rank=%d, MR%d=0x%x\n", u1Rank[0], u1MRIdx[0], u1Value[0]));
}
#if __LP5_COMBO__
#if WORKAROUND_LP5_HEFF
if (is_heff_mode(p))
{
mcDELAY_US(1);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
0, CKECTRL_CKE2RANK_OPT6);
}
#endif
#endif
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
0, SWCMD_EN_RTMRWEN);
}
#if 0
static void DramcModeRegWriteByRank_RTSWCMD_MRW(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
{
U32 u4Response, u4TimeCnt;
vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL2),
P_Fld(0, SWCMD_CTRL2_RTSWCMD_AGE) |
P_Fld(u1Rank, SWCMD_CTRL2_RTSWCMD_RK) |
P_Fld(u1MRIdx, SWCMD_CTRL2_RTSWCMD_MA) |
P_Fld(u1Value, SWCMD_CTRL2_RTSWCMD_OP));
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL),
1, MPC_CTRL_RTSWCMD_HPRI_EN);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_RTSWCMD_CNT),
0x2a, RTSWCMD_CNT_RTSWCMD_CNT);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
4, SWCMD_EN_RTSWCMD_SEL);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
1, SWCMD_EN_RTSWCMDEN);
#if __LP5_COMBO__
#if WORKAROUND_LP5_HEFF
if (is_heff_mode(p))
{
mcDELAY_US(1);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
1, CKECTRL_CKE2RANK_OPT6);
}
#endif
#endif
u4TimeCnt = TIME_OUT_CNT;
do {
u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP3),
SPCMDRESP3_RTSWCMD_RESPONSE);
u4TimeCnt--;
mcDELAY_US(5);
} while ((u4Response == 0) && (u4TimeCnt > 0));
if (u4TimeCnt == 0)//time out
{
mcSHOW_ERR_MSG(("[LP5 RT SW Cmd MRW ] Resp fail (time out) Rank=%d, MR%d=0x%x\n", u1Rank, u1MRIdx, u1Value));
}
#if __LP5_COMBO__
#if WORKAROUND_LP5_HEFF
if (is_heff_mode(p))
{
mcDELAY_US(1);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL),
0, CKECTRL_CKE2RANK_OPT6);
}
#endif
#endif
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN),
0, SWCMD_EN_RTSWCMDEN);
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL),
0, MPC_CTRL_RTSWCMD_HPRI_EN);
}
#endif
static void DramcModeRegWriteByRank_SCSM(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
{
U32 counter = 0;
@ -2548,17 +2331,6 @@ void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
else
#endif
{
#if (__LP5_COMBO__ == TRUE)
if (is_lp5_family(p))
{
#if ENABLE_RUNTIME_MRW_FOR_LP5
DramcModeRegWriteByRank_RTMRW(p, &u1Rank, &u1MRIdx, &u1Value, 1);
#else
DramcModeRegWriteByRank_RTSWCMD_MRW(p, u1Rank, u1MRIdx, u1Value);
#endif
}
else
#endif
{
DramcModeRegWriteByRank_SCSM(p, u1Rank, u1MRIdx, u1Value);
}
@ -2583,11 +2355,6 @@ void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
u1RankStart = u1Rank;
}
#if (__LP5_COMBO__ == TRUE)
if (is_lp5_family(p))
u1FSPMRIdx=16;
else
#endif
u1FSPMRIdx=13;
for (u1RankIdx=u1RankStart;u1RankIdx<u1RankStart+u1RankNum;u1RankIdx++)
@ -2620,14 +2387,6 @@ void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
mcSHOW_MRW_MSG((" [MRW Check] Rank%d FSP%d Backup_MR%d= 0x%x MR%d= 0x%x ==>%s\n", u1RankIdx, gFSPWR_Flag[u1RankIdx], u1MRIdx, MR_backup, u1MRIdx, u1Value, (u1Value==MR_backup?"PASS":"FAIL")));
#endif
#if (__LP5_COMBO__ == TRUE)
if (is_lp5_family(p))
{
if (u1MRIdx==u1FSPMRIdx)
gFSPWR_Flag[u1RankIdx] = u1Value & 0x3;
}
else
#endif
{
if (u1MRIdx==u1FSPMRIdx)
gFSPWR_Flag[u1RankIdx] = (u1Value>> 6) & 0x1;

42
src/vendorcode/mediatek/mt8195/include/dramc_actiming.h
View File

@ -122,49 +122,7 @@ typedef enum
AC_TIMING_NUMBER_LP4
} AC_TIMING_LP4_COUNT_TYPE_T;
#if (__LP5_COMBO__)
/* Used to keep track the total number of LP5 ACTimings */
typedef enum
{
#if SUPPORT_LP5_DDR6400_ACTIM
#if ENABLE_READ_DBI
AC_TIME_LP5_BYTE_DDR6400_RDBI_ON = 0,
AC_TIME_LP5_NORM_DDR6400_RDBI_ON,
#else //(ENABLE_READ_DBI == 0)
AC_TIME_LP5_BYTE_DDR6400_RDBI_OFF,
AC_TIME_LP5_NORM_DDR6400_RDBI_OFF,
#endif //ENABLE_READ_DBI
#endif
#if SUPPORT_LP5_DDR5500_ACTIM
#if ((ENABLE_READ_DBI) || (LP5_DDR4266_RDBI_WORKAROUND))
AC_TIME_LP5_BYTE_DDR5500_RDBI_ON,
AC_TIME_LP5_NORM_DDR5500_RDBI_ON,
#else
AC_TIME_LP5_BYTE_DDR5500_RDBI_OFF,
AC_TIME_LP5_NORM_DDR5500_RDBI_OFF,
#endif
#endif
#if SUPPORT_LP5_DDR4266_ACTIM
#if ((ENABLE_READ_DBI) || (LP5_DDR4266_RDBI_WORKAROUND))
AC_TIME_LP5_BYTE_DDR4266_RDBI_ON,
AC_TIME_LP5_NORM_DDR4266_RDBI_ON,
#else //(ENABLE_READ_DBI == 0)
AC_TIME_LP5_BYTE_DDR4266_RDBI_OFF,
AC_TIME_LP5_NORM_DDR4266_RDBI_OFF,
#endif //ENABLE_READ_DBI
#endif
#if SUPPORT_LP5_DDR3200_ACTIM
AC_TIME_LP5_BYTE_DDR3200_RDBI_OFF,
AC_TIME_LP5_NORM_DDR3200_RDBI_OFF,
#endif
AC_TIMING_NUMBER_LP5
} AC_TIMING_LP5_COUNT_TYPE_T;
#else
#define AC_TIMING_NUMBER_LP5 0
#endif
/* ACTiming struct declaration (declared here due Fld_wid for each register type)
* Should include all fields from ACTiming excel file (And update the correct values in UpdateACTimingReg()

3
src/vendorcode/mediatek/mt8195/include/dramc_dv_init.h
View File

@ -323,9 +323,6 @@ extern void get_top_configuration_from_DV_random(DV_new_config_T * tr);
extern void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr);
extern void DPI_SW_main_LP4(DRAMC_CTX_T *p, cal_sv_rand_args_t *psra);
extern void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr);
#if __LP5_COMBO__
extern void LP5_DRAM_config(DRAMC_DVFS_GROUP_CONFIG_T *dfs_tr, LP5_DRAM_CONFIG_T *tr);
#endif
extern void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate);
extern void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs);
extern void ANA_sequence_shuffle_colletion(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr);