From 98b7d0457467bf83fffc3fa7acdf80bc1efbf21d Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Fri, 31 May 2024 18:35:37 -0600 Subject: [PATCH] soc/common/smbus: Support reading SPD5 hubs for DDR5 DDR5 uses a Serial Presence Detect (SPD) with hub function (SPD5 hub device) to store the SPD data. The SPD5 hub has 1024 bytes of EEPROM (`CONFIG_DIMM_SPD_SIZE=1024`). Tested on Clevo V560TU (system76/darp10) with 2x Crucial CT16G48C40S5 DIMMs. Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe Co-authored-by: Meera Ravindranath Signed-off-by: Jeremy Soller Signed-off-by: Tim Crawford --- src/include/spd_bin.h | 12 +++ src/lib/spd_cache.c | 4 +- src/soc/intel/common/block/smbus/smbuslib.c | 93 ++++++++++++++++++--- 3 files changed, 95 insertions(+), 14 deletions(-) diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index c51e449559..9514bcbd87 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -36,6 +36,18 @@ #define DDR4_SPD_PART_OFF 329 #define DDR4_SPD_PART_LEN 20 #define DDR4_SPD_SN_OFF 325 +#define MAX_SPD_PAGE_SIZE_SPD5 128 +#define MAX_SPD_SIZE (SPD_PAGE_LEN * 4) +#define SPD_HUB_MEMREG(addr) ((u8)(0x80 | (addr))) +#define SPD5_MR11 0x0B +#define SPD5_MR0 0x00 +#define SPD5_MEMREG_REG(addr) ((u8)((~0x80) & (addr))) +#define SPD5_MR0_SPD5_HUB_DEV 0x51 + +struct spd_offset_table { + u16 start; /* Offset 0 */ + u16 end; /* Offset 2 */ +}; struct spd_block { u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */ diff --git a/src/lib/spd_cache.c b/src/lib/spd_cache.c index dff6ede860..adb5ade06e 100644 --- a/src/lib/spd_cache.c +++ b/src/lib/spd_cache.c @@ -209,7 +209,9 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk) dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_DRAM_TYPE); - if (dram_type == SPD_DRAM_DDR4) + if (dram_type == SPD_DRAM_DDR5) + blk->len = CONFIG_DIMM_SPD_SIZE; + else if (dram_type == SPD_DRAM_DDR4) blk->len = SPD_PAGE_LEN_DDR4; else blk->len = SPD_PAGE_LEN; diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index aff6fb0a1b..2584137480 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -13,8 +13,11 @@ static void update_spd_len(struct spd_block *blk) if (blk->spd_array[i] != NULL) j |= blk->spd_array[i][SPD_DRAM_TYPE]; + /* If spd used is DDR5, then its length is 1024 byte. */ + if (j == SPD_DRAM_DDR5) + blk->len = CONFIG_DIMM_SPD_SIZE; /* If spd used is DDR4, then its length is 512 byte. */ - if (j == SPD_DRAM_DDR4) + else if (j == SPD_DRAM_DDR4) blk->len = SPD_PAGE_LEN_DDR4; else blk->len = SPD_PAGE_LEN; @@ -37,6 +40,61 @@ static void smbus_read_spd(u8 *spd, u8 addr) } } +static void switch_page(u8 spd_addr, u8 new_page) +{ + u32 offset; + /* + * By default,an SPD5 hub accepts 1 byte addressing pointing + * to the first 128 bytes of memory. MR11[2:0] selects the page + * pointer to address the entire 1024 bytes of non-volatile memory. + */ + offset = SPD5_MEMREG_REG(SPD5_MR11); + smbus_write_byte(spd_addr, offset, new_page); +} + +/* + * Read the SPD data over the SMBus, at the specified SPD address, + * starting at the specified starting offset and read the given amount of data. + */ +static void smbus_read_spd5(u8 *spd, u8 spd_addr, u16 size) +{ + u8 page = ~0; + u32 max_page_size = MAX_SPD_PAGE_SIZE_SPD5; + + if (size > MAX_SPD_SIZE) { + printk(BIOS_ERR, "Maximum SPD size reached\n"); + return; + } + for (int i = 0; i < size; i++) { + u8 next_page = (u8) (i / max_page_size); + if (next_page != page) { + switch_page(spd_addr, next_page); + page = next_page; + } + unsigned int byte_addr = SPD_HUB_MEMREG(i % max_page_size); + spd[i] = smbus_read_byte(spd_addr, byte_addr); + } +} + +/* Read SPD5 MR0 and check if SPD Byte 0 matches the SPD5 HUB MR0 identifier.*/ +static int is_spd5_hub(u8 spd_addr) +{ + u8 spd_hub_byte; + + spd_hub_byte = smbus_read_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR0)); + return spd_hub_byte == SPD5_MR0_SPD5_HUB_DEV; +} + +/* + * Reset the SPD page back to page 0 on an SPD5 Hub device at the + * input SPD SMbus address. + */ +static void reset_page_spd5(u8 spd_addr) +{ + /* Set SPD5 MR11[2:0] = 0 (Page 0) */ + smbus_write_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR11), 0); +} + /* return -1 if SMBus errors otherwise return 0 */ static int get_spd(u8 *spd, u8 addr) { @@ -52,22 +110,31 @@ static int get_spd(u8 *spd, u8 addr) return -1; } - if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) { - printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); - smbus_read_spd(spd, addr); - } + if (is_spd5_hub(addr)) { + smbus_read_spd5(spd, addr, CONFIG_DIMM_SPD_SIZE); - /* Check if module is DDR4, DDR4 spd is 512 byte. */ - if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { - /* Switch to page 1 */ - smbus_write_byte(SPD_PAGE_1, 0, 0); + /* Reset the page for the next loop iteration */ + reset_page_spd5(addr); + } else { - if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) { + if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) { printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); - smbus_read_spd(spd + SPD_PAGE_LEN, addr); + smbus_read_spd(spd, addr); + } + + /* Check if module is DDR4, DDR4 spd is 512 byte. */ + if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && + CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { + /* Switch to page 1 */ + smbus_write_byte(SPD_PAGE_1, 0, 0); + + if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) { + printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); + smbus_read_spd(spd + SPD_PAGE_LEN, addr); + } + /* Restore to page 0 */ + smbus_write_byte(SPD_PAGE_0, 0, 0); } - /* Restore to page 0 */ - smbus_write_byte(SPD_PAGE_0, 0, 0); } return 0; }