cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm

C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.

This removes the need for a magic lapic in the devicetree.

Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/include/cpu/intel/speedstep.h

@@ -3,11 +3,9 @@
 #ifndef CPU_INTEL_SPEEDSTEP_H
 #define CPU_INTEL_SPEEDSTEP_H
 
+#include <stdbool.h>
 #include <stdint.h>
 
-/* Magic value used to locate speedstep configuration in the device tree */
-#define SPEEDSTEP_APIC_MAGIC 0xACAC
-
 /* MWAIT coordination I/O base address. This must match
  * the \_PR_.CP00 PM base address.
  */
@@ -92,4 +90,8 @@ void speedstep_gen_pstates(sst_table_t *);
 #define SPEEDSTEP_MIN_POWER_PENRYN	15000
 #define SPEEDSTEP_SLFM_POWER_PENRYN	12000
 
+bool southbridge_support_c5(void);
+bool southbridge_support_c6(void);
+bool northbridge_support_slfm(void);
+
 #endif /* CPU_INTEL_SPEEDSTEP_H */