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cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm

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C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.

This removes the need for a magic lapic in the devicetree.

Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans
2022-11-07 11:39:58 +01:00
committed by Felix Held
parent 6f573217a0
commit 98c92570d9
33 changed files with 81 additions and 124 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/southbridge/intel/i82801gx/lpc.c
View File

@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/intel/speedstep.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -473,3 +474,13 @@ static const struct pci_driver ich7_lpc __pci_driver = {
.vendor = PCI_VID_INTEL,
.devices = pci_device_ids,
};
bool southbridge_support_c5(void)
{
return false;
}
bool southbridge_support_c6(void)
{
return false;
}

21
src/southbridge/intel/i82801ix/lpc.c
View File

@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/intel/speedstep.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -137,6 +138,20 @@ static void i82801ix_gpi_routing(struct device *dev)
pci_write_config32(dev, D31F0_GPIO_ROUT, reg32);
}
bool southbridge_support_c5(void)
{
struct device *lpc_dev = __pci_0_1f_0;
struct southbridge_intel_i82801ix_config *config = lpc_dev->chip_info;
return config->c5_enable == 1;
}
bool southbridge_support_c6(void)
{
struct device *lpc_dev = __pci_0_1f_0;
struct southbridge_intel_i82801ix_config *config = lpc_dev->chip_info;
return config->c6_enable == 1;
}
static void i82801ix_power_options(struct device *dev)
{
u8 reg8;
@@ -216,15 +231,15 @@ static void i82801ix_power_options(struct device *dev)
reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
if (CONFIG(DEBUG_PERIODIC_SMI))
reg16 |= (3 << 0); // Periodic SMI every 8s
if (config->c5_enable)
if (southbridge_support_c5())
reg16 |= (1 << 11); /* Enable C5, C6 and PMSYNC# */
pci_write_config16(dev, D31F0_GEN_PMCON_1, reg16);
/* Set exit timings for C5/C6. */
if (config->c5_enable) {
if (southbridge_support_c5()) {
reg8 = pci_read_config8(dev, D31F0_C5_EXIT_TIMING);
reg8 &= ~((7 << 3) | (7 << 0));
if (config->c6_enable)
if (southbridge_support_c6())
reg8 |= (5 << 3) | (3 << 0); /* 38-44us PMSYNC# to STPCLK#,
95-102us DPRSTP# to STP_CPU# */
else

21
src/southbridge/intel/i82801jx/lpc.c
View File

@@ -13,6 +13,7 @@
#include <arch/ioapic.h>
#include <acpi/acpi.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/speedstep.h>
#include <acpi/acpigen.h>
#include <arch/smp/mpspec.h>
#include "chip.h"
@@ -139,6 +140,20 @@ static void i82801jx_gpi_routing(struct device *dev)
pci_write_config32(dev, D31F0_GPIO_ROUT, reg32);
}
bool southbridge_support_c5(void)
{
struct device *lpc_dev = __pci_0_1f_0;
struct southbridge_intel_i82801jx_config *config = lpc_dev->chip_info;
return config->c5_enable == 1;
}
bool southbridge_support_c6(void)
{
struct device *lpc_dev = __pci_0_1f_0;
struct southbridge_intel_i82801jx_config *config = lpc_dev->chip_info;
return config->c6_enable == 1;
}
static void i82801jx_power_options(struct device *dev)
{
u8 reg8;
@@ -218,15 +233,15 @@ static void i82801jx_power_options(struct device *dev)
reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
if (CONFIG(DEBUG_PERIODIC_SMI))
reg16 |= (3 << 0); // Periodic SMI every 8s
if (config->c5_enable)
if (southbridge_support_c5())
reg16 |= (1 << 11); /* Enable C5, C6 and PMSYNC# */
pci_write_config16(dev, D31F0_GEN_PMCON_1, reg16);
/* Set exit timings for C5/C6. */
if (config->c5_enable) {
if (southbridge_support_c5()) {
reg8 = pci_read_config8(dev, D31F0_C5_EXIT_TIMING);
reg8 &= ~((7 << 3) | (7 << 0));
if (config->c6_enable)
if (southbridge_support_c6())
reg8 |= (5 << 3) | (3 << 0); /* 38-44us PMSYNC# to STPCLK#,
95-102us DPRSTP# to STP_CPU# */
else