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This patch fix a AMD sb800 wrapper compile warning:

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src/southbridge/amd/cimx_wrapper/sb800/late
 call clear_ioapic but not include the prototype declare header file.

Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Kerry She
2011-06-01 01:56:49 +00:00
committed by Kerry She
parent b2ecd81514
commit 991f880893
5 changed files with 16 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/vendorcode/amd/cimx/sb800/EC.c
View File

@ -71,7 +71,7 @@ ecPowerOnInit (
RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF)); //set LSB of Mailbox port
RWEC8 (0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1
if ( pConfig->BuildParameters.EcKbd == ENABLED) {
if ( pConfig->BuildParameters.EcKbd == CIMX_OPTION_ENABLED) {
//Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3);
@ -83,7 +83,7 @@ ecPowerOnInit (
RWEC8 (0x30, 0x00, 0x01);
}
if ( pConfig->BuildParameters.EcChannel0 == ENABLED) {
if ( pConfig->BuildParameters.EcChannel0 == CIMX_OPTION_ENABLED) {
//Logical device 0x03
RWEC8 (0x07, 0x00, 0x03);
RWEC8 (0x60, 0x00, 0x00);

4
src/vendorcode/amd/cimx/sb800/SATA.c
View File

@ -470,7 +470,7 @@ sataInitAfterPciEnum (
if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) {
// RIAD or AHCI
if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) {
if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) {
RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
// RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
@ -631,7 +631,7 @@ sataInitLatePost (
//Enable write access to pci header, pm capabilities
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) {
// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) {
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7);
// }
sataBar5setting (pConfig, &ddBar5);

8
src/vendorcode/amd/cimx/sb800/SBTYPE.h
View File

@ -1093,13 +1093,13 @@ typedef unsigned int CIM_STATUS;
#pragma pack (pop)
/**
* DISABLED - Define disable in module
* CIMX_OPTION_DISABLED - Define disable in module
*/
#define DISABLED 0
#define CIMX_OPTION_DISABLED 0
/**
* ENABLED - Define enable in module
* CIMX_OPTION_ENABLED - Define enable in module
*/
#define ENABLED 1
#define CIMX_OPTION_ENABLED 1
// mov al, code
// out 80h, al