- Update the device header files
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -68,13 +68,13 @@
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#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
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#define PCI_BASE_ADDRESS_SPACE_IO 0x01
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#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
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#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
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#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
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#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
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#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
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#define PCI_BASE_ADDRESS_MEM_LIMIT_MASK 0x06
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#define PCI_BASE_ADDRESS_MEM_LIMIT_32 0x00 /* 32 bit address */
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#define PCI_BASE_ADDRESS_MEM_LIMIT_1M 0x02 /* Below 1M [obsolete] */
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#define PCI_BASE_ADDRESS_MEM_LIMIT_64 0x04 /* 64 bit address */
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#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
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#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
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#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
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#define PCI_BASE_ADDRESS_MEM_ATTR_MASK 0x0f
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#define PCI_BASE_ADDRESS_IO_ATTR_MASK 0x03
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/* bit 1 is reserved if address_space = 1 */
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/* Header type 0 (normal devices) */
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