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Fix the indent and whitespace to match LinuxBIOS standards

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Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Jordan Crouse
2007-05-10 18:32:28 +00:00
committed by Stefan Reinauer
parent f8030bd924
commit 9934b813da
5 changed files with 388 additions and 449 deletions
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23
src/cpu/amd/model_lx/cpubug.c
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@ -30,7 +30,6 @@
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
/************************************************************************** /**************************************************************************
* *
* pcideadlock * pcideadlock
@ -40,27 +39,27 @@
* There is also fix code in cache and PCI functions. This bug is very is pervasive. * There is also fix code in cache and PCI functions. This bug is very is pervasive.
* *
**************************************************************************/ **************************************************************************/
static void pcideadlock(void){ static void pcideadlock(void)
{
msr_t msr; msr_t msr;
/* /*
* forces serialization of all load misses. Setting this bit prevents the * forces serialization of all load misses. Setting this bit prevents the
* DM pipe from backing up if a read request has to be held up waiting * DM pipe from backing up if a read request has to be held up waiting
* for PCI writes to complete. * for PCI writes to complete.
*/ */
msr = rdmsr(CPU_DM_CONFIG0); msr = rdmsr(CPU_DM_CONFIG0);
msr.lo |= DM_CONFIG0_LOWER_MISSER_SET; msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
wrmsr(CPU_DM_CONFIG0, msr); wrmsr(CPU_DM_CONFIG0, msr);
/* write serialize memory hole to PCI. Need to unWS when something is /* write serialize memory hole to PCI. Need to unWS when something is
* shadowed regardless of cachablility. * shadowed regardless of cachablility.
*/ */
msr.lo = 0x021212121; msr.lo = 0x021212121;
msr.hi = 0x021212121; msr.hi = 0x021212121;
wrmsr( CPU_RCONF_A0_BF, msr); wrmsr(CPU_RCONF_A0_BF, msr);
wrmsr( CPU_RCONF_C0_DF, msr); wrmsr(CPU_RCONF_C0_DF, msr);
wrmsr( CPU_RCONF_E0_FF, msr); wrmsr(CPU_RCONF_E0_FF, msr);
} }
/****************************************************************************/ /****************************************************************************/
@ -74,17 +73,19 @@ static void pcideadlock(void){
/** to maintain coherency with and the cache is not enabled yet.*/ /** to maintain coherency with and the cache is not enabled yet.*/
/***/ /***/
/****************************************************************************/ /****************************************************************************/
static void disablememoryreadorder(void){ static void disablememoryreadorder(void)
{
msr_t msr; msr_t msr;
msr = rdmsr(MC_CF8F_DATA); msr = rdmsr(MC_CF8F_DATA);
msr.hi |= CF8F_UPPER_REORDER_DIS_SET; msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
wrmsr(MC_CF8F_DATA, msr); wrmsr(MC_CF8F_DATA, msr);
} }
/* For cpu version C3. Should be the only released version */ /* For cpu version C3. Should be the only released version */
void cpubug(void) { void cpubug(void)
pcideadlock(); {
pcideadlock();
disablememoryreadorder(); disablememoryreadorder();
printk_debug("Done cpubug fixes \n"); printk_debug("Done cpubug fixes \n");
} }

163
src/cpu/amd/model_lx/cpureginit.c
View File

@ -25,7 +25,8 @@
;* SetDelayControl ;* SetDelayControl
;* ;*
;*************************************************************************/ ;*************************************************************************/
void SetDelayControl(void){ void SetDelayControl(void)
{
unsigned int msrnum, glspeed; unsigned int msrnum, glspeed;
unsigned char spdbyte0, spdbyte1; unsigned char spdbyte0, spdbyte1;
msr_t msr; msr_t msr;
@ -37,7 +38,7 @@ void SetDelayControl(void){
msr.hi = 0; msr.hi = 0;
msr.lo = 0x2814D352; msr.lo = 0x2814D352;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
msrnum = CPU_BC_MSS_ARRAY_CTL1; msrnum = CPU_BC_MSS_ARRAY_CTL1;
msr.hi = 0; msr.hi = 0;
msr.lo = 0x1068334D; msr.lo = 0x1068334D;
@ -46,8 +47,8 @@ void SetDelayControl(void){
msrnum = CPU_BC_MSS_ARRAY_CTL2; msrnum = CPU_BC_MSS_ARRAY_CTL2;
msr.hi = 0x00000106; msr.hi = 0x00000106;
msr.lo = 0x83104104; msr.lo = 0x83104104;
wrmsr(msrnum,msr); wrmsr(msrnum, msr);
msrnum = GLCP_FIFOCTL; msrnum = GLCP_FIFOCTL;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.hi = 0x00000005; msr.hi = 0x00000005;
@ -59,38 +60,34 @@ void SetDelayControl(void){
msr.lo = 0x00000001; msr.lo = 0x00000001;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* Debug Delay Control Setup Check /* Debug Delay Control Setup Check
Leave it alone if it has been setup. FS2 or something is here.*/ Leave it alone if it has been setup. FS2 or something is here. */
msrnum = GLCP_DELAY_CONTROLS; msrnum = GLCP_DELAY_CONTROLS;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
if (msr.lo & ~(0x7C0)){ if (msr.lo & ~(0x7C0)) {
return; return;
} }
/* /*
; Delay Controls based on DIMM loading. UGH! * Delay Controls based on DIMM loading. UGH!
; # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5) * # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5)
; Note - We only support module width of 64. * Note - We only support module width of 64.
*/ */
spdbyte0 = spd_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH); spdbyte0 = spd_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH);
if (spdbyte0 !=0xFF){ if (spdbyte0 != 0xFF) {
spdbyte0 = (unsigned char) 64/spdbyte0 * (unsigned char) (spd_read_byte(DIMM0, SPD_NUM_DIMM_BANKS)); spdbyte0 = (unsigned char)64 / spdbyte0 *
} (unsigned char)(spd_read_byte(DIMM0, SPD_NUM_DIMM_BANKS));
else{ } else {
spdbyte0=0; spdbyte0 = 0;
} }
spdbyte1 = spd_read_byte(DIMM1, SPD_PRIMARY_SDRAM_WIDTH); spdbyte1 = spd_read_byte(DIMM1, SPD_PRIMARY_SDRAM_WIDTH);
if (spdbyte1 !=0xFF){ if (spdbyte1 != 0xFF) {
spdbyte1 = (unsigned char) 64/spdbyte1 * (unsigned char) (spd_read_byte(DIMM1, SPD_NUM_DIMM_BANKS)); spdbyte1 = (unsigned char)64 / spdbyte1 *
(unsigned char)(spd_read_byte(DIMM1, SPD_NUM_DIMM_BANKS));
} else {
spdbyte1 = 0;
} }
else{
spdbyte1=0;
}
/* The current thinking. Subject to change... /* The current thinking. Subject to change...
@ -141,117 +138,104 @@ void SetDelayControl(void){
*/ */
msr.hi = msr.lo = 0; msr.hi = msr.lo = 0;
if (spdbyte0 == 0 || spdbyte1 == 0){ if (spdbyte0 == 0 || spdbyte1 == 0) {
/* one dimm solution */ /* one dimm solution */
if (spdbyte1 == 0){ if (spdbyte1 == 0) {
msr.hi |= 0x000800000; msr.hi |= 0x000800000;
} }
spdbyte0 += spdbyte1; spdbyte0 += spdbyte1;
if (spdbyte0 > 8){ if (spdbyte0 > 8) {
/* large dimm */ /* large dimm */
if (glspeed < 334){ if (glspeed < 334) {
msr.hi |= 0x0837100AA; msr.hi |= 0x0837100AA;
msr.lo |= 0x056960004; msr.lo |= 0x056960004;
} } else {
else{
msr.hi |= 0x082710055; msr.hi |= 0x082710055;
msr.lo |= 0x056960004; msr.lo |= 0x056960004;
} }
} } else if (spdbyte0 > 4) {
else if (spdbyte0 > 4){
/* medium dimm */ /* medium dimm */
if (glspeed < 334){ if (glspeed < 334) {
msr.hi |= 0x0837100AA; msr.hi |= 0x0837100AA;
msr.lo |= 0x056960004; msr.lo |= 0x056960004;
} } else {
else{
msr.hi |= 0x0827100AA; msr.hi |= 0x0827100AA;
msr.lo |= 0x056960004; msr.lo |= 0x056960004;
} }
} } else {
else{
/* small dimm */ /* small dimm */
if (glspeed < 334){ if (glspeed < 334) {
msr.hi |= 0x0837100FF; msr.hi |= 0x0837100FF;
msr.lo |= 0x056960004; msr.lo |= 0x056960004;
} } else {
else{
msr.hi |= 0x0827100FF; msr.hi |= 0x0827100FF;
msr.lo |= 0x056960004; msr.lo |= 0x056960004;
} }
} }
} } else {
else{
/* two dimm solution */ /* two dimm solution */
spdbyte0 += spdbyte1; spdbyte0 += spdbyte1;
if (spdbyte0 > 24){ if (spdbyte0 > 24) {
/* huge dimms */ /* huge dimms */
if (glspeed < 334){ if (glspeed < 334) {
msr.hi |= 0x0B37100A5; msr.hi |= 0x0B37100A5;
msr.lo |= 0x056960004; msr.lo |= 0x056960004;
} } else {
else{
msr.hi |= 0x0B2710000; msr.hi |= 0x0B2710000;
msr.lo |= 0x056960004; msr.lo |= 0x056960004;
} }
} } else if (spdbyte0 > 16) {
else if (spdbyte0 > 16){
/* large dimms */ /* large dimms */
if (glspeed < 334){ if (glspeed < 334) {
msr.hi |= 0x0B37100A5; msr.hi |= 0x0B37100A5;
msr.lo |= 0x056960004; msr.lo |= 0x056960004;
} } else {
else{
msr.hi |= 0x0B27100A5; msr.hi |= 0x0B27100A5;
msr.lo |= 0x056960004; msr.lo |= 0x056960004;
} }
} } else if (spdbyte0 >= 8) {
else if (spdbyte0 >= 8){
/* medium dimms */ /* medium dimms */
if (glspeed < 334){ if (glspeed < 334) {
msr.hi |= 0x0937100A5; msr.hi |= 0x0937100A5;
msr.lo |= 0x056960004; msr.lo |= 0x056960004;
} } else {
else{
msr.hi |= 0x0C27100A5; msr.hi |= 0x0C27100A5;
msr.lo |= 0x056960004; msr.lo |= 0x056960004;
} }
} } else {
else{
/* small dimms */ /* small dimms */
if (glspeed < 334){ if (glspeed < 334) {
msr.hi |= 0x0837100A5; msr.hi |= 0x0837100A5;
msr.lo |= 0x056960004; msr.lo |= 0x056960004;
} } else {
else{
msr.hi |= 0x082710000; msr.hi |= 0x082710000;
msr.lo |= 0x056960004; msr.lo |= 0x056960004;
} }
} }
} }
wrmsr(GLCP_DELAY_CONTROLS,msr); wrmsr(GLCP_DELAY_CONTROLS, msr);
return; return;
} }
/* ***************************************************************************/ /* ***************************************************************************/
/* * cpuRegInit*/ /* * cpuRegInit*/
/* ***************************************************************************/ /* ***************************************************************************/
void void cpuRegInit(void)
cpuRegInit (void){ {
int msrnum; int msrnum;
msr_t msr; msr_t msr;
/* Castle 2.0 BTM periodic sync period. */ /* Castle 2.0 BTM periodic sync period. */
/* [40:37] 1 sync record per 256 bytes */ /* [40:37] 1 sync record per 256 bytes */
msrnum = CPU_PF_CONF; msrnum = CPU_PF_CONF;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.hi |= (0x8 << 5); msr.hi |= (0x8 << 5);
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* /*
; Castle performance setting. ; Castle performance setting.
; Enable Quack for fewer re-RAS on the MC ; Enable Quack for fewer re-RAS on the MC
*/ */
msrnum = GLIU0_ARB; msrnum = GLIU0_ARB;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.hi &= ~ARB_UPPER_DACK_EN_SET; msr.hi &= ~ARB_UPPER_DACK_EN_SET;
@ -264,7 +248,7 @@ cpuRegInit (void){
msr.hi |= ARB_UPPER_QUACK_EN_SET; msr.hi |= ARB_UPPER_QUACK_EN_SET;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* GLIU port active enable, limit south pole masters (AES and PCI) to one outstanding transaction. */ /* GLIU port active enable, limit south pole masters (AES and PCI) to one outstanding transaction. */
msrnum = GLIU1_PORT_ACTIVE; msrnum = GLIU1_PORT_ACTIVE;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.lo &= ~0x880; msr.lo &= ~0x880;
@ -273,46 +257,45 @@ cpuRegInit (void){
/* Set the Delay Control in GLCP */ /* Set the Delay Control in GLCP */
SetDelayControl(); SetDelayControl();
/* Enable RSDC*/ /* Enable RSDC */
msrnum = CPU_AC_SMM_CTL; msrnum = CPU_AC_SMM_CTL;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.lo |= SMM_INST_EN_SET; msr.lo |= SMM_INST_EN_SET;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* FPU imprecise exceptions bit */ /* FPU imprecise exceptions bit */
msrnum = CPU_FPU_MSR_MODE; msrnum = CPU_FPU_MSR_MODE;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.lo |= FPU_IE_SET; msr.lo |= FPU_IE_SET;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* Power Savers (Do after BIST) */ /* Power Savers (Do after BIST) */
/* Enable Suspend on HLT & PAUSE instructions*/ /* Enable Suspend on HLT & PAUSE instructions */
msrnum = CPU_XC_CONFIG; msrnum = CPU_XC_CONFIG;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE; msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */ /* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
msrnum = CPU_BC_CONF_0; msrnum = CPU_BC_CONF_0;
msr = rdmsr(msrnum); msr = rdmsr(msrnum);
msr.lo |= TSC_SUSP_SET | SUSP_EN_SET; msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
msr.lo &= 0x0F0FFFFFF; msr.lo &= 0x0F0FFFFFF;
msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2 */ msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2 */
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
/* Disable the debug clock to save power.*/ /* Disable the debug clock to save power. */
/* NOTE: leave it enabled for fs2 debug */ /* NOTE: leave it enabled for fs2 debug */
/* msrnum = GLCP_DBGCLKCTL; #if 0
msrnum = GLCP_DBGCLKCTL;
msr.hi = 0; msr.hi = 0;
msr.lo = 0; msr.lo = 0;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
*/ #endif
/* Setup throttling delays to proper mode if it is ever enabled. */ /* Setup throttling delays to proper mode if it is ever enabled. */
msrnum = GLCP_TH_OD; msrnum = GLCP_TH_OD;
msr.hi = 0; msr.hi = 0;
msr.lo = 0x00000603C; msr.lo = 0x00000603C;
wrmsr(msrnum, msr); wrmsr(msrnum, msr);
} }

21
src/cpu/amd/model_lx/model_lx_init.c
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@ -33,12 +33,9 @@
static void vsm_end_post_smi(void) static void vsm_end_post_smi(void)
{ {
__asm__ volatile ( __asm__ volatile ("push %ax\n"
"push %ax\n"
"mov $0x5000, %ax\n" "mov $0x5000, %ax\n"
".byte 0x0f, 0x38\n" ".byte 0x0f, 0x38\n" "pop %ax\n");
"pop %ax\n"
);
} }
static void model_lx_init(device_t dev) static void model_lx_init(device_t dev)
@ -55,23 +52,23 @@ static void model_lx_init(device_t dev)
vsm_end_post_smi(); vsm_end_post_smi();
// Set gate A20 (legacy vsm disables it in late init) // Set gate A20 (legacy vsm disables it in late init)
printk_debug("A20 (0x92): %d\n",inb(0x92)); printk_debug("A20 (0x92): %d\n", inb(0x92));
outb(0x02,0x92); outb(0x02, 0x92);
printk_debug("A20 (0x92): %d\n",inb(0x92)); printk_debug("A20 (0x92): %d\n", inb(0x92));
printk_debug("CPU model_lx_init DONE\n"); printk_debug("CPU model_lx_init DONE\n");
}; };
static struct device_operations cpu_dev_ops = { static struct device_operations cpu_dev_ops = {
.init = model_lx_init, .init = model_lx_init,
}; };
static struct cpu_device_id cpu_table[] = { static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x05A2 }, {X86_VENDOR_AMD, 0x05A2},
{ 0, 0 }, {0, 0},
}; };
static struct cpu_driver driver __cpu_driver = { static struct cpu_driver driver __cpu_driver = {
.ops = &cpu_dev_ops, .ops = &cpu_dev_ops,
.id_table = cpu_table, .id_table = cpu_table,
}; };

8
src/cpu/amd/model_lx/syspreinit.c
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@ -29,14 +29,14 @@
/* * Destroys: Al,*/ /* * Destroys: Al,*/
/* **/ /* **/
/* ***************************************************************************/ /* ***************************************************************************/
void void StartTimer1(void)
StartTimer1(void){ {
outb(0x56, 0x43); outb(0x56, 0x43);
outb(0x12, 0x41); outb(0x12, 0x41);
} }
void void SystemPreInit(void)
SystemPreInit(void){ {
/* they want a jump ... */ /* they want a jump ... */
#ifndef USE_DCACHE_RAM #ifndef USE_DCACHE_RAM

622
src/cpu/amd/model_lx/vsmsetup.c
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