arch/x86: Move TSEG_STAGE_CACHE implementation
This is declared weak so that platforms that do not have smm_subregion() can provide their own implementation. Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@@ -29,7 +29,6 @@ romstage-y += fsp_util.c
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romstage-y += hob.c
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romstage-y += raminit.c
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romstage-y += romstage.c
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romstage-y += stage_cache.c
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romstage-$(CONFIG_MMA) += mma_core.c
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ramstage-$(CONFIG_RUN_FSP_GOP) += fsp_gop.c
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@@ -37,13 +36,11 @@ ramstage-y += fsp_relocate.c
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ramstage-y += fsp_util.c
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ramstage-y += hob.c
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ramstage-y += ramstage.c
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ramstage-y += stage_cache.c
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ramstage-$(CONFIG_INTEL_GMA_ADD_VBT) += vbt.c
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ramstage-$(CONFIG_MMA) += mma_core.c
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CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
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postcar-y += stage_cache.c
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ifneq ($(CONFIG_SKIP_FSP_CAR),y)
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postcar-y += temp_ram_exit.c
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postcar-y += exit_car.S
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@@ -1,28 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <stage_cache.h>
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void stage_cache_external_region(void **base, size_t *size)
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{
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if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
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printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
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*base = NULL;
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*size = 0;
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}
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}
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