arch/x86: Move TSEG_STAGE_CACHE implementation

This is declared weak so that platforms that do not
have smm_subregion() can provide their own implementation.

Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/amd/picasso/ramtop.c

@@ -23,7 +23,6 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cbmem.h>
-#include <stage_cache.h>
 #include <arch/bert_storage.h>
 #include <soc/northbridge.h>
 #include <soc/iomap.h>
@@ -82,15 +81,6 @@ static size_t smm_region_size(void)
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void stage_cache_external_region(void **base, size_t *size)
-{
-	if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
-		printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
-		*base = NULL;
-		*size = 0;
-	}
-}
-
 void smm_region(void **start, size_t *size)
 {
 	*start = (void *)smm_region_start();