arch/x86: Move TSEG_STAGE_CACHE implementation

This is declared weak so that platforms that do not
have smm_subregion() can provide their own implementation.

Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/cpu/x86/smm/Makefile.inc

@@ -42,6 +42,10 @@ endif
 
 ifeq ($(CONFIG_SMM_TSEG),y)
 
+ramstage-y += stage_cache.c
+romstage-y += stage_cache.c
+postcar-y += stage_cache.c
+
 smmstub-y += smm_stub.S
 
 smm-y += smm_module_handler.c

src/cpu/x86/smm/stage_cache.c

@@ -1,8 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2013 Google Inc.
+ * Copyright 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,8 +16,14 @@
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <stage_cache.h>
+#include <types.h>
 
-void stage_cache_external_region(void **base, size_t *size)
+int __weak smm_subregion(int sub, void **base, size_t *size)
+{
+	return -1;
+}
+
+void __weak stage_cache_external_region(void **base, size_t *size)
 {
 	if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
 		printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");

src/drivers/intel/fsp1_1/Makefile.inc

@@ -29,7 +29,6 @@ romstage-y += fsp_util.c
 romstage-y += hob.c
 romstage-y += raminit.c
 romstage-y += romstage.c
-romstage-y += stage_cache.c
 romstage-$(CONFIG_MMA) += mma_core.c
 
 ramstage-$(CONFIG_RUN_FSP_GOP) += fsp_gop.c
@@ -37,13 +36,11 @@ ramstage-y += fsp_relocate.c
 ramstage-y += fsp_util.c
 ramstage-y += hob.c
 ramstage-y += ramstage.c
-ramstage-y += stage_cache.c
 ramstage-$(CONFIG_INTEL_GMA_ADD_VBT) += vbt.c
 ramstage-$(CONFIG_MMA) += mma_core.c
 
 CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
 
-postcar-y += stage_cache.c
 ifneq ($(CONFIG_SKIP_FSP_CAR),y)
 postcar-y += temp_ram_exit.c
 postcar-y += exit_car.S

src/soc/amd/picasso/ramtop.c

@@ -23,7 +23,6 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cbmem.h>
-#include <stage_cache.h>
 #include <arch/bert_storage.h>
 #include <soc/northbridge.h>
 #include <soc/iomap.h>
@@ -82,15 +81,6 @@ static size_t smm_region_size(void)
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void stage_cache_external_region(void **base, size_t *size)
-{
-	if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
-		printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
-		*base = NULL;
-		*size = 0;
-	}
-}
-
 void smm_region(void **start, size_t *size)
 {
 	*start = (void *)smm_region_start();

src/soc/amd/stoneyridge/ramtop.c

@@ -23,7 +23,6 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cbmem.h>
-#include <stage_cache.h>
 #include <arch/bert_storage.h>
 #include <soc/northbridge.h>
 #include <soc/iomap.h>
@@ -82,15 +81,6 @@ static size_t smm_region_size(void)
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void stage_cache_external_region(void **base, size_t *size)
-{
-	if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
-		printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
-		*base = NULL;
-		*size = 0;
-	}
-}
-
 void smm_region(void **start, size_t *size)
 {
 	*start = (void *)smm_region_start();

src/soc/intel/common/block/smm/smm.c

@@ -22,18 +22,6 @@
 #include <intelblocks/smm.h>
 #include <intelblocks/systemagent.h>
 #include <soc/pm.h>
-#include <stage_cache.h>
-
-#if !CONFIG(PLATFORM_USES_FSP1_1)
-void stage_cache_external_region(void **base, size_t *size)
-{
-	if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
-		printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
-		*base = NULL;
-		*size = 0;
-	}
-}
-#endif
 
 void smm_southbridge_clear_state(void)
 {