diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl
index 98938339bf..04df1fee44 100644
--- a/src/soc/intel/tigerlake/acpi/tcss.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss.asl
@@ -354,12 +354,6 @@ Scope (\_SB.PCI0)
 		Offset(0x10),
 		RBAR, 64        /* RegBar, offset 0x7110 in MCHBAR */
 	}
-	Field (MBAR, DWordAcc, NoLock, Preserve)
-	{
-		Offset(0x304),  /* PRIMDN_MASK1_0_0_0_MCHBAR_IMPH, offset 0x7404 */
-		,     31,
-		TCD3, 1         /* [31:31] TCSS IN D3 bit */
-	}
 
 	/*
 	 * Operation region defined to access the pCode mailbox interface. Get the MCHBAR
@@ -689,11 +683,6 @@ Scope (\_SB.PCI0)
 			}
 			Else
 			{
-				/*
-				 * Program IOP MCTP Drop (TCSS_IN_D3) after D3 cold exit and
-				 * acknowledgement by IOM.
-				 */
-				TCD3 = 0
 				/*
 				 * If the TCSS Deven is cleared by BIOS Mailbox request, then
 				 * restore to previously saved value of TCSS DEVNE.
@@ -741,11 +730,6 @@ Scope (\_SB.PCI0)
 			}
 		}
 
-		/*
-		 * Program IOM MCTP Drop (TCSS_IN_D3) in D3Cold entry before entering D3 cold.
-		 */
-		TCD3 = 1
-
 		/* Request IOM for D3 cold entry sequence. */
 		TD3C = 1
 	}
diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
index 085990dbfd..d00f79432d 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
@@ -32,12 +32,20 @@ Method (_S0W, 0x0)
 
 Method (_PR0)
 {
-	Return (Package() { \_SB.PCI0.D3C })
+	If (DUID == 0) {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
+	} Else {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
+	}
 }
 
 Method (_PR3)
 {
-	Return (Package() { \_SB.PCI0.D3C })
+	If (DUID == 0) {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
+	} Else {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
+	}
 }
 
 /*
@@ -64,24 +72,6 @@ Method (D3CE, 0, Serialized)
  */
 Name (SD3C, 0)
 
-Method (_PS0, 0, Serialized)
-{
-	If (DUID == 0) {
-		\_SB.PCI0.TBT0._ON()
-	} Else {
-		\_SB.PCI0.TBT1._ON()
-	}
-}
-
-Method (_PS3, 0, Serialized)
-{
-	If (DUID == 0) {
-		\_SB.PCI0.TBT0._OFF()
-	} Else {
-		\_SB.PCI0.TBT1._OFF()
-	}
-}
-
 Method (_DSW, 3)
 {
 	/* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */
diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
index 08d890087c..9e1b324bfe 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
@@ -227,12 +227,20 @@ Method (_S0W, 0x0, NotSerialized)
 
 Method (_PR0)
 {
-	Return (Package() { \_SB.PCI0.D3C })
+	If ((TUID == 0) || (TUID == 1)) {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
+	} Else {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
+	}
 }
 
 Method (_PR3)
 {
-	Return (Package() { \_SB.PCI0.D3C })
+	If ((TUID == 0) || (TUID == 1)) {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
+	} Else {
+		Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
+	}
 }
 
 /*