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Introduce stage-specific architecture for coreboot

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Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.

These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.

In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.

Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.

We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.

Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
This commit is contained in:
Furquan Shaikh
2014-04-23 10:18:48 -07:00
parent fb494d68ff
commit 99ac98f7e1
77 changed files with 494 additions and 305 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
src/Kconfig
View File

@@ -237,27 +237,8 @@ config ARCH_ARMV7
bool
default n
# Warning: The file is included whether or not the if is here.
# but the if controls how the evaluation occurs.
if ARCH_X86
source src/arch/x86/Kconfig
endif
if ARCH_ARMV7
source src/arch/armv7/Kconfig
endif
config HAVE_ARCH_MEMSET
bool
default n
config HAVE_ARCH_MEMCPY
bool
default n
config HAVE_ARCH_MEMMOVE
bool
default n
source src/vendorcode/Kconfig
@@ -1123,3 +1104,9 @@ config REG_SCRIPT
default n
help
Internal option that controls whether we compile in register scripts.
# Maximum reboot count
# TODO: Improve description.
config MAX_REBOOT_CNT
int
default 3

21
src/arch/armv7/Kconfig
View File

@@ -1,18 +1,17 @@
menu "Architecture (armv7)"
config ARM_ARCH_OPTIONS
config ARCH_BOOTBLOCK_ARMV7
bool
default y
select HAVE_ARCH_MEMSET
select HAVE_ARCH_MEMCPY
select HAVE_ARCH_MEMMOVE
default n
select ARCH_ARMV7
# Maximum reboot count
# TODO: Improve description.
config MAX_REBOOT_CNT
int
default 3
config ARCH_ROMSTAGE_ARMV7
bool
default n
config ARCH_RAMSTAGE_ARMV7
bool
default n
choice
prompt "Bootblock behaviour"

57
src/arch/armv7/Makefile.inc
View File

@@ -30,28 +30,27 @@ subdirs-y += lib/
# ARM specific options
###############################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7),y)
CBFSTOOL_PRE1_OPTS = -m armv7 -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) -o $(CONFIG_CBFS_ROM_OFFSET)
CBFSTOOL_PRE_OPTS = -b 0
endif
ifeq ($(CONFIG_ARCH_ARMV7),y)
stages_c = $(src)/arch/armv7/stages.c
stages_o = $(obj)/arch/armv7/stages.o
$(stages_o): $(stages_c) $(obj)/config.h
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) -I. $(INCLUDES) -c -o $@ $< -marm
$(CC_armv7) -I. $(INCLUDES) $(INCLUDES_armv7) -c -o $@ $< -marm
CFLAGS += \
-ffixed-r8\
-march=armv7-a\
-marm\
-mno-unaligned-access\
-mthumb\
-mthumb-interwork
endif # CONFIG_ARCH_ARMV7
###############################################################################
# bootblock
###############################################################################
ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV7),y)
bootblock-y += cache.c
bootblock-y += eabi_compat.c
bootblock-y += memset.S
@@ -79,31 +78,35 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) $(bootblock-S-ccopts) -Wa,-acdlns -c -o $@ $< > $(basename $@).disasm
$(CC_bootblock) $(bootblock-S-ccopts) -Wa,-acdlns -c -o $@ $< > $(basename $@).disasm
$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) $(bootblock-S-ccopts) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
$(CC_bootblock) $(bootblock-S-ccopts) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
$(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(bootblock_custom) $(OPTION_TABLE_H) $(obj)/config.h
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) $(bootblock-c-ccopts) $(INCLUDES) -MM \
$(CC_bootblock) $(bootblock-c-ccopts) $(INCLUDES) $(INCLUDES_bootblock) -MM \
-MT$(objgenerated)/bootblock.inc \
$< > $(objgenerated)/bootblock.inc.d
$(CC) $(bootblock-c-ccopts) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@
$(CC_bootblock) $(bootblock-c-ccopts) -c -S $(CFLAGS_bootblock) -I. $(INCLUDES) $(INCLUDES_bootblock) $< -o $@
$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(stages) $(obj)/config.h
@printf " LINK $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -m armelf_linux_eabi -include $(obj)/config.h -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld
$(LD_bootblock) -m armelf_linux_eabi -include $(obj)/config.h -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld
else
$(CC) -nostdlib -nostartfiles -include $(obj)/config.h -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(objgenerated)/bootblock.o $(bootblock-objs) $(stages) $(LIBGCC_FILE_NAME) -Wl,--end-group
$(CC_bootblock) -nostdlib -nostartfiles -include $(obj)/config.h -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(objgenerated)/bootblock.o $(bootblock-objs) $(stages) $(LIBGCC_FILE_NAME_bootblock) -Wl,--end-group
endif
endif # CONFIG_ARCH_BOOTBLOCK_ARMV7
###############################################################################
# romstage
###############################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7),y)
romstage-y += cache.c
romstage-y += div0.c
romstage-y += eabi_compat.c
@@ -127,9 +130,9 @@ crt0s += $(cpu_incs-y)
$(objcbfs)/romstage.debug: $$(romstage-objs) $(stages_o) $(objgenerated)/romstage.ld
@printf " LINK $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage.ld
$(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage.ld
else
$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage.ld -Wl,--start-group $(romstage-objs) $(stages_o) $(LIBGCC_FILE_NAME) -Wl,--end-group
$(CC_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage.ld -Wl,--start-group $(romstage-objs) $(stages_o) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group
endif
$(objgenerated)/romstage.ld: $$(ldscripts) $(obj)/ldoptions
@@ -144,20 +147,24 @@ $(objgenerated)/crt0.romstage.S: $$(crt0s)
$(objgenerated)/crt0.romstage.o: $(objgenerated)/crt0.s
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) -Wa,-acdlns -c -o $@ $< > $(basename $@).disasm
$(CC_romstage) -Wa,-acdlns -c -o $@ $< > $(basename $@).disasm
$(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/build.h
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@
$(CC_romstage) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
@printf " CC romstage.inc\n"
$(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
$(CC_romstage) -MMD $(CFLAGS_romstage) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
endif # CONFIG_ARCH_ROMSTAGE_ARMV7
###############################################################################
# ramstage
###############################################################################
ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV7),y)
ramstage-y += exception.c
ramstage-y += exception_asm.S
ramstage-y += div0.c
@@ -175,17 +182,17 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/armv7/ramstage.ld
@printf " CC $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/armv7/ramstage.ld
$(LD_ramstage) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/armv7/ramstage.ld
else
$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/ramstage.ld $<
$(CC_ramstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/ramstage.ld $<
endif
$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME)
$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage)
@printf " CC $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group
$(LD_ramstage) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) --end-group
else
$(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group
$(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group
endif
ifeq ($(CONFIG_GENERATE_PIRQ_TABLE),y)
@@ -211,3 +218,5 @@ endif
ifeq ($(CONFIG_HAVE_BUS_CONFIG),y)
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c
endif
endif # CONFIG_ARCH_RAMSTAGE_ARMV7

24
src/arch/x86/Kconfig
View File

@@ -1,11 +1,17 @@
menu "Architecture (x86)"
config X86_ARCH_OPTIONS
config ARCH_BOOTBLOCK_X86_32
bool
default y
select HAVE_ARCH_MEMSET
select HAVE_ARCH_MEMCPY
select HAVE_ARCH_MEMMOVE
default n
select ARCH_X86
config ARCH_ROMSTAGE_X86_32
bool
default n
config ARCH_RAMSTAGE_X86_32
bool
default n
# This is an SMP option. It relates to starting up APs.
# It is usually set in mainboard/*/Kconfig.
@@ -34,12 +40,6 @@ config STACK_SIZE
hex
default 0x1000
# Maximum reboot count
# TODO: Improve description.
config MAX_REBOOT_CNT
int
default 3
# This is something you almost certainly don't want to mess with.
# How many SIPIs do we send when starting up APs and cores?
# The answer in 2000 or so was '2'. Nowadays, on many systems,
@@ -84,7 +84,7 @@ config ROMCC
config PC80_SYSTEM
bool
default y
default y if ARCH_X86
config BOOTBLOCK_MAINBOARD_INIT
string

84
src/arch/x86/Makefile.inc
View File

@@ -51,8 +51,10 @@ cbfs-files-$(CONFIG_INTEL_MBI) += mbi.bin
mbi.bin-file := $(call strip_quotes,$(CONFIG_MBI_FILE))
mbi.bin-type := mbi
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
CBFSTOOL_PRE1_OPTS = -m x86 -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) ))
CBFSTOOL_PRE_OPTS = -b $(shell cat $(objcbfs)/base_xip.txt)
endif
################################################################################
# i386 specific tools
@@ -71,6 +73,8 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l
# bootblock
###############################################################################
ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb
bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds
bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds
@@ -110,31 +114,36 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) $(DISASSEMBLY) -c -o $@ $< > $(basename $@).disasm
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC_bootblock) $(DISASSEMBLY) -c -o $@ $< > $(basename $@).disasm
$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
$(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
$(objgenerated)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H)
@printf " ROMCC $(subst $(obj)/,,$(@))\n"
$(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \
$(CC_bootblock) $(INCLUDES) $(INCLUDES_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
$< > $(objgenerated)/bootblock.inc.d
$(ROMCC) -c -S $(bootblock_romccflags) -I. $(INCLUDES) $< -o $@
$(ROMCC) -c -S $(bootblock_romccflags) -I. $(INCLUDES) $(INCLUDES_bootblock) $< -o $@
$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld
@printf " LINK $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -m elf_i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
$(LD_bootblock) -m elf_i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld
else
$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $<
$(CC_bootblock) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $<
endif
endif # CONFIG_ARCH_BOOTBLOCK_X86_32
###############################################################################
# romstage
###############################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
crt0s = $(src)/arch/x86/init/prologue.inc
ldscripts =
ldscripts += $(src)/arch/x86/init/romstage.ld
@@ -166,14 +175,25 @@ else
ROMCCFLAGS := -mcpu=i386 -O2 # !MMX, !SSE
endif
$(objcbfs)/romstage_%.bin: $(objcbfs)/romstage_%.elf
@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
$(OBJCOPY_romstage) -O binary $< $@
$(objcbfs)/romstage_%.elf: $(objcbfs)/romstage_%.debug
@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
cp $< $@.tmp
$(OBJCOPY_romstage) --strip-debug $@.tmp
$(OBJCOPY_romstage) --add-gnu-debuglink=$< $@.tmp
mv $@.tmp $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
printf " ROMCC romstage.inc\n"
$(ROMCC) -c -S $(ROMCCFLAGS) -D__PRE_RAM__ -I. $(INCLUDES) $< -o $@
$(ROMCC) -c -S $(ROMCCFLAGS) -D__PRE_RAM__ -I. $(INCLUDES) $(INCLUDES_romstage) $< -o $@
else
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
@printf " CC romstage.inc\n"
$(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
$(CC_romstage) -MMD $(CFLAGS_romstage) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
@printf " POST romstage.inc\n"
@@ -189,21 +209,21 @@ romstage-libs ?=
$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_null.ld
$(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_null.ld
else
$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group
$(CC_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group
endif
$(NM) $@ | grep -q " [DdBb] "; if [ $$? -eq 0 ]; then \
$(NM_romstage) $@ | grep -q " [DdBb] "; if [ $$? -eq 0 ]; then \
echo "Forbidden global variables in romstage:"; \
$(NM) $@ | grep " [DdBb] "; test "$(CONFIG_CPU_AMD_AGESA)" = y; \
$(NM_romstage) $@ | grep " [DdBb] "; test "$(CONFIG_CPU_AMD_AGESA)" = y; \
else true; fi
$(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld $$(romstage-libs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_xip.ld
$(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_xip.ld
else
$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group
$(CC_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group
endif
$(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions
@@ -232,16 +252,20 @@ $(objgenerated)/crt0.romstage.S: $$(crt0s)
$(objgenerated)/crt0.romstage.o: $(objgenerated)/crt0.s
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) $(DISASSEMBLY) -c -o $@ $< > $(basename $@).disasm
$(CC_romstage) $(DISASSEMBLY) -c -o $@ $< > $(basename $@).disasm
$(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/build.h
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@
$(CC_romstage) $(INCLUDES) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@
endif # CONFIG_ARCH_ROMSTAGE_X86_32
###############################################################################
# ramstage
###############################################################################
ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
ifeq ($(CONFIG_GENERATE_MP_TABLE),y)
ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/mptable.c),)
@@ -284,6 +308,7 @@ endif
ramstage-libs ?=
$(eval $(call create_class_compiler,rmodules,x86_32))
ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE)))
@@ -297,30 +322,31 @@ else
$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/x86/ramstage.ld
@printf " CC $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld
$(LD_ramstage) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld
else
$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/ramstage.ld $<
$(CC_ramstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/ramstage.ld $<
endif
endif
$(objgenerated)/ramstage.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) $$(ramstage-libs)
$(objgenerated)/ramstage.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) $$(ramstage-libs)
@printf " CC $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) --end-group
$(LD_ramstage) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME_ramstage) --end-group
else
$(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group
$(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group
endif
endif # CONFIG_ARCH_RAMSTAGE_X86_32
################################################################################
seabios:
$(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \
HOSTCC="$(HOSTCC)" \
CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \
OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \
AS="$(AS)" CPP="$(CPP)" \
CC="$(CC_x86_32)" LD="$(LD_x86_32)" OBJDUMP="$(OBJDUMP_x86_32)" \
OBJCOPY="$(OBJCOPY_x86_32)" STRIP="$(STRIP_x86_32)" \
AS="$(AS_x86_32)" CPP="$(CPP)" \
CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \
CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \
CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \
@@ -329,8 +355,8 @@ seabios:
filo:
$(MAKE) -C payloads/external/FILO -f Makefile.inc \
HOSTCC="$(HOSTCC)" \
CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \
OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \
CC="$(CC_x86_32)" LD="$(LD_x86_32)" OBJDUMP="$(OBJDUMP_x86_32)" \
OBJCOPY="$(OBJCOPY_x86_32)" STRIP="$(STRIP_x86_32)" \
CONFIG_FILO_MASTER=$(CONFIG_FILO_MASTER) \
CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE)
@@ -338,6 +364,6 @@ filo:
grub2:
$(MAKE) -C payloads/external/GRUB2 -f Makefile.inc \
HOSTCC="$(HOSTCC)" \
CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \
OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \
CC="$(CC_x86_32)" LD="$(LD_x86_32)" OBJDUMP="$(OBJDUMP_x86_32)" \
OBJCOPY="$(OBJCOPY_x86_32)" STRIP="$(STRIP_x86_32)" \
CONFIG_GRUB2_MASTER=$(CONFIG_GRUB2_MASTER)

8
src/arch/x86/boot/Makefile.inc
View File

@@ -1,6 +1,13 @@
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c
romstage-$(CONFIG_BROKEN_CAR_MIGRATE) += cbmem.c
endif # CONFIG_ARCH_ROMSTAGE_X86_32
ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
ramstage-y += boot.c
ramstage-y += gdt.c
ramstage-y += tables.c
@@ -14,3 +21,4 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S
$(obj)/arch/x86/boot/smbios.ramstage.o: $(obj)/build.h
endif # CONFIG_ARCH_RAMSTAGE_X86_32

21
src/arch/x86/lib/Makefile.inc
View File

@@ -1,3 +1,16 @@
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
romstage-y += cbfs_and_run.c
romstage-y += memset.c
romstage-y += memcpy.c
romstage-y += memmove.c
romstage-y += rom_media.c
endif # CONFIG_ARCH_ROMSTAGE_X86_32
ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
ramstage-y += c_start.S
ramstage-y += cpu.c
ramstage-y += pci_ops_conf1.c
@@ -12,12 +25,6 @@ ramstage-y += rom_media.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S
romstage-y += cbfs_and_run.c
romstage-y += memset.c
romstage-y += memcpy.c
romstage-y += memmove.c
romstage-y += rom_media.c
smm-y += memset.c
smm-y += memcpy.c
smm-y += memmove.c
@@ -26,3 +33,5 @@ smm-y += rom_media.c
rmodules-y += memset.c
rmodules-y += memcpy.c
rmodules-y += memmove.c
endif # CONFIG_ARCH_RAMSTAGE_X86_32

5
src/cpu/Makefile.inc
View File

@@ -12,6 +12,7 @@ subdirs-y += via
subdirs-y += x86
subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86
$(eval $(call create_class_compiler,cpu_microcode,x86_32))
################################################################################
## Rules for building the microcode blob in CBFS
################################################################################
@@ -42,13 +43,13 @@ endif
# final microcode file.
$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
@printf " LD $(subst $(obj)/,,$(@))\n"
$(LD) -static --entry=0 $+ -o $@
$(LD_cpu_microcode) -static --entry=0 $+ -o $@
# We have a lot of useless data in the large blob, and we are only interested in
# the data section, so we only copy that part to the final microcode file
$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
@printf " MICROCODE $(subst $(obj)/,,$(@))\n"
$(OBJCOPY) -j .data -O binary $< $@
$(OBJCOPY_cpu_microcode) -j .data -O binary $< $@
ifeq ($(cbfs_include_ucode),y)
# Add CPU microcode to specified rom image $(1)

4
src/cpu/allwinner/a10/Kconfig
View File

@@ -6,7 +6,9 @@ if CPU_ALLWINNER_A10
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_ARMV7
select ARCH_BOOTBLOCK_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
select HAVE_MONOTONIC_TIMER
select HAVE_UART_SPECIAL
select BOOTBLOCK_CONSOLE

4
src/cpu/amd/agesa/Kconfig
View File

@@ -26,7 +26,9 @@ config CPU_AMD_AGESA
default y if CPU_AMD_AGESA_FAMILY15_TN
default y if CPU_AMD_AGESA_FAMILY16_KB
default n
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select TSC_SYNC_LFENCE
select UDELAY_LAPIC
select LAPIC_MONOTONIC_TIMER

4
src/cpu/amd/geode_gx1/Kconfig
View File

@@ -19,7 +19,9 @@
config CPU_AMD_GEODE_GX1
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
if CPU_AMD_GEODE_GX1

4
src/cpu/amd/geode_gx2/Kconfig
View File

@@ -19,7 +19,9 @@
config CPU_AMD_GEODE_GX2
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
if CPU_AMD_GEODE_GX2

4
src/cpu/amd/geode_lx/Kconfig
View File

@@ -1,6 +1,8 @@
config CPU_AMD_GEODE_LX
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
if CPU_AMD_GEODE_LX

4
src/cpu/amd/model_10xxx/Kconfig
View File

@@ -1,6 +1,8 @@
config CPU_AMD_MODEL_10XXX
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SSE
select SSE2
select MMCONF_SUPPORT_DEFAULT

4
src/cpu/amd/model_fxx/Kconfig
View File

@@ -1,6 +1,8 @@
config CPU_AMD_MODEL_FXX
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select MMX
select SSE
select SSE2

4
src/cpu/amd/sc520/Kconfig
View File

@@ -1,3 +1,5 @@
config CPU_AMD_SC520
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32

4
src/cpu/armltd/cortex-a9/Kconfig
View File

@@ -1,6 +1,8 @@
config CPU_ARMLTD_CORTEX_A9
bool
select ARCH_ARMV7
select ARCH_BOOTBLOCK_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
default n
if CPU_ARMLTD_CORTEX_A9

4
src/cpu/dmp/vortex86ex/Kconfig
View File

@@ -19,5 +19,7 @@
config CPU_DMP_VORTEX86EX
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select UDELAY_TSC

4
src/cpu/intel/ep80579/Kconfig
View File

@@ -1,5 +1,7 @@
config CPU_INTEL_EP80579
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SSE
select SUPPORT_CPU_UCODE_IN_CBFS

4
src/cpu/intel/fsp_model_206ax/Kconfig
View File

@@ -28,7 +28,9 @@ if CPU_INTEL_FSP_MODEL_206AX || CPU_INTEL_FSP_MODEL_306AX
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select UDELAY_LAPIC

5
src/cpu/intel/fsp_model_206ax/Makefile.inc
View File

@@ -9,4 +9,7 @@ cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
cpu_incs += $(src)/cpu/intel/fsp_model_206ax/cache_as_ram.inc
CC := $(CC) -I$(CONFIG_MICROCODE_INCLUDE_PATH)
CC_bootblock := $(CC_bootblock) -I$(CONFIG_MICROCODE_INCLUDE_PATH)
CC_romstage := $(CC_romstage) -I$(CONFIG_MICROCODE_INCLUDE_PATH)
CC_ramstage := $(CC_ramstage) -I$(CONFIG_MICROCODE_INCLUDE_PATH)
CC_x86_32 := $(CC_x86_32) -I$(CONFIG_MICROCODE_INCLUDE_PATH)

4
src/cpu/intel/haswell/Kconfig
View File

@@ -6,7 +6,9 @@ if CPU_INTEL_HASWELL
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select BACKUP_DEFAULT_SMM_REGION
select SMP
select SSE2

4
src/cpu/intel/model_1067x/Kconfig
View File

@@ -1,6 +1,8 @@
config CPU_INTEL_MODEL_1067X
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select TSC_SYNC_MFENCE

4
src/cpu/intel/model_106cx/Kconfig
View File

@@ -1,6 +1,8 @@
config CPU_INTEL_MODEL_106CX
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select UDELAY_LAPIC

4
src/cpu/intel/model_2065x/Kconfig
View File

@@ -5,7 +5,9 @@ if CPU_INTEL_MODEL_2065X
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE
select SSE2

4
src/cpu/intel/model_206ax/Kconfig
View File

@@ -8,7 +8,9 @@ if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select UDELAY_LAPIC

4
src/cpu/intel/model_65x/Kconfig
View File

@@ -1,5 +1,7 @@
config CPU_INTEL_MODEL_65X
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS

4
src/cpu/intel/model_67x/Kconfig
View File

@@ -1,5 +1,7 @@
config CPU_INTEL_MODEL_67X
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS

4
src/cpu/intel/model_68x/Kconfig
View File

@@ -20,6 +20,8 @@
config CPU_INTEL_MODEL_68X
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS

4
src/cpu/intel/model_69x/Kconfig
View File

@@ -1,5 +1,7 @@
config CPU_INTEL_MODEL_69X
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS

4
src/cpu/intel/model_6bx/Kconfig
View File

@@ -1,5 +1,7 @@
config CPU_INTEL_MODEL_6BX
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS

4
src/cpu/intel/model_6dx/Kconfig
View File

@@ -1,5 +1,7 @@
config CPU_INTEL_MODEL_6DX
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS

4
src/cpu/intel/model_6ex/Kconfig
View File

@@ -1,6 +1,8 @@
config CPU_INTEL_MODEL_6EX
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select UDELAY_LAPIC

4
src/cpu/intel/model_6fx/Kconfig
View File

@@ -1,6 +1,8 @@
config CPU_INTEL_MODEL_6FX
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select UDELAY_LAPIC

4
src/cpu/intel/model_6xx/Kconfig
View File

@@ -1,5 +1,7 @@
config CPU_INTEL_MODEL_6XX
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS

4
src/cpu/intel/model_f0x/Kconfig
View File

@@ -1,5 +1,7 @@
config CPU_INTEL_MODEL_F0X
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS

4
src/cpu/intel/model_f1x/Kconfig
View File

@@ -1,5 +1,7 @@
config CPU_INTEL_MODEL_F1X
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS

4
src/cpu/intel/model_f2x/Kconfig
View File

@@ -1,5 +1,7 @@
config CPU_INTEL_MODEL_F2X
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS

4
src/cpu/intel/model_f3x/Kconfig
View File

@@ -1,5 +1,7 @@
config CPU_INTEL_MODEL_F3X
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS

4
src/cpu/intel/model_f4x/Kconfig
View File

@@ -1,5 +1,7 @@
config CPU_INTEL_MODEL_F4X
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS

4
src/cpu/qemu-x86/Kconfig
View File

@@ -19,4 +19,6 @@
config CPU_QEMU_X86
bool
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32

4
src/cpu/samsung/exynos5250/Kconfig
View File

@@ -1,5 +1,7 @@
config CPU_SAMSUNG_EXYNOS5250
select ARCH_ARMV7
select ARCH_BOOTBLOCK_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
select HAVE_MONOTONIC_TIMER
select HAVE_UART_SPECIAL
select DYNAMIC_CBMEM

4
src/cpu/samsung/exynos5420/Kconfig
View File

@@ -1,5 +1,7 @@
config CPU_SAMSUNG_EXYNOS5420
select ARCH_ARMV7
select ARCH_BOOTBLOCK_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
select HAVE_MONOTONIC_TIMER
select HAVE_UART_SPECIAL
select DYNAMIC_CBMEM

4
src/cpu/ti/am335x/Kconfig
View File

@@ -1,5 +1,7 @@
config CPU_TI_AM335X
select ARCH_ARMV7
select ARCH_BOOTBLOCK_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
select HAVE_MONOTONIC_TIMER
select HAVE_UART_SPECIAL
select BOOTBLOCK_CONSOLE

5
src/cpu/ti/am335x/Makefile.inc
View File

@@ -16,6 +16,7 @@ ramstage-y += uart.c
endif
$(call add-class,omap-header)
$(eval $(call create_class_compiler,omap-header,armv7))
real-target: $(obj)/MLO
@@ -28,14 +29,14 @@ get_header_size= \
$(obj)/omap-header.bin: $$(omap-header-objs) $$(header_ld) $(obj)/coreboot.rom
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) -nostdlib -nostartfiles -static -include $(obj)/config.h \
$(CC_omap-header) -nostdlib -nostartfiles -static -include $(obj)/config.h \
-Wl,--defsym,header_load_size=$(strip \
$(call get_header_size,$(obj)/coreboot.rom, \
$(CONFIG_CBFS_PREFIX)/romstage \
) \
) \
-o $@.tmp $< -T $(header_ld)
$(OBJCOPY) --only-section=".header" -O binary $@.tmp $@
$(OBJCOPY_omap-header) --only-section=".header" -O binary $@.tmp $@
$(obj)/MLO: $(obj)/coreboot.rom $(obj)/omap-header.bin
@printf " HEADER $(subst $(obj)/,,$(@))\n"

4
src/cpu/via/c3/Kconfig
View File

@@ -5,7 +5,9 @@ if CPU_VIA_C3
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select UDELAY_TSC
select MMX
select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS

4
src/cpu/via/c7/Kconfig
View File

@@ -5,7 +5,9 @@ if CPU_VIA_C7
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select UDELAY_TSC
select MMX
select SSE2

4
src/cpu/via/nano/Kconfig
View File

@@ -24,7 +24,9 @@ if CPU_VIA_NANO
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select UDELAY_TSC
select MMX
select SSE2

6
src/cpu/x86/Makefile.inc
View File

@@ -16,13 +16,13 @@ endif
rmodules-$(CONFIG_PARALLEL_MP) += sipi_vector.S
$(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules.o
$(CC) $(LDFLAGS) -nostdlib -r -o $@ $^
$(CC_ramstage) $(LDFLAGS) -nostdlib -r -o $@ $^
$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0))
$(SIPI_BIN): $(SIPI_RMOD)
$(OBJCOPY) -O binary $< $@
$(OBJCOPY_ramstage) -O binary $< $@
$(SIPI_BIN).ramstage.o: $(SIPI_BIN)
@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
cd $(dir $@); $(OBJCOPY) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@)
cd $(dir $@); $(OBJCOPY_ramstage) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@)

30
src/cpu/x86/smm/Makefile.inc
View File

@@ -19,7 +19,11 @@
ramstage-$(CONFIG_BACKUP_DEFAULT_SMM_REGION) += backup_default_smm.c
$(eval $(call create_class_compiler,smm,x86_32))
$(eval $(call create_class_compiler,smmstub,x86_32))
ifeq ($(CONFIG_SMM_MODULES),y)
smmstub-y += smm_stub.S
smm-y += smm_module_handler.c
@@ -32,32 +36,32 @@ ramstage-srcs += $(obj)/cpu/x86/smm/smmstub
# SMM Stub Module. The stub is used as a trampoline for relocation and normal
# SMM handling.
$(obj)/cpu/x86/smm/smmstub.o: $$(smmstub-objs)
$(CC) $(LDFLAGS) -nostdlib -r -o $@ $^
$(CC_smmstub) $(LDFLAGS) -nostdlib -r -o $@ $^
# Link the SMM stub module with a 0-byte heap.
$(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smmstub.elf, $(obj)/cpu/x86/smm/smmstub.o, 0))
$(obj)/cpu/x86/smm/smmstub: $(obj)/cpu/x86/smm/smmstub.elf.rmod
$(OBJCOPY) -O binary $< $@
$(OBJCOPY_smmstub) -O binary $< $@
$(obj)/cpu/x86/smm/smmstub.ramstage.o: $(obj)/cpu/x86/smm/smmstub
@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
cd $(dir $@); $(OBJCOPY) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@)
cd $(dir $@); $(OBJCOPY_smmstub) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@)
# C-based SMM handler.
$(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(LIBGCC_FILE_NAME)
$(CC) $(LDFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(smm-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group
$(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(LIBGCC_FILE_NAME_smm)
$(CC_smm) $(LDFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(smm-objs) $(LIBGCC_FILE_NAME_smm) -Wl,--end-group
$(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smm.elf, $(obj)/cpu/x86/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE)))
$(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod
$(OBJCOPY) -O binary $< $@
$(OBJCOPY_smm) -O binary $< $@
$(obj)/cpu/x86/smm/smm.ramstage.o: $(obj)/cpu/x86/smm/smm
@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
cd $(dir $@); $(OBJCOPY) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@)
cd $(dir $@); $(OBJCOPY_smm) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@)
else # CONFIG_SMM_MODULES
@@ -79,18 +83,18 @@ endif
smm-y += smihandler.c
$(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(LIBGCC_FILE_NAME)
$(CC) $(LDFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(smm-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group
$(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(LIBGCC_FILE_NAME_smm)
$(CC_smm) $(LDFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(smm-objs) $(LIBGCC_FILE_NAME_smm) -Wl,--end-group
$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/ldoptions
$(CC) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o
$(NM) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
$(OBJCOPY) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm
$(CC_smm) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o
$(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
$(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm
# change to the target path because objcopy will use the path name in its
# ELF symbol names.
$(obj)/cpu/x86/smm/smm_wrap.ramstage.o: $(obj)/cpu/x86/smm/smm_wrap
@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
cd $(obj)/cpu/x86/smm; $(OBJCOPY) -I binary smm -O elf32-i386 -B i386 smm_wrap.ramstage.o
cd $(obj)/cpu/x86/smm; $(OBJCOPY_smm) -I binary smm -O elf32-i386 -B i386 smm_wrap.ramstage.o
endif # CONFIG_SMM_MODULES

2
src/device/Makefile.inc
View File

@@ -9,7 +9,7 @@ ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c
ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c
ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c
ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c
ramstage-$(CONFIG_ARCH_X86) += pnp_device.c
ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += pnp_device.c
ramstage-$(CONFIG_PCI) += pci_ops.c
ramstage-$(CONFIG_PCI) += pci_early.c
ramstage-y += smbus_ops.c

3
src/include/version.h
View File

@@ -15,8 +15,5 @@ extern const char coreboot_compile_time[];
extern const char coreboot_compile_by[];
extern const char coreboot_compile_host[];
extern const char coreboot_compile_domain[];
extern const char coreboot_compiler[];
extern const char coreboot_linker[];
extern const char coreboot_assembler[];
#endif /* VERSION_H */

46
src/lib/Makefile.inc
View File

@@ -19,27 +19,10 @@
subdirs-y += loaders
bootblock-y += cbfs.c
ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
bootblock-y += memset.c
endif
bootblock-y += memchr.c
ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
bootblock-y += memcpy.c
endif
bootblock-y += memcmp.c
ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y)
bootblock-y += memmove.c
endif
ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
romstage-y += memset.c
rmodules-y += memset.c
endif
romstage-y += memchr.c
ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
romstage-y += memcpy.c
rmodules-y += memcpy.c
endif
romstage-y += memcmp.c
rmodules-y += memcmp.c
romstage-y += cbfs.c
@@ -53,26 +36,14 @@ romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
endif
romstage-y += compute_ip_checksum.c
ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y)
romstage-y += memmove.c
endif
romstage-$(CONFIG_ARCH_X86) += gcc.c
romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += gcc.c
ramstage-y += hardwaremain.c
ramstage-y += selfboot.c
ramstage-y += coreboot_table.c
ramstage-y += bootmem.c
ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
ramstage-y += memset.c
endif
ramstage-y += memchr.c
ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
ramstage-y += memcpy.c
endif
ramstage-y += memcmp.c
ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y)
ramstage-y += memmove.c
endif
ramstage-y += malloc.c
smm-$(CONFIG_SMM_TSEG) += malloc.c
ramstage-y += delay.c
@@ -83,7 +54,7 @@ ramstage-y += cbfs.c
ramstage-y += lzma.c
#ramstage-y += lzmadecode.c
ramstage-y += stack.c
ramstage-$(CONFIG_ARCH_X86) += gcc.c
ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c
ramstage-y += clog2.c
romstage-y += clog2.c
ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
@@ -114,15 +85,6 @@ ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += ramstage_cache.c
ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
smm-y += memset.c
endif
ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
smm-y += memcpy.c
endif
ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y)
smm-y += memmove.c
endif
smm-y += cbfs.c memcmp.c
smm-y += gcc.c
@@ -146,8 +108,8 @@ RMODULE_LDFLAGS := -nostartfiles -Wl,--emit-relocs -Wl,-z,defs -Wl,-Bsymbolic -
# rmdoule is named $(1).rmod
define rmodule_link
$(strip $(1)): $(strip $(2)) $$(RMODULE_LDSCRIPT) $$(obj)/ldoptions $$(RMODTOOL)
$$(CC) $$(CFLAGS) $$(RMODULE_LDFLAGS) -Wl,--defsym=__heap_size=$(strip $(3)) -o $$@ -Wl,--start-group $(strip $(2)) $$(LIBGCC_FILE_NAME) -Wl,--end-group
$$(NM) -n $$@ > $$(basename $$@).map
$$(CC_rmodules) $$(CFLAGS_rmodules) $$(RMODULE_LDFLAGS) -Wl,--defsym=__heap_size=$(strip $(3)) -o $$@ -Wl,--start-group $(strip $(2)) $$(LIBGCC_FILE_NAME_rmodules) -Wl,--end-group
$$(NM_rmodules) -n $$@ > $$(basename $$@).map
$(strip $(1)).rmod: $(strip $(1))
$$(RMODTOOL) -i $$^ -o $$@

3
src/lib/coreboot_table.c
View File

@@ -284,9 +284,6 @@ static void lb_strings(struct lb_header *header)
{ LB_TAG_COMPILE_BY, coreboot_compile_by, },
{ LB_TAG_COMPILE_HOST, coreboot_compile_host, },
{ LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, },
{ LB_TAG_COMPILER, coreboot_compiler, },
{ LB_TAG_LINKER, coreboot_linker, },
{ LB_TAG_ASSEMBLER, coreboot_assembler, },
};
unsigned int i;
for(i = 0; i < ARRAY_SIZE(strings); i++) {

13
src/lib/version.c
View File

@@ -25,16 +25,6 @@
#error COREBOOT_COMPILE_HOST not defined
#endif
#ifndef COREBOOT_COMPILER
#error COREBOOT_COMPILER not defined
#endif
#ifndef COREBOOT_LINKER
#error COREBOOT_LINKER not defined
#endif
#ifndef COREBOOT_ASSEMBLER
#error COREBOOT_ASSEMBLER not defined
#endif
#ifndef COREBOOT_EXTRA_VERSION
#define COREBOOT_EXTRA_VERSION ""
#endif
@@ -50,7 +40,4 @@ const char coreboot_compile_time[] = COREBOOT_COMPILE_TIME;
const char coreboot_compile_by[] = COREBOOT_COMPILE_BY;
const char coreboot_compile_host[] = COREBOOT_COMPILE_HOST;
const char coreboot_compile_domain[] = COREBOOT_COMPILE_DOMAIN;
const char coreboot_compiler[] = COREBOOT_COMPILER;
const char coreboot_linker[] = COREBOOT_LINKER;
const char coreboot_assembler[] = COREBOOT_ASSEMBLER;

2
src/mainboard/advansus/a785e-i/Makefile.inc
View File

@@ -11,5 +11,5 @@ ifneq ($(CONFIG_CPU_AMD_AGESA),y)
-I$(AGESA_ROOT)/Proc/CPU/ \
-I$(AGESA_ROOT)/Proc/CPU/Family
CFLAGS += $(AGESA_INC)
CFLAGS_common += $(AGESA_INC)
endif

2
src/mainboard/asus/m5a88-v/Makefile.inc
View File

@@ -11,5 +11,5 @@ ifneq ($(CONFIG_CPU_AMD_AGESA),y)
-I$(AGESA_ROOT)/Proc/CPU/ \
-I$(AGESA_ROOT)/Proc/CPU/Family
CFLAGS += $(AGESA_INC)
CFLAGS_common += $(AGESA_INC)
endif

2
src/mainboard/avalue/eax-785e/Makefile.inc
View File

@@ -11,5 +11,5 @@ ifneq ($(CONFIG_CPU_AMD_AGESA),y)
-I$(AGESA_ROOT)/Proc/CPU/ \
-I$(AGESA_ROOT)/Proc/CPU/Family
CFLAGS += $(AGESA_INC)
CFLAGS_common += $(AGESA_INC)
endif

4
src/mainboard/bifferos/bifferboard/Kconfig
View File

@@ -2,7 +2,9 @@ if BOARD_BIFFEROS_BIFFERBOARD
config BOARD_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ROMCC
select BOARD_ROMSIZE_KB_128
select NORTHBRIDGE_RDC_R8610

4
src/mainboard/packardbell/ms2290/Kconfig
View File

@@ -2,7 +2,9 @@ if BOARD_PACKARDBELL_MS2290
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select NORTHBRIDGE_INTEL_NEHALEM
select SOUTHBRIDGE_INTEL_IBEXPEAK
select HAVE_OPTION_TABLE

4
src/soc/intel/baytrail/Kconfig
View File

@@ -8,7 +8,9 @@ if SOC_INTEL_BAYTRAIL
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select CACHE_MRC_SETTINGS
select CAR_MIGRATION
select COLLECT_TIMESTAMPS

2
src/superio/Makefile.inc
View File

@@ -28,4 +28,4 @@ subdirs-y += smsc
subdirs-y += via
subdirs-y += winbond
ramstage-$(CONFIG_ARCH_X86) += common/conf_mode.c
ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += common/conf_mode.c

5
src/vendorcode/amd/agesa/f10/Makefile.inc
View File

@@ -48,5 +48,8 @@ AGESA_CFLAGS = -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
export AGESA_ROOT
export AGESA_INC
export AGESA_CFLAGS
CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS)
CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS)
CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS)

7
src/vendorcode/amd/agesa/f12/Makefile.inc
View File

@@ -86,5 +86,8 @@ AGESA_CFLAGS =-march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-st
export AGESA_ROOT := $(AGESA_ROOT)
export AGESA_INC := $(AGESA_INC)
export AGESA_CFLAGS := $(AGESA_CFLAGS)
CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS)
#######################################################################
CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS)
CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS)
#######################################################################

7
src/vendorcode/amd/agesa/f14/Makefile.inc
View File

@@ -67,11 +67,16 @@ AGESA_CFLAGS =-march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-st
export AGESA_ROOT := $(AGESA_ROOT)
export AGESA_INC := $(AGESA_INC)
export AGESA_CFLAGS := $(AGESA_CFLAGS)
CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS)
CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS)
CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS)
#######################################################################
classes-y += libagesa
$(eval $(call create_class_compiler,libagesa,x86_32))
libagesa-y = Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
libagesa-y += Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c

6
src/vendorcode/amd/agesa/f15/Makefile.inc
View File

@@ -529,5 +529,7 @@ AGESA_CFLAGS = -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
export AGESA_ROOT
export AGESA_INC
export AGESA_CFLAGS
CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS)
CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS)
CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS)

7
src/vendorcode/amd/agesa/f15tn/Makefile.inc
View File

@@ -91,11 +91,16 @@ AGESA_CFLAGS =-march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-st
export AGESA_ROOT := $(AGESA_ROOT)
export AGESA_INC := $(AGESA_INC)
export AGESA_CFLAGS := $(AGESA_CFLAGS)
CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS)
CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS)
CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS)
#######################################################################
classes-y += libagesa
$(eval $(call create_class_compiler,libagesa,x86_32))
libagesa-y += Legacy/Proc/Dispatcher.c
libagesa-y += Legacy/Proc/agesaCallouts.c
libagesa-y += Legacy/Proc/hobTransfer.c

5
src/vendorcode/amd/agesa/f16kb/Makefile.inc
View File

@@ -98,5 +98,8 @@ AGESA_CFLAGS =-march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-st
export AGESA_ROOT := $(AGESA_ROOT)
export AGESA_INC := $(AGESA_INC)
export AGESA_CFLAGS := $(AGESA_CFLAGS)
CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS)
CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS)
CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS)
#######################################################################

6
src/vendorcode/amd/cimx/rd890/Makefile.inc
View File

@@ -113,7 +113,11 @@ NB_CIMX_CFLAGS =
export CIMX_ROOT
export NB_CIMX_INC
export NB_CIMX_CFLAGS
CC := $(CC) $(NB_CIMX_CFLAGS) $(NB_CIMX_INC)
CC_bootblock := $(CC_bootblock) $(NB_CIMX_CFLAGS) $(NB_CIMX_INC)
CC_romstage := $(CC_romstage) $(NB_CIMX_CFLAGS) $(NB_CIMX_INC)
CC_ramstage := $(CC_ramstage) $(NB_CIMX_CFLAGS) $(NB_CIMX_INC)
CC_x86_32 := $(CC_x86_32) $(NB_CIMX_CFLAGS) $(NB_CIMX_INC)
#######################################################################

5
src/vendorcode/amd/cimx/sb700/Makefile.inc
View File

@@ -72,7 +72,10 @@ SB_CIMX_CFLAGS =
export CIMX_ROOT
export SB_CIMX_INC
export SB_CIMX_CFLAGS
CC := $(CC) $(SB_CIMX_CFLAGS) $(SB_CIMX_INC)
CC_bootblock := $(CC_bootblock) $(SB_CIMX_INC)
CC_romstage := $(CC_romstage) $(SB_CIMX_INC)
CC_ramstage := $(CC_ramstage) $(SB_CIMX_INC)
CC_x86_32 := $(CC_x86_32) $(SB_CIMX_INC)
#######################################################################

5
src/vendorcode/amd/cimx/sb800/Makefile.inc
View File

@@ -79,7 +79,10 @@ CIMX_CFLAGS =
export CIMX_ROOT
export CIMX_INC
export CIMX_CFLAGS
CC := $(CC) $(CIMX_INC)
CC_bootblock := $(CC_bootblock) $(CIMX_INC)
CC_romstage := $(CC_romstage) $(CIMX_INC)
CC_ramstage := $(CC_ramstage) $(CIMX_INC)
CC_x86_32 := $(CC_x86_32) $(CIMX_INC)
#######################################################################

5
src/vendorcode/amd/cimx/sb900/Makefile.inc
View File

@@ -82,7 +82,10 @@ CIMX_CFLAGS =
export CIMX_ROOT
export CIMX_INC
export CIMX_CFLAGS
CC := $(CC) $(CIMX_INC)
CC_bootblock := $(CC_bootblock) $(CIMX_INC)
CC_romstage := $(CC_romstage) $(CIMX_INC)
CC_ramstage := $(CC_ramstage) $(CIMX_INC)
CC_x86_32 := $(CC_x86_32) $(CIMX_INC)
#######################################################################

22
src/vendorcode/google/chromeos/Makefile.inc
View File

@@ -19,9 +19,9 @@
romstage-y += chromeos.c
ramstage-y += chromeos.c
romstage-$(CONFIG_ARCH_X86) += vbnv.c
ramstage-$(CONFIG_ARCH_X86) += vbnv.c
romstage-$(CONFIG_ARCH_X86) += vboot.c
romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vbnv.c
ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += vbnv.c
romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vboot.c
ramstage-y += gnvs.c
romstage-y += fmap.c
ramstage-y += fmap.c
@@ -33,9 +33,9 @@ romstage-srcs += src/mainboard/$(MAINBOARDDIR)/chromeos.c
endif
ifeq ($(MOCK_TPM),1)
CFLAGS += -DMOCK_TPM=1
CFLAGS_common += -DMOCK_TPM=1
else
CFLAGS += -DMOCK_TPM=0
CFLAGS_common += -DMOCK_TPM=0
endif
ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y)
@@ -43,7 +43,12 @@ romstage-y += vboot_loader.c
rmodules-y += vboot_wrapper.c
VB_LIB = $(obj)/external/vboot_reference/vboot_fw.a
VB_FIRMWARE_ARCH := $(ARCHDIR-y)
# Currently, vboot comes into picture only during the romstage, thus
# is compiled for being used in romstage only. Since, we are splitting
# up all components in one of the three stages of coreboot, vboot seems
# most logical to fall under the romstage. Thus, all references to arch
# and other compiler stuff for vboot is using the romstage arch.
VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-ROMSTAGE-y))
VB_SOURCE := vboot_reference
# Add the vboot include paths.
@@ -62,11 +67,11 @@ VBOOT_STUB_DEPS += $(obj)/arch/x86/lib/memcpy.rmodules.o
VBOOT_STUB_DEPS += $(VB_LIB)
# Remove the '-include' option since that will break vboot's build and ensure
# vboot_reference can get to coreboot's include files.
VBOOT_CFLAGS += $(patsubst -I%,-I../%,$(filter-out -include $(src)/include/kconfig.h, $(CFLAGS)))
VBOOT_CFLAGS += $(patsubst -I%,-I../%,$(filter-out -include $(src)/include/kconfig.h, $(CFLAGS_romstage)))
VBOOT_CFLAGS += -DVBOOT_DEBUG
$(VBOOT_STUB_DOTO): $(VBOOT_STUB_DEPS)
$(CC) $(LDFLAGS) -nostdlib -r -o $@ $^
$(CC_romstage) $(LDFLAGS) -nostdlib -r -o $@ $^
# Link the vbootstub module with a 64KiB-byte heap.
$(eval $(call rmodule_link,$(VBOOT_STUB_ELF), $(VBOOT_STUB_DOTO), 0x10000))
@@ -75,6 +80,7 @@ $(eval $(call rmodule_link,$(VBOOT_STUB_ELF), $(VBOOT_STUB_DOTO), 0x10000))
$(VB_LIB):
@printf " MAKE $(subst $(obj)/,,$(@))\n"
$(Q)FIRMWARE_ARCH=$(VB_FIRMWARE_ARCH) \
CC="$(CC_romstage)" \
CFLAGS="$(VBOOT_CFLAGS)" \
make -C $(VB_SOURCE) \
BUILD=../$(dir $(VB_LIB)) \

5
src/vendorcode/intel/Makefile.inc
View File

@@ -23,5 +23,8 @@ FSP_SRC_FILES := $(wildcard src/vendorcode/intel/$(FSP_PATH)srx/*.c)
FSP_C_INPUTS := $(foreach file, $(FSP_SRC_FILES), $(FSP_PATH)srx/$(notdir $(file)))
ramstage-y += $(FSP_C_INPUTS)
CC := $(CC) -Isrc/vendorcode/intel/$(FSP_PATH)include
CC_bootblock := $(CC_bootblock) -Isrc/vendorcode/intel/$(FSP_PATH)include
CC_romstage := $(CC_romstage) -Isrc/vendorcode/intel/$(FSP_PATH)include
CC_ramstage := $(CC_ramstage) -Isrc/vendorcode/intel/$(FSP_PATH)include
CC_x86_32 := $(CC_x86_32) -Isrc/vendorcode/intel/$(FSP_PATH)include
endif