added config and other test files.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
316
src/mainboard/amd/solo/Config.lb
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316
src/mainboard/amd/solo/Config.lb
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#
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###
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### Build code to export a CMOS option table
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###
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default HAVE_OPTION_TABLE=1
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option HAVE_MP_TABLE=0
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####
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#### Build options
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####
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#
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###
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### Location of the DIMM EEPROMS on the SMBUS
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### This is fixed into a narrow range by the DIMM package standard.
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###
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option SMBUS_MEM_DEVICE_START=(0xa << 3)
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option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +1)
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option SMBUS_MEM_DEVICE_INC=1
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default CONFIG_CONSOLE_VGA=0
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default CONFIG_CONSOLE_LOGBUF=0
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default CONFIG_CONSOLE_SROM=0
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default CONFIG_SMP=0
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default CONFIG_UDELAY_TSC=0
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#
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###
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### Customize our winbond superio chip for this motherboard
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###
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option SIO_BASE=0x2e
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option SIO_SYSTEM_CLK_INPUT=0
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option CONFIG_CONSOLE_SERIAL8250=0
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#
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###
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### Build code for the fallback boot
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###
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option HAVE_FALLBACK_BOOT=1
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#
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###
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### Build code to reset the motherboard from linuxBIOS
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###
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## option HAVE_HARD_RESET=1
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#
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###
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### Build code to export a programmable irq routing table
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###
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option HAVE_PIRQ_TABLE=1
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option IRQ_SLOT_COUNT=7
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#
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###
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### Build code to export an x86 MP table
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### Useful for specifying IRQ routing values
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###
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##option HAVE_MP_TABLE=1
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#
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###
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### Do not build special code for the keyboard
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###
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default NO_KEYBOARD=1
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#
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###
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### Build code for SMP support
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### Only worry about 2 micro processors
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###
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##option CONFIG_SMP=1
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option MAX_CPUS=1
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#
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###
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### Build code to setup a generic IOAPIC
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###
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option CONFIG_IOAPIC=1
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#
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###
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### MEMORY_HOLE instructs earlymtrr.inc to
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### enable caching from 0-640KB and to disable
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### caching from 640KB-1MB using fixed MTRRs
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###
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### Enabling this option breaks SMP because secondary
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### CPU identification depends on only variable MTRRs
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### being enabled.
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###
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option MEMORY_HOLE=0
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#
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###
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### Enable both fixed and variable MTRRS
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### When we setup MTRRs in mtrr.c
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###
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### We must setup the fixed mtrrs or we confuse SMP secondary
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### processor identification
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###
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option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
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#
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###
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### Clean up the motherboard id strings
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###
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option MAINBOARD_PART_NUMBER="Solo7"
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option MAINBOARD_VENDOR="AMD"
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#
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###
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### Let Assembly code know where on the pci bus the AMD southbridge is
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###
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option AMD8111_DEV=0x3800
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#
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###
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### Call the final_mainboard_fixup function
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###
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option FINAL_MAINBOARD_FIXUP=1
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#
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###
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### Figure out which type of linuxBIOS image to build
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### If we aren't a fallback image we must be a normal image
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### This is useful for optional includes
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###
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default USE_FALLBACK_IMAGE=0
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option USE_NORMAL_IMAGE=(! USE_FALLBACK_IMAGE)
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#
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####
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#### LinuxBIOS layout values
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####
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#
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### ROM_SIZE is the size of boot ROM that this board will use.
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option ROM_SIZE=262144
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#
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### ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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option ROM_IMAGE_SIZE=65535
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#
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###
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### Use a small 8K stack
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###
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option STACK_SIZE=0x2000
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#
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###
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### Use a small 8K heap
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###
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option HEAP_SIZE=0x2000
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#
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###
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### Only use the option table in a normal image
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###
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option USE_OPTION_TABLE=!USE_FALLBACK_IMAGE
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#
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###
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### Compute the location and size of where this firmware image
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### (linuxBIOS plus bootloader) will live in the boot rom chip.
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###
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default FALLBACK_SIZE=65536
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if USE_FALLBACK_IMAGE
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option ROM_SECTION_SIZE = FALLBACK_SIZE
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option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
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end
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if USE_NORMAL_IMAGE
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option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
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option ROM_SECTION_OFFSET= 0
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end
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#
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###
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### Compute the start location and size size of
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### The linuxBIOS bootloader.
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###
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option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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option CONFIG_ROM_STREAM = 1
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#
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###
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### Compute where this copy of linuxBIOS will start in the boot rom
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###
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option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
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#
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###
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### Compute a range of ROM that can cached to speed up linuxBIOS,
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### execution speed.
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###
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##expr XIP_ROM_SIZE = 65536
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##expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE
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##option XIP_ROM_SIZE=65536
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##option XIP_ROM_BASE=0xffff0000
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#
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## XIP_ROM_SIZE && XIP_ROM_BASE values that work.
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##option XIP_ROM_SIZE=0x8000
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##option XIP_ROM_BASE=0xffff8000
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#
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###
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### Compute where the SMP startup code needs to live
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### FIXME I don't see how to make this work for the normal image....
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###
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option START_CPU_SEG=0xf0000
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#
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#
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###
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### Set all of the defaults for an x86 architecture
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###
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#
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#
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###
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### Build the objects we have code for in this directory.
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###
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##object mainboard.o
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driver mainboard.o
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object static_devices.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#
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arch i386 end
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cpu k8 end
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#
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option DEBUG=1
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default USE_FALLBACK_IMAGE=1
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option A=(1+2)
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option B=0xa
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#
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###
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### Build our 16 bit and 32 bit linuxBIOS entry code
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###
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/i386/entry32.lds
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#
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###
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### Build our reset vector (This is where linuxBIOS is entered)
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###
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset16.inc
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ldscript /cpu/i386/reset16.lds
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end
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if USE_NORMAL_IMAGE
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mainboardinit cpu/i386/reset32.inc
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ldscript /cpu/i386/reset32.lds
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end
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#
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#### Should this be in the northbridge code?
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#mainboardinit archi386/lib/cpu_reset.inc
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#
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###
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### Include an id string (For safe flashing)
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###
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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#
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####
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#### This is the early phase of linuxBIOS startup
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#### Things are delicate and we test to see if we should
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#### failover to another image.
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####
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option MAX_REBOOT_CNT=2
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##ldscript arch/i386/lib/failover.lds USE_FALLBACK_IMAGE
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#
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###
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### Setup our mtrrs
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###
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mainboardinit cpu/k8/earlymtrr.inc
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#
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#
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###
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### Only the bootstrap cpu makes it here.
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### Failover if we need to
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###
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#
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if USE_FALLBACK_IMAGE
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mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
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end
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#
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####
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#### O.k. We aren't just an intermediary anymore!
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####
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#
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###
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### When debugging disable the watchdog timer
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###
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##option MAXIMUM_CONSOLE_LOGLEVEL=7
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#default MAXIMUM_CONSOLE_LOGLEVEL=7
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#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
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#if DISABLE_WATCHDOG
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# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
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#end
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#
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###
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### Setup the serial port
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###
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#mainboardinit superiowinbond/w83627hf/setup_serial.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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if USE_FALLBACK_IMAGE mainboardinit archi386/lib/noop_failover.inc end
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#
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###
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### Romcc output
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###
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#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
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#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
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#mainboardinit .failover.inc
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makerule ./auto.E dep "$(MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
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mainboardinit ./auto.inc
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#
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###
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### Setup RAM
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###
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mainboardinit ram/ramtest.inc
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mainboardinit southbridge/amd/amd8111/smbus.inc
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mainboardinit sdram/generic_dump_spd.inc
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#
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###
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### Include the secondary Configuration files
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###
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northbridge amd/amdk8
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end
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southbridge amd/amd8111
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end
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#mainboardinit archi386/smp/secondary.inc
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superio NSC/pc87360
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register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1"
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end
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dir /pc80
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##dir /src/superio/winbond/w83627hf
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cpu p5 end
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cpu p6 end
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cpu k7 end
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cpu k8 end
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