src/cpu: Drop unneeded empty lines
Change-Id: I116b15c83fcc5d69d3f80a2e6cf0fb085064d9a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Michael Niewöhner
parent
b6265139c7
commit
99e0c7ddc1
@@ -97,7 +97,6 @@ static void model_15_init(struct device *dev)
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msr.hi &= ~(1 << (46 - 32));
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msr.hi &= ~(1 << (46 - 32));
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wrmsr(NB_CFG_MSR, msr);
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wrmsr(NB_CFG_MSR, msr);
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/* Write protect SMM space with SMMLOCK. */
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/* Write protect SMM space with SMMLOCK. */
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msr = rdmsr(HWCR_MSR);
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msr = rdmsr(HWCR_MSR);
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msr.lo |= (1 << 0);
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msr.lo |= (1 << 0);
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@@ -33,8 +33,6 @@
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#define SMRR_SUPPORTED (1 << 11)
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#define SMRR_SUPPORTED (1 << 11)
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#define PRMRR_SUPPORTED (1 << 12)
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#define PRMRR_SUPPORTED (1 << 12)
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static void update_save_state(int cpu, uintptr_t curr_smbase,
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static void update_save_state(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase,
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uintptr_t staggered_smbase,
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struct smm_relocation_params *relo_params)
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struct smm_relocation_params *relo_params)
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@@ -52,7 +52,6 @@ void intel_sibling_init(struct device *cpu)
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cpu_path.type = DEVICE_PATH_APIC;
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cpu_path.type = DEVICE_PATH_APIC;
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cpu_path.apic.apic_id = cpu->path.apic.apic_id + i;
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cpu_path.apic.apic_id = cpu->path.apic.apic_id + i;
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/* Allocate new CPU device structure iff sibling CPU
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/* Allocate new CPU device structure iff sibling CPU
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* was not in static device tree.
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* was not in static device tree.
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*/
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*/
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@@ -242,7 +242,6 @@ static void model_1067x_init(struct device *cpu)
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{
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{
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char processor_name[49];
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char processor_name[49];
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/* Gather some information: */
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/* Gather some information: */
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const struct cpuid_result cpuid1 = cpuid(1);
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const struct cpuid_result cpuid1 = cpuid(1);
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@@ -265,7 +264,6 @@ static void model_1067x_init(struct device *cpu)
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/* Test for TM2 only if EIST is available. */
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/* Test for TM2 only if EIST is available. */
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const char tm2 = eist && (cpuid1.ecx & (1 << 8));
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const char tm2 = eist && (cpuid1.ecx & (1 << 8));
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/* Turn on caching if we haven't already */
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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x86_enable_cache();
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@@ -110,7 +110,6 @@ int cpu_config_tdp_levels(void)
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return (platform_info.hi >> 1) & 3;
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return (platform_info.hi >> 1) & 3;
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}
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}
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static void configure_thermal_target(void)
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static void configure_thermal_target(void)
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{
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{
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struct cpu_intel_model_2065x_config *conf;
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struct cpu_intel_model_2065x_config *conf;
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@@ -158,7 +157,6 @@ static void enable_lapic_tpr(void)
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wrmsr(MSR_PIC_MSG_CONTROL, msr);
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wrmsr(MSR_PIC_MSG_CONTROL, msr);
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}
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}
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static void set_max_ratio(void)
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static void set_max_ratio(void)
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{
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{
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msr_t msr, perf_ctl;
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msr_t msr, perf_ctl;
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@@ -282,7 +280,6 @@ static void post_mp_init(void)
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smm_lock();
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smm_lock();
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}
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}
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static const struct mp_ops mp_ops = {
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_cpu_count = get_cpu_count,
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@@ -534,7 +534,6 @@ static void post_mp_init(void)
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smm_lock();
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smm_lock();
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}
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}
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static const struct mp_ops mp_ops = {
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_cpu_count = get_cpu_count,
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@@ -189,7 +189,6 @@ int calculate_l2_latency(void)
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return 0;
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return 0;
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}
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}
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/* Setup address, data_high:data_low into the L2
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/* Setup address, data_high:data_low into the L2
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* control registers and then issue command with correct cache way
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* control registers and then issue command with correct cache way
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*/
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*/
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@@ -25,7 +25,6 @@
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#define G_SMRAME (1 << 3)
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#define G_SMRAME (1 << 3)
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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/* On model_6fx, model_1067x and model_106cx SMRR functions slightly
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/* On model_6fx, model_1067x and model_106cx SMRR functions slightly
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differently. The MSR are at different location from the rest
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differently. The MSR are at different location from the rest
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and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */
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and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */
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@@ -104,7 +104,6 @@ void speedstep_gen_pstates(sst_table_t *const table)
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/* Gather speedstep limits. */
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/* Gather speedstep limits. */
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speedstep_get_limits(¶ms);
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speedstep_get_limits(¶ms);
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/*\ First, find the number of normal states: \*/
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/*\ First, find the number of normal states: \*/
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/* Calculate with doubled values to work
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/* Calculate with doubled values to work
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@@ -130,7 +129,6 @@ void speedstep_gen_pstates(sst_table_t *const table)
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if (states < 2) /* Report at least two normal states. */
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if (states < 2) /* Report at least two normal states. */
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states = 2;
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states = 2;
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/*\ Now, fill the table: \*/
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/*\ Now, fill the table: \*/
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table->num_states = 0;
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table->num_states = 0;
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@@ -106,7 +106,6 @@ struct saved_msr {
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uint32_t hi;
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uint32_t hi;
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} __packed;
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} __packed;
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/* The sipi vector rmodule is included in the ramstage using 'objdump -B'. */
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/* The sipi vector rmodule is included in the ramstage using 'objdump -B'. */
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extern char _binary_sipi_vector_start[];
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extern char _binary_sipi_vector_start[];
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@@ -69,7 +69,6 @@ static void smi_set_eos(void)
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southbridge_smi_set_eos();
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southbridge_smi_set_eos();
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}
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}
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static u32 pci_orig;
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static u32 pci_orig;
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/**
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/**
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@@ -88,7 +87,6 @@ static void smi_restore_pci_address(void)
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outl(pci_orig, 0xcf8);
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outl(pci_orig, 0xcf8);
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}
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}
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static const struct smm_runtime *smm_runtime;
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static const struct smm_runtime *smm_runtime;
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struct global_nvs *gnvs;
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struct global_nvs *gnvs;
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@@ -590,7 +590,6 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params)
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fxsave_area = NULL;
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fxsave_area = NULL;
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}
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}
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handler_size = rmodule_memory_size(&smm_mod);
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handler_size = rmodule_memory_size(&smm_mod);
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base -= handler_size;
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base -= handler_size;
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total_size += handler_size;
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total_size += handler_size;
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