src/cpu: Drop unneeded empty lines
Change-Id: I116b15c83fcc5d69d3f80a2e6cf0fb085064d9a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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			| @@ -97,7 +97,6 @@ static void model_15_init(struct device *dev) | ||||
| 	msr.hi &= ~(1 << (46 - 32)); | ||||
| 	wrmsr(NB_CFG_MSR, msr); | ||||
|  | ||||
|  | ||||
| 	/* Write protect SMM space with SMMLOCK. */ | ||||
| 	msr = rdmsr(HWCR_MSR); | ||||
| 	msr.lo |= (1 << 0); | ||||
|   | ||||
| @@ -33,8 +33,6 @@ | ||||
| #define SMRR_SUPPORTED (1 << 11) | ||||
| #define PRMRR_SUPPORTED (1 << 12) | ||||
|  | ||||
|  | ||||
|  | ||||
| static void update_save_state(int cpu, uintptr_t curr_smbase, | ||||
| 				uintptr_t staggered_smbase, | ||||
| 				struct smm_relocation_params *relo_params) | ||||
|   | ||||
| @@ -52,7 +52,6 @@ void intel_sibling_init(struct device *cpu) | ||||
| 		cpu_path.type = DEVICE_PATH_APIC; | ||||
| 		cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; | ||||
|  | ||||
|  | ||||
| 		/* Allocate new CPU device structure iff sibling CPU | ||||
| 		 * was not in static device tree. | ||||
| 		 */ | ||||
|   | ||||
| @@ -242,7 +242,6 @@ static void model_1067x_init(struct device *cpu) | ||||
| { | ||||
| 	char processor_name[49]; | ||||
|  | ||||
|  | ||||
| 	/* Gather some information: */ | ||||
|  | ||||
| 	const struct cpuid_result cpuid1 = cpuid(1); | ||||
| @@ -265,7 +264,6 @@ static void model_1067x_init(struct device *cpu) | ||||
| 	/* Test for TM2 only if EIST is available. */ | ||||
| 	const char tm2 = eist && (cpuid1.ecx & (1 << 8)); | ||||
|  | ||||
|  | ||||
| 	/* Turn on caching if we haven't already */ | ||||
| 	x86_enable_cache(); | ||||
|  | ||||
|   | ||||
| @@ -110,7 +110,6 @@ int cpu_config_tdp_levels(void) | ||||
| 	return (platform_info.hi >> 1) & 3; | ||||
| } | ||||
|  | ||||
|  | ||||
| static void configure_thermal_target(void) | ||||
| { | ||||
| 	struct cpu_intel_model_2065x_config *conf; | ||||
| @@ -158,7 +157,6 @@ static void enable_lapic_tpr(void) | ||||
| 	wrmsr(MSR_PIC_MSG_CONTROL, msr); | ||||
| } | ||||
|  | ||||
|  | ||||
| static void set_max_ratio(void) | ||||
| { | ||||
| 	msr_t msr, perf_ctl; | ||||
| @@ -282,7 +280,6 @@ static void post_mp_init(void) | ||||
| 	smm_lock(); | ||||
| } | ||||
|  | ||||
|  | ||||
| static const struct mp_ops mp_ops = { | ||||
| 	.pre_mp_init = pre_mp_init, | ||||
| 	.get_cpu_count = get_cpu_count, | ||||
|   | ||||
| @@ -534,7 +534,6 @@ static void post_mp_init(void) | ||||
| 	smm_lock(); | ||||
| } | ||||
|  | ||||
|  | ||||
| static const struct mp_ops mp_ops = { | ||||
| 	.pre_mp_init = pre_mp_init, | ||||
| 	.get_cpu_count = get_cpu_count, | ||||
|   | ||||
| @@ -189,7 +189,6 @@ int calculate_l2_latency(void) | ||||
| 	return 0; | ||||
| } | ||||
|  | ||||
|  | ||||
| /* Setup address, data_high:data_low into the L2 | ||||
|  * control registers and then issue command with correct cache way | ||||
|  */ | ||||
|   | ||||
| @@ -25,7 +25,6 @@ | ||||
| #define  G_SMRAME	(1 << 3) | ||||
| #define  C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0)) | ||||
|  | ||||
|  | ||||
| /* On model_6fx, model_1067x and model_106cx SMRR functions slightly | ||||
|    differently. The MSR are at different location from the rest | ||||
|    and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */ | ||||
|   | ||||
| @@ -104,7 +104,6 @@ void speedstep_gen_pstates(sst_table_t *const table) | ||||
| 	/* Gather speedstep limits. */ | ||||
| 	speedstep_get_limits(¶ms); | ||||
|  | ||||
|  | ||||
| 	/*\ First, find the number of normal states: \*/ | ||||
|  | ||||
| 	/* Calculate with doubled values to work | ||||
| @@ -130,7 +129,6 @@ void speedstep_gen_pstates(sst_table_t *const table) | ||||
| 	if (states < 2) /* Report at least two normal states. */ | ||||
| 		states = 2; | ||||
|  | ||||
|  | ||||
| 	/*\ Now, fill the table: \*/ | ||||
|  | ||||
| 	table->num_states = 0; | ||||
|   | ||||
| @@ -106,7 +106,6 @@ struct saved_msr { | ||||
| 	uint32_t hi; | ||||
| } __packed; | ||||
|  | ||||
|  | ||||
| /* The sipi vector rmodule is included in the ramstage using 'objdump -B'. */ | ||||
| extern char _binary_sipi_vector_start[]; | ||||
|  | ||||
|   | ||||
| @@ -69,7 +69,6 @@ static void smi_set_eos(void) | ||||
| 	southbridge_smi_set_eos(); | ||||
| } | ||||
|  | ||||
|  | ||||
| static u32 pci_orig; | ||||
|  | ||||
| /** | ||||
| @@ -88,7 +87,6 @@ static void smi_restore_pci_address(void) | ||||
| 	outl(pci_orig, 0xcf8); | ||||
| } | ||||
|  | ||||
|  | ||||
| static const struct smm_runtime *smm_runtime; | ||||
|  | ||||
| struct global_nvs *gnvs; | ||||
|   | ||||
| @@ -590,7 +590,6 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) | ||||
| 		fxsave_area = NULL; | ||||
| 	} | ||||
|  | ||||
|  | ||||
| 	handler_size = rmodule_memory_size(&smm_mod); | ||||
| 	base -= handler_size; | ||||
| 	total_size += handler_size; | ||||
|   | ||||
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