{cpu/nb}/amd/family15tn: Remove platform
This platform use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I18eb1c1ccad16980a4e57318dec411b82c45b25a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69116 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans
@@ -2,7 +2,6 @@
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config CPU_AMD_AGESA
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bool
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default y if CPU_AMD_AGESA_FAMILY15_TN
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default y if CPU_AMD_AGESA_FAMILY16_KB
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default n
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select ARCH_X86
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@@ -46,5 +45,4 @@ config ENABLE_MRC_CACHE
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endif # CPU_AMD_AGESA
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source "src/cpu/amd/agesa/family15tn/Kconfig"
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source "src/cpu/amd/agesa/family16kb/Kconfig"
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@@ -1,6 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0-only
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
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romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
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@@ -1,7 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config CPU_AMD_AGESA_FAMILY15_TN
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bool
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select IDS_OPTIONS_HOOKED_UP
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select SMM_ASEG
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select X86_AMD_FIXED_MTRRS
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@@ -1,12 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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romstage-y += fixme.c
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ramstage-y += fixme.c
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ramstage-y += chip_name.c
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ramstage-y += model_15_init.c
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smm-y += udelay.c
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subdirs-y += ../../mtrr
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subdirs-$(CONFIG_SMM_LEGACY_ASEG) += ../../smm
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@@ -1,48 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Processor Object
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*
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*/
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Scope (\_SB) { /* define processor scope */
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Device (P000) {
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Name(_HID, "ACPI0007")
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Name(_UID, 0)
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}
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Device (P001) {
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Name(_HID, "ACPI0007")
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Name(_UID, 1)
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}
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Device (P002) {
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Name(_HID, "ACPI0007")
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Name(_UID, 2)
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}
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Device (P003) {
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Name(_HID, "ACPI0007")
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Name(_UID, 3)
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}
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Device (P004) {
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Name(_HID, "ACPI0007")
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Name(_UID, 4)
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}
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Device (P005) {
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Name(_HID, "ACPI0007")
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Name(_UID, 5)
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}
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Device (P006) {
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Name(_HID, "ACPI0007")
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Name(_UID, 6)
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}
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Device (P007) {
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Name(_HID, "ACPI0007")
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Name(_UID, 7)
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}
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} /* End _SB scope */
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@@ -1,7 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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struct chip_operations cpu_amd_agesa_family15tn_ops = {
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CHIP_NAME("AMD CPU Family 15h Model 10h-1Fh")
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};
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@@ -1,51 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/hpet.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <AGESA.h>
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#include <amdlib.h>
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void amd_initcpuio(void)
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{
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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/* Enable legacy video routing: D18F1xF4 VGA Enable */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
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PciData = 1;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* The platform BIOS needs to ensure the memory ranges of Hudson legacy
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* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
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* set to non-posted regions.
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*/
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
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PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
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PciData |= 1 << 7; /* set NP (non-posted) bit */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
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PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Map the remaining PCI hole as posted MMIO */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
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PciData = 0x00FECF00; /* last address before non-posted range */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
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PciData = (UINT32)MsrReg;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Send all IO (0000-FFFF) to southbridge. */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
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PciData = 0x0000F000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
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PciData = 0x00000003;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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}
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@@ -1,114 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <amdblocks/cpu.h>
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#include <amdblocks/smm.h>
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#include <console/console.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <device/device.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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static void model_15_init(struct device *dev)
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{
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printk(BIOS_DEBUG, "Model 15 Init.\n");
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msr_t msr;
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int msrno;
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unsigned int cpu_idx;
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#if CONFIG(LOGICAL_CPUS)
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u32 siblings;
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#endif
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/*
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* AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
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* by coreboot.
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*/
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disable_cache();
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/* Enable access to AMD RdDram and WrDram extension bits */
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msr = rdmsr(SYSCFG_MSR);
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msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
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msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
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wrmsr(SYSCFG_MSR, msr);
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// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
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msr.lo = msr.hi = 0;
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wrmsr(MTRR_FIX_16K_A0000, msr);
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msr.lo = msr.hi = 0x1e1e1e1e;
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wrmsr(MTRR_FIX_64K_00000, msr);
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wrmsr(MTRR_FIX_16K_80000, msr);
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for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
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wrmsr(msrno, msr);
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msr = rdmsr(SYSCFG_MSR);
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msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
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msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
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wrmsr(SYSCFG_MSR, msr);
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if (acpi_is_wakeup_s3())
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restore_mtrr();
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x86_mtrr_check();
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enable_cache();
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/* zero the machine check error status registers */
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mca_clear_status();
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#if CONFIG(LOGICAL_CPUS)
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siblings = get_cpu_count() - 1; // minus BSP
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if (siblings > 0) {
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msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
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msr.lo |= 1 << 28;
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wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
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msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
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msr.hi |= 1 << (33 - 32);
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wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
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}
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printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
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#endif
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/* DisableCf8ExtCfg */
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msr = rdmsr(NB_CFG_MSR);
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msr.hi &= ~(1 << (46 - 32));
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wrmsr(NB_CFG_MSR, msr);
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if (CONFIG(HAVE_SMI_HANDLER)) {
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cpu_idx = cpu_info()->index;
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printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
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/* Set SMM base address for this CPU */
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msr = rdmsr(SMM_BASE_MSR);
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msr.lo = SMM_BASE - (cpu_idx * 0x400);
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wrmsr(SMM_BASE_MSR, msr);
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/* Enable the SMM memory window */
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msr = rdmsr(SMM_MASK_MSR);
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msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
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wrmsr(SMM_MASK_MSR, msr);
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}
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/* Write protect SMM space with SMMLOCK. */
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lock_smm();
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}
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static struct device_operations cpu_dev_ops = {
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.init = model_15_init,
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};
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static const struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, 0x610f00 }, /* TN-A0 */
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{ X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 (Richland) */
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{ 0, 0 },
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};
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static const struct cpu_driver model_15 __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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@@ -1,45 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* udelay() implementation for SMI handlers
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* This is neat in that it never writes to hardware registers, and thus does
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* not modify the state of the hardware while servicing SMIs.
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*/
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#include <cpu/x86/msr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/x86/tsc.h>
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#include <delay.h>
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#include <stdint.h>
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void udelay(uint32_t us)
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{
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uint8_t fid, did, pstate_idx;
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uint64_t tsc_clock, tsc_start, tsc_now, tsc_wait_ticks;
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msr_t msr;
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const uint64_t tsc_base = 100000000;
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/* Get initial timestamp before we do the math */
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tsc_start = rdtscll();
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/* Get the P-state. This determines which MSR to read */
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msr = rdmsr(PS_STS_REG);
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pstate_idx = msr.lo & 0x07;
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/* Get FID and VID for current P-State */
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msr = rdmsr(PSTATE_0_MSR + pstate_idx);
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/* Extract the FID and VID values */
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fid = msr.lo & 0x3f;
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did = (msr.lo >> 6) & 0x7;
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/* Calculate the CPU clock (from base freq of 100MHz) */
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tsc_clock = tsc_base * (fid + 0x10) / (1 << did);
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/* Now go on and wait */
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tsc_wait_ticks = (tsc_clock / 1000000) * us;
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do {
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tsc_now = rdtscll();
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} while (tsc_now - tsc_wait_ticks < tsc_start);
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}
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@@ -136,10 +136,6 @@ untampered_lapic:
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/* This is an ugly hack, and we should find a way to read the CPU index
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* without relying on the LAPIC ID.
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*/
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#if CONFIG(CPU_AMD_AGESA_FAMILY15_TN)
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/* LAPIC IDs start from 0x10; map that to the proper core index */
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subl $0x10, %ecx
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#endif
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/* calculate stack offset by multiplying the APIC ID
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* by 1024 (0x400), and save that offset in ebp.
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@@ -2,7 +2,6 @@
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ifeq ($(CONFIG_NORTHBRIDGE_AMD_AGESA),y)
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subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn
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subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb
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endif
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@@ -1,20 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
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bool
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select LEGACY_SMP_INIT
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select RESOURCE_ALLOCATOR_V3
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if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x100000
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config ECAM_MMCONF_BASE_ADDRESS
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default 0xF8000000
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config ECAM_MMCONF_BUS_NUMBER
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default 64
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endif # NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
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@@ -1,10 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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romstage-y += dimmSpd.c
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ramstage-y += iommu.c
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ramstage-y += northbridge.c
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ramstage-y += acpi_tables.c
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romstage-y += state_machine.c
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ramstage-y += state_machine.c
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@@ -1,87 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
|
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/* Note: Only need HID on Primary Bus */
|
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External (TOM1)
|
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External (TOM2)
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Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */
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/* Describe the Northbridge devices */
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Method (_BBN, 0, NotSerialized)
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{
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Return (Zero)
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}
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Method (_STA, 0, NotSerialized)
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{
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Return (0x0B)
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}
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||||
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Method (_PRT, 0, NotSerialized)
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{
|
||||
If (PICM)
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{
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Return (APR0)
|
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}
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||||
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||||
Return (PR0)
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||||
}
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||||
|
||||
Device(AMRT) {
|
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Name(_ADR, 0x00000000)
|
||||
} /* end AMRT */
|
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|
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/* Dev2 is also an external GFX bridge */
|
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Device(PBR2) {
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Name(_ADR, 0x00020000)
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||||
Name(_PRW, Package() {0x18, 4})
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||||
Method(_PRT,0) {
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If(PICM) { Return(APS2) } /* APIC mode */
|
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Return (PS2) /* PIC Mode */
|
||||
} /* end _PRT */
|
||||
} /* end PBR2 */
|
||||
|
||||
/* Dev4 GPP0 Root Port Bridge */
|
||||
Device(PBR4) {
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||||
Name(_ADR, 0x00040000)
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||||
Name(_PRW, Package() {0x18, 4})
|
||||
Method(_PRT,0) {
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||||
If(PICM) { Return(APS4) } /* APIC mode */
|
||||
Return (PS4) /* PIC Mode */
|
||||
} /* end _PRT */
|
||||
} /* end PBR4 */
|
||||
|
||||
/* Dev5 GPP1 Root Port Bridge */
|
||||
Device(PBR5) {
|
||||
Name(_ADR, 0x00050000)
|
||||
Name(_PRW, Package() {0x18, 4})
|
||||
Method(_PRT,0) {
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If(PICM) { Return(APS5) } /* APIC mode */
|
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Return (PS5) /* PIC Mode */
|
||||
} /* end _PRT */
|
||||
} /* end PBR5 */
|
||||
|
||||
/* Dev6 GPP2 Root Port Bridge */
|
||||
Device(PBR6) {
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||||
Name(_ADR, 0x00060000)
|
||||
Name(_PRW, Package() {0x18, 4})
|
||||
Method(_PRT,0) {
|
||||
If(PICM) { Return(APS6) } /* APIC mode */
|
||||
Return (PS6) /* PIC Mode */
|
||||
} /* end _PRT */
|
||||
} /* end PBR6 */
|
||||
|
||||
/* The onboard EtherNet chip */
|
||||
Device(PBR7) {
|
||||
Name(_ADR, 0x00070000)
|
||||
Name(_PRW, Package() {0x18, 4})
|
||||
Method(_PRT,0) {
|
||||
If(PICM) { Return(APS7) } /* APIC mode */
|
||||
Return (PS7) /* PIC Mode */
|
||||
} /* end _PRT */
|
||||
} /* end PBR7 */
|
||||
|
||||
Device(K10M) {
|
||||
Name (_ADR, 0x00180003)
|
||||
#include <soc/amd/common/acpi/thermal_zone.asl>
|
||||
}
|
||||
@@ -1,29 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write Hudson IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS,
|
||||
IO_APIC_ADDR, 0);
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xF);
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
@@ -1,11 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _NB_AGESA_CHIP_H_
|
||||
#define _NB_AGESA_CHIP_H_
|
||||
|
||||
struct northbridge_amd_agesa_family15tn_config
|
||||
{
|
||||
u8 spdAddrLookup[2][2][4];
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -1,46 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/pci_def.h>
|
||||
#include <device/device.h>
|
||||
|
||||
/* warning: Porting.h includes an open #pragma pack(1) */
|
||||
#include <Porting.h>
|
||||
#include <AGESA.h>
|
||||
#include "chip.h"
|
||||
|
||||
#include <northbridge/amd/agesa/dimmSpd.h>
|
||||
|
||||
/**
|
||||
* Gets the SMBus address for an SPD from the array in devicetree.cb
|
||||
* then read the SPD into the supplied buffer.
|
||||
*/
|
||||
AGESA_STATUS AmdMemoryReadSPD(UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info)
|
||||
{
|
||||
UINT8 spdAddress;
|
||||
|
||||
DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2);
|
||||
if (dev == NULL)
|
||||
return AGESA_ERROR;
|
||||
|
||||
DEVTREE_CONST struct northbridge_amd_agesa_family15tn_config *config = dev->chip_info;
|
||||
if (config == NULL)
|
||||
return AGESA_ERROR;
|
||||
|
||||
if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup))
|
||||
return AGESA_ERROR;
|
||||
if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0]))
|
||||
return AGESA_ERROR;
|
||||
if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0]))
|
||||
return AGESA_ERROR;
|
||||
|
||||
spdAddress = config->spdAddrLookup
|
||||
[info->SocketId][info->MemChannelId][info->DimmId];
|
||||
|
||||
if (spdAddress == 0)
|
||||
return AGESA_ERROR;
|
||||
|
||||
int err = hudson_readSpd(spdAddress, (void *)info->Buffer, DDR3_SPD_SIZE);
|
||||
if (err)
|
||||
return AGESA_ERROR;
|
||||
return AGESA_SUCCESS;
|
||||
}
|
||||
@@ -1,50 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <lib.h>
|
||||
|
||||
static void iommu_read_resources(struct device *dev)
|
||||
{
|
||||
struct resource *res;
|
||||
|
||||
/* Get the normal pci resources of this device */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* IOMMU MMIO registers */
|
||||
res = new_resource(dev, 0x44);
|
||||
res->size = 512 * 1024;
|
||||
res->align = log2(res->size);
|
||||
res->gran = log2(res->size);
|
||||
res->limit = 0xffffffff; /* 4G */
|
||||
res->flags = IORESOURCE_MEM;
|
||||
}
|
||||
|
||||
static void iommu_set_resources(struct device *dev)
|
||||
{
|
||||
struct resource *res;
|
||||
|
||||
pci_dev_set_resources(dev);
|
||||
|
||||
res = find_resource(dev, 0x44);
|
||||
/* Remember this resource has been stored */
|
||||
res->flags |= IORESOURCE_STORED;
|
||||
/* For now, do only 32-bit space allocation */
|
||||
pci_write_config32(dev, 0x48, 0x0);
|
||||
pci_write_config32(dev, 0x44, res->base | (1 << 0));
|
||||
}
|
||||
|
||||
static struct device_operations iommu_ops = {
|
||||
.read_resources = iommu_read_resources,
|
||||
.set_resources = iommu_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.ops_pci = &pci_dev_ops_pci,
|
||||
};
|
||||
|
||||
static const struct pci_driver iommu_driver __pci_driver = {
|
||||
.ops = &iommu_ops,
|
||||
.vendor = PCI_VID_AMD,
|
||||
.device = PCI_DID_AMD_15H_MODEL_101F_NB_IOMMU,
|
||||
};
|
||||
@@ -1,736 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <acpi/acpi.h>
|
||||
#include <acpi/acpigen.h>
|
||||
#include <stdint.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <lib.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <AGESA.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <cpu/amd/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <Porting.h>
|
||||
#include <Options.h>
|
||||
#include <Topology.h>
|
||||
#include <northbridge/amd/nb_common.h>
|
||||
#include <northbridge/amd/agesa/state_machine.h>
|
||||
#include <northbridge/amd/agesa/agesa_helper.h>
|
||||
|
||||
#define MAX_NODE_NUMS MAX_NODES
|
||||
|
||||
static unsigned int node_nums;
|
||||
static unsigned int sblink;
|
||||
static struct device *__f0_dev[MAX_NODE_NUMS];
|
||||
static struct device *__f1_dev[MAX_NODE_NUMS];
|
||||
static struct device *__f2_dev[MAX_NODE_NUMS];
|
||||
static struct device *__f4_dev[MAX_NODE_NUMS];
|
||||
static unsigned int fx_devs = 0;
|
||||
|
||||
static struct device *get_node_pci(u32 nodeid, u32 fn)
|
||||
{
|
||||
return pcidev_on_root(DEV_CDB + nodeid, fn);
|
||||
}
|
||||
|
||||
static void get_fx_devs(void)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < MAX_NODE_NUMS; i++) {
|
||||
__f0_dev[i] = get_node_pci(i, 0);
|
||||
__f1_dev[i] = get_node_pci(i, 1);
|
||||
__f2_dev[i] = get_node_pci(i, 2);
|
||||
__f4_dev[i] = get_node_pci(i, 4);
|
||||
if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
|
||||
fx_devs = i + 1;
|
||||
}
|
||||
if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
|
||||
die("Cannot find 0:0x18.[0|1]\n");
|
||||
}
|
||||
printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
|
||||
}
|
||||
|
||||
static u32 f1_read_config32(unsigned int reg)
|
||||
{
|
||||
if (fx_devs == 0)
|
||||
get_fx_devs();
|
||||
return pci_read_config32(__f1_dev[0], reg);
|
||||
}
|
||||
|
||||
static void f1_write_config32(unsigned int reg, u32 value)
|
||||
{
|
||||
int i;
|
||||
if (fx_devs == 0)
|
||||
get_fx_devs();
|
||||
for (i = 0; i < fx_devs; i++) {
|
||||
struct device *dev;
|
||||
dev = __f1_dev[i];
|
||||
if (dev && dev->enabled) {
|
||||
pci_write_config32(dev, reg, value);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
if (fx_devs == 0)
|
||||
get_fx_devs();
|
||||
|
||||
|
||||
temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16]
|
||||
if (!(temp & 1))
|
||||
return 0; // this memory range is not enabled
|
||||
/*
|
||||
* BKDG: {DramBase[47:24], 00_0000h} <= address[47:0] so shift left by 8 bits
|
||||
* for physical address and the convert to KiB by shifting 10 bits left
|
||||
*/
|
||||
*basek = ((temp & 0xffff0000)) >> (10 - 8);
|
||||
/* Now high bits [47:40] */
|
||||
temp = pci_read_config32(__f1_dev[nodeid], 0x140 + (nodeid << 3)); //[47:40] at [7:0]
|
||||
*basek = *basek | ((resource_t)temp << (40 - 10));
|
||||
/*
|
||||
* BKDG address[39:0] <= {DramLimit[47:24], FF_FFFFh} converted as above but
|
||||
* ORed with 0xffff to get real limit before shifting.
|
||||
*/
|
||||
temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16]
|
||||
*limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8);
|
||||
/* Now high bits [47:40] */
|
||||
temp = pci_read_config32(__f1_dev[nodeid], 0x144 + (nodeid << 3)); //[47:40] at [7:0]
|
||||
*limitk = *limitk | ((resource_t)temp << (40 - 10));
|
||||
*limitk += 1; // round up last byte
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static u32 amdfam15_nodeid(struct device *dev)
|
||||
{
|
||||
return (dev->path.pci.devfn >> 3) - DEV_CDB;
|
||||
}
|
||||
|
||||
static void set_vga_enable_reg(u32 nodeid, u32 linkn)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = 1 | (nodeid << 4) | (linkn << 12);
|
||||
/* it will routing
|
||||
* (1)mmio 0xa0000:0xbffff
|
||||
* (2)io 0x3b0:0x3bb, 0x3c0:0x3df
|
||||
*/
|
||||
f1_write_config32(0xf4, val);
|
||||
|
||||
}
|
||||
|
||||
static void nb_read_resources(struct device *dev)
|
||||
{
|
||||
/*
|
||||
* This MMCONF resource must be reserved in the PCI domain.
|
||||
* It is not honored by the coreboot resource allocator if it is in
|
||||
* the CPU_CLUSTER.
|
||||
*/
|
||||
mmconf_resource(dev, MMIO_CONF_BASE);
|
||||
|
||||
/* There should be no BAR on this device. */
|
||||
}
|
||||
|
||||
/**
|
||||
* I tried to reuse the resource allocation code in set_resource()
|
||||
* but it is too difficult to deal with the resource allocation magic.
|
||||
*/
|
||||
|
||||
static void create_vga_resource(struct device *dev, unsigned int nodeid)
|
||||
{
|
||||
struct bus *link;
|
||||
|
||||
/* find out which link the VGA card is connected,
|
||||
* we only deal with the 'first' vga card */
|
||||
for (link = dev->link_list; link; link = link->next) {
|
||||
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
|
||||
#if CONFIG(MULTIPLE_VGA_ADAPTERS)
|
||||
extern struct device *vga_pri; // the primary vga device, defined in device.c
|
||||
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
|
||||
link->secondary, link->subordinate);
|
||||
/* We need to make sure the vga_pri is under the link */
|
||||
if ((vga_pri->bus->secondary >= link->secondary) &&
|
||||
(vga_pri->bus->secondary <= link->subordinate))
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* no VGA card installed */
|
||||
if (link == NULL)
|
||||
return;
|
||||
|
||||
printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink);
|
||||
set_vga_enable_reg(nodeid, sblink);
|
||||
}
|
||||
|
||||
static void nb_set_resources(struct device *dev)
|
||||
{
|
||||
unsigned int nodeid;
|
||||
|
||||
/* Find the nodeid */
|
||||
nodeid = amdfam15_nodeid(dev);
|
||||
|
||||
create_vga_resource(dev, nodeid); //TODO: do we need this?
|
||||
}
|
||||
|
||||
static unsigned long acpi_fill_hest(acpi_hest_t *hest)
|
||||
{
|
||||
void *addr, *current;
|
||||
|
||||
/* Skip the HEST header. */
|
||||
current = (void *)(hest + 1);
|
||||
|
||||
addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
|
||||
if (addr != NULL)
|
||||
current += acpi_create_hest_error_source(hest, current, 0,
|
||||
addr + 2, *(UINT16 *)addr - 2);
|
||||
|
||||
addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
|
||||
if (addr != NULL)
|
||||
current += acpi_create_hest_error_source(hest, current, 1,
|
||||
addr + 2, *(UINT16 *)addr - 2);
|
||||
|
||||
return (unsigned long)current;
|
||||
}
|
||||
|
||||
static void northbridge_fill_ssdt_generator(const struct device *device)
|
||||
{
|
||||
msr_t msr;
|
||||
char pscope[] = "\\_SB.PCI0";
|
||||
|
||||
acpigen_write_scope(pscope);
|
||||
msr = rdmsr(TOP_MEM);
|
||||
acpigen_write_name_dword("TOM1", msr.lo);
|
||||
msr = rdmsr(TOP_MEM2);
|
||||
/*
|
||||
* Since XP only implements parts of ACPI 2.0, we can't use a qword
|
||||
* here.
|
||||
* See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
|
||||
* slide 22ff.
|
||||
* Shift value right by 20 bit to make it fit into 32bit,
|
||||
* giving us 1MB granularity and a limit of almost 4Exabyte of memory.
|
||||
*/
|
||||
acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
|
||||
acpigen_pop_len();
|
||||
}
|
||||
|
||||
static void patch_ssdt_processor_scope(acpi_header_t *ssdt)
|
||||
{
|
||||
unsigned int len = ssdt->length - sizeof(acpi_header_t);
|
||||
unsigned int i;
|
||||
|
||||
for (i = sizeof(acpi_header_t); i < len; i++) {
|
||||
/* Search for _PR_ scope and replace it with _SB_ */
|
||||
if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f)
|
||||
*(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f;
|
||||
}
|
||||
/* Recalculate checksum */
|
||||
ssdt->checksum = 0;
|
||||
ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
|
||||
}
|
||||
|
||||
static unsigned long agesa_write_acpi_tables(const struct device *device,
|
||||
unsigned long current,
|
||||
acpi_rsdp_t *rsdp)
|
||||
{
|
||||
acpi_srat_t *srat;
|
||||
acpi_slit_t *slit;
|
||||
acpi_header_t *ssdt;
|
||||
acpi_header_t *alib;
|
||||
acpi_header_t *ivrs;
|
||||
acpi_hest_t *hest;
|
||||
|
||||
/* HEST */
|
||||
current = ALIGN_UP(current, 8);
|
||||
hest = (acpi_hest_t *)current;
|
||||
acpi_write_hest(hest, acpi_fill_hest);
|
||||
acpi_add_table(rsdp, hest);
|
||||
current += hest->header.length;
|
||||
|
||||
current = ALIGN_UP(current, 8);
|
||||
printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current);
|
||||
ivrs = agesawrapper_getlateinitptr(PICK_IVRS);
|
||||
if (ivrs != NULL) {
|
||||
memcpy((void *)current, ivrs, ivrs->length);
|
||||
ivrs = (acpi_header_t *)current;
|
||||
current += ivrs->length;
|
||||
acpi_add_table(rsdp, ivrs);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n");
|
||||
}
|
||||
|
||||
/* SRAT */
|
||||
current = ALIGN_UP(current, 8);
|
||||
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
|
||||
srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT);
|
||||
if (srat != NULL) {
|
||||
memcpy((void *)current, srat, srat->header.length);
|
||||
srat = (acpi_srat_t *)current;
|
||||
current += srat->header.length;
|
||||
acpi_add_table(rsdp, srat);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n");
|
||||
}
|
||||
|
||||
/* SLIT */
|
||||
current = ALIGN_UP(current, 8);
|
||||
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
|
||||
slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT);
|
||||
if (slit != NULL) {
|
||||
memcpy((void *)current, slit, slit->header.length);
|
||||
slit = (acpi_slit_t *)current;
|
||||
current += slit->header.length;
|
||||
acpi_add_table(rsdp, slit);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n");
|
||||
}
|
||||
|
||||
/* ALIB */
|
||||
current = ALIGN_UP(current, 16);
|
||||
printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
|
||||
alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB);
|
||||
if (alib != NULL) {
|
||||
memcpy((void *)current, alib, alib->length);
|
||||
alib = (acpi_header_t *)current;
|
||||
current += alib->length;
|
||||
acpi_add_table(rsdp, (void *)alib);
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n");
|
||||
}
|
||||
|
||||
/* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */
|
||||
/* SSDT */
|
||||
current = ALIGN_UP(current, 16);
|
||||
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
|
||||
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE);
|
||||
if (ssdt != NULL) {
|
||||
patch_ssdt_processor_scope(ssdt);
|
||||
memcpy((void *)current, ssdt, ssdt->length);
|
||||
ssdt = (acpi_header_t *)current;
|
||||
current += ssdt->length;
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n");
|
||||
}
|
||||
acpi_add_table(rsdp, ssdt);
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
static struct device_operations northbridge_operations = {
|
||||
.read_resources = nb_read_resources,
|
||||
.set_resources = nb_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.acpi_fill_ssdt = northbridge_fill_ssdt_generator,
|
||||
.write_acpi_tables = agesa_write_acpi_tables,
|
||||
};
|
||||
|
||||
static const struct pci_driver family15_northbridge __pci_driver = {
|
||||
.ops = &northbridge_operations,
|
||||
.vendor = PCI_VID_AMD,
|
||||
.device = PCI_DID_AMD_15H_MODEL_101F_NB_HT,
|
||||
};
|
||||
|
||||
static const struct pci_driver family10_northbridge __pci_driver = {
|
||||
.ops = &northbridge_operations,
|
||||
.vendor = PCI_VID_AMD,
|
||||
.device = PCI_DID_AMD_10H_NB_HT,
|
||||
};
|
||||
|
||||
struct chip_operations northbridge_amd_agesa_family15tn_ops = {
|
||||
CHIP_NAME("AMD FAM15 Northbridge")
|
||||
.enable_dev = 0,
|
||||
};
|
||||
|
||||
static void domain_read_resources(struct device *dev)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
/* Find the already assigned resource pairs */
|
||||
get_fx_devs();
|
||||
for (reg = 0x80; reg <= 0xd8; reg += 0x08) {
|
||||
u32 base, limit;
|
||||
base = f1_read_config32(reg);
|
||||
limit = f1_read_config32(reg + 0x04);
|
||||
/* Is this register allocated? */
|
||||
if ((base & 3) != 0) {
|
||||
unsigned int nodeid, reg_link;
|
||||
struct device *reg_dev;
|
||||
if (reg < 0xc0) { // mmio
|
||||
nodeid = (limit & 0xf) + (base & 0x30);
|
||||
} else { // io
|
||||
nodeid = (limit & 0xf) + ((base >> 4) & 0x30);
|
||||
}
|
||||
reg_link = (limit >> 4) & 7;
|
||||
reg_dev = __f0_dev[nodeid];
|
||||
if (reg_dev) {
|
||||
/* Reserve the resource */
|
||||
struct resource *res;
|
||||
res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
|
||||
if (res) {
|
||||
res->flags = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
/* FIXME: do we need to check extend conf space?
|
||||
I don't believe that much preset value */
|
||||
|
||||
pci_domain_read_resources(dev);
|
||||
}
|
||||
|
||||
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
|
||||
struct hw_mem_hole_info {
|
||||
unsigned int hole_startk;
|
||||
int node_id;
|
||||
};
|
||||
static struct hw_mem_hole_info get_hw_mem_hole_info(void)
|
||||
{
|
||||
struct hw_mem_hole_info mem_hole;
|
||||
int i;
|
||||
mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
|
||||
mem_hole.node_id = -1;
|
||||
for (i = 0; i < node_nums; i++) {
|
||||
resource_t basek, limitk;
|
||||
u32 hole;
|
||||
if (!get_dram_base_limit(i, &basek, &limitk))
|
||||
continue; // no memory on this node
|
||||
hole = pci_read_config32(__f1_dev[i], 0xf0);
|
||||
if (hole & 1) { // we find the hole
|
||||
mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
|
||||
mem_hole.node_id = i; // record the node No with hole
|
||||
break; // only one hole
|
||||
}
|
||||
}
|
||||
|
||||
/* We need to double check if there is special set on base reg and limit reg
|
||||
* are not continuous instead of hole, it will find out its hole_startk.
|
||||
*/
|
||||
if (mem_hole.node_id == -1) {
|
||||
resource_t limitk_pri = 0;
|
||||
for (i = 0; i < node_nums; i++) {
|
||||
resource_t base_k, limit_k;
|
||||
if (!get_dram_base_limit(i, &base_k, &limit_k))
|
||||
continue; // no memory on this node
|
||||
if (base_k > 4 * 1024 * 1024) break; // don't need to go to check
|
||||
if (limitk_pri != base_k) { // we find the hole
|
||||
mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G
|
||||
mem_hole.node_id = i;
|
||||
break; //only one hole
|
||||
}
|
||||
limitk_pri = limit_k;
|
||||
}
|
||||
}
|
||||
return mem_hole;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void domain_set_resources(struct device *dev)
|
||||
{
|
||||
unsigned long mmio_basek;
|
||||
u32 pci_tolm;
|
||||
int i, idx;
|
||||
struct bus *link;
|
||||
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
|
||||
struct hw_mem_hole_info mem_hole;
|
||||
#endif
|
||||
|
||||
pci_tolm = 0xffffffffUL;
|
||||
for (link = dev->link_list; link; link = link->next) {
|
||||
pci_tolm = find_pci_tolm(link);
|
||||
}
|
||||
|
||||
// FIXME handle interleaved nodes. If you fix this here, please fix
|
||||
// amdk8, too.
|
||||
mmio_basek = pci_tolm >> 10;
|
||||
/* Round mmio_basek to something the processor can support */
|
||||
mmio_basek &= ~((1 << 6) - 1);
|
||||
|
||||
// FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
|
||||
// MMIO hole. If you fix this here, please fix amdk8, too.
|
||||
/* Round the mmio hole to 64M */
|
||||
mmio_basek &= ~((64 * 1024) - 1);
|
||||
|
||||
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
|
||||
/* if the hw mem hole is already set in raminit stage, here we will compare
|
||||
* mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
|
||||
* use hole_basek as mmio_basek and we don't need to reset hole.
|
||||
* otherwise We reset the hole to the mmio_basek
|
||||
*/
|
||||
|
||||
mem_hole = get_hw_mem_hole_info();
|
||||
|
||||
// Use hole_basek as mmio_basek, and we don't need to reset hole anymore
|
||||
if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk))
|
||||
mmio_basek = mem_hole.hole_startk;
|
||||
#endif
|
||||
|
||||
idx = 0x10;
|
||||
for (i = 0; i < node_nums; i++) {
|
||||
resource_t basek, limitk, sizek; // 4 1T
|
||||
|
||||
if (!get_dram_base_limit(i, &basek, &limitk))
|
||||
continue; // no memory on this node
|
||||
|
||||
sizek = limitk - basek;
|
||||
|
||||
/* See if we need a hole from 0xa0000 (640K) to 0xbffff (768K) */
|
||||
if (basek < 640 && sizek > 768) {
|
||||
ram_resource_kb(dev, (idx | i), basek, 640 - basek);
|
||||
idx += 0x10;
|
||||
basek = 768;
|
||||
sizek = limitk - basek;
|
||||
|
||||
}
|
||||
|
||||
/* split the region to accommodate pci memory space */
|
||||
if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) {
|
||||
if (basek <= mmio_basek) {
|
||||
unsigned int pre_sizek;
|
||||
pre_sizek = mmio_basek - basek;
|
||||
if (pre_sizek > 0) {
|
||||
ram_resource_kb(dev, (idx | i), basek, pre_sizek);
|
||||
idx += 0x10;
|
||||
sizek -= pre_sizek;
|
||||
}
|
||||
basek = mmio_basek;
|
||||
}
|
||||
if ((basek + sizek) <= 4 * 1024 * 1024) {
|
||||
sizek = 0;
|
||||
}
|
||||
else {
|
||||
uint64_t topmem2 = amd_topmem2();
|
||||
basek = 4 * 1024 * 1024;
|
||||
sizek = topmem2 / 1024 - basek;
|
||||
}
|
||||
}
|
||||
|
||||
ram_resource_kb(dev, (idx | i), basek, sizek);
|
||||
idx += 0x10;
|
||||
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
|
||||
i, mmio_basek, basek, limitk);
|
||||
}
|
||||
|
||||
add_uma_resource_below_tolm(dev, 7);
|
||||
|
||||
for (link = dev->link_list; link; link = link->next) {
|
||||
if (link->children) {
|
||||
assign_resources(link);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static struct device_operations pci_domain_ops = {
|
||||
.read_resources = domain_read_resources,
|
||||
.set_resources = domain_set_resources,
|
||||
.scan_bus = pci_domain_scan_bus,
|
||||
};
|
||||
|
||||
static void sysconf_init(struct device *dev) // first node
|
||||
{
|
||||
sblink = (pci_read_config32(dev, 0x64) >> 8) & 7; // don't forget sublink1
|
||||
node_nums = ((pci_read_config32(dev, 0x60) >> 4) & 7) + 1; //NodeCnt[2:0]
|
||||
}
|
||||
|
||||
static void cpu_bus_scan(struct device *dev)
|
||||
{
|
||||
struct bus *cpu_bus;
|
||||
struct device *dev_mc;
|
||||
int i, j;
|
||||
int coreid_bits;
|
||||
int core_max = 0;
|
||||
unsigned int ApicIdCoreIdSize;
|
||||
unsigned int core_nums;
|
||||
int siblings = 0;
|
||||
unsigned int family;
|
||||
|
||||
dev_mc = pcidev_on_root(DEV_CDB, 0);
|
||||
if (!dev_mc) {
|
||||
printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB);
|
||||
die("");
|
||||
}
|
||||
sysconf_init(dev_mc);
|
||||
|
||||
/* Get Max Number of cores(MNC) */
|
||||
coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
|
||||
core_max = 1 << (coreid_bits & 0x000F); //mnc
|
||||
|
||||
ApicIdCoreIdSize = ((cpuid_ecx(0x80000008) >> 12) & 0xF);
|
||||
if (ApicIdCoreIdSize) {
|
||||
core_nums = (1 << ApicIdCoreIdSize) - 1;
|
||||
} else {
|
||||
core_nums = 3; //quad core
|
||||
}
|
||||
|
||||
/* Find which cpus are present */
|
||||
cpu_bus = dev->link_list;
|
||||
for (i = 0; i < node_nums; i++) {
|
||||
struct device *cdb_dev;
|
||||
unsigned int devn;
|
||||
struct bus *pbus;
|
||||
|
||||
devn = DEV_CDB + i;
|
||||
pbus = dev_mc->bus;
|
||||
|
||||
/* Find the cpu's pci device */
|
||||
cdb_dev = pcidev_on_root(devn, 0);
|
||||
if (!cdb_dev) {
|
||||
/* If I am probing things in a weird order
|
||||
* ensure all of the cpu's pci devices are found.
|
||||
*/
|
||||
int fn;
|
||||
for (fn = 0; fn <= 5; fn++) { //FBDIMM?
|
||||
cdb_dev = pci_probe_dev(NULL, pbus,
|
||||
PCI_DEVFN(devn, fn));
|
||||
}
|
||||
cdb_dev = pcidev_on_root(devn, 0);
|
||||
} else {
|
||||
/* Ok, We need to set the links for that device.
|
||||
* otherwise the device under it will not be scanned
|
||||
*/
|
||||
add_more_links(cdb_dev, 4);
|
||||
}
|
||||
|
||||
family = cpuid_eax(1);
|
||||
family = (family >> 20) & 0xFF;
|
||||
if (family == 1) { //f10
|
||||
u32 dword;
|
||||
cdb_dev = pcidev_on_root(devn, 3);
|
||||
dword = pci_read_config32(cdb_dev, 0xe8);
|
||||
siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12);
|
||||
} else if (family == 6) {//f15
|
||||
cdb_dev = pcidev_on_root(devn, 5);
|
||||
if (cdb_dev && cdb_dev->enabled) {
|
||||
siblings = pci_read_config32(cdb_dev, 0x84);
|
||||
siblings &= 0xFF;
|
||||
}
|
||||
} else {
|
||||
siblings = 0; //default one core
|
||||
}
|
||||
int enable_node = cdb_dev && cdb_dev->enabled;
|
||||
printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
|
||||
dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
|
||||
|
||||
for (j = 0; j <= siblings; j++) {
|
||||
extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
|
||||
u32 modules = TopologyConfiguration.PlatformNumberOfModules;
|
||||
u32 lapicid_start = 0;
|
||||
|
||||
/*
|
||||
* APIC ID calucation is tightly coupled with AGESA v5 code.
|
||||
* This calculation MUST match the assignment calculation done
|
||||
* in LocalApicInitializationAtEarly() function.
|
||||
* And reference GetLocalApicIdForCore()
|
||||
*
|
||||
* Apply APIC enumeration rules
|
||||
* For systems with >= 16 APICs, put the IO-APICs at 0..n and
|
||||
* put the local-APICs at m..z
|
||||
*
|
||||
* This is needed because many IO-APIC devices only have 4 bits
|
||||
* for their APIC id and therefore must reside at 0..15
|
||||
*/
|
||||
|
||||
u8 plat_num_io_apics = 3; /* FIXME */
|
||||
|
||||
if ((node_nums * core_max) + plat_num_io_apics >= 0x10) {
|
||||
lapicid_start = (plat_num_io_apics - 1) / core_max;
|
||||
lapicid_start = (lapicid_start + 1) * core_max;
|
||||
printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
|
||||
}
|
||||
u32 apic_id = (lapicid_start * (i / modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
|
||||
printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
|
||||
i, j, apic_id);
|
||||
|
||||
struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
|
||||
if (cpu)
|
||||
amd_cpu_topology(cpu, i, j);
|
||||
} //j
|
||||
}
|
||||
}
|
||||
|
||||
static void cpu_bus_init(struct device *dev)
|
||||
{
|
||||
initialize_cpus(dev->link_list);
|
||||
}
|
||||
|
||||
static struct device_operations cpu_bus_ops = {
|
||||
.read_resources = noop_read_resources,
|
||||
.set_resources = noop_set_resources,
|
||||
.init = cpu_bus_init,
|
||||
.scan_bus = cpu_bus_scan,
|
||||
};
|
||||
|
||||
static void root_complex_enable_dev(struct device *dev)
|
||||
{
|
||||
/* Set the operations if it is a special bus type */
|
||||
if (dev->path.type == DEVICE_PATH_DOMAIN) {
|
||||
dev->ops = &pci_domain_ops;
|
||||
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
|
||||
dev->ops = &cpu_bus_ops;
|
||||
}
|
||||
}
|
||||
|
||||
struct chip_operations northbridge_amd_agesa_family15tn_root_complex_ops = {
|
||||
CHIP_NAME("AMD Family 15tn Root Complex")
|
||||
.enable_dev = root_complex_enable_dev,
|
||||
};
|
||||
|
||||
/*********************************************************************
|
||||
* Change the vendor / device IDs to match the generic VBIOS header. *
|
||||
*********************************************************************/
|
||||
u32 map_oprom_vendev(u32 vendev)
|
||||
{
|
||||
u32 new_vendev = vendev;
|
||||
|
||||
switch (vendev) {
|
||||
case 0x10029900: /* AMD Radeon HD 7660G (Trinity) */
|
||||
case 0x10029901: /* AMD Radeon HD 7660D (Trinity) */
|
||||
case 0x10029903: /* AMD Radeon HD 7640G (Trinity) */
|
||||
case 0x10029904: /* AMD Radeon HD 7560D (Trinity) */
|
||||
case 0x10029907: /* AMD Radeon HD 7620G (Trinity) */
|
||||
case 0x10029908: /* AMD Radeon HD 7600G (Trinity) */
|
||||
case 0x1002990A: /* AMD Radeon HD 7500G (Trinity) */
|
||||
case 0x1002990B: /* AMD Radeon HD 8650G (Richland) */
|
||||
case 0x1002990C: /* AMD Radeon HD 8670D (Richland) */
|
||||
case 0x1002990D: /* AMD Radeon HD 8550G (Richland) */
|
||||
case 0x1002990E: /* AMD Radeon HD 8570D (Richland) */
|
||||
case 0x1002990F: /* AMD Radeon HD 8610G (Richland) */
|
||||
case 0x10029910: /* AMD Radeon HD 7660G (Trinity) */
|
||||
case 0x10029913: /* AMD Radeon HD 7640G (Trinity) */
|
||||
case 0x10029917: /* AMD Radeon HD 7620G (Trinity) */
|
||||
case 0x10029918: /* AMD Radeon HD 7600G (Trinity) */
|
||||
case 0x10029919: /* AMD Radeon HD 7500G (Trinity) */
|
||||
case 0x10029990: /* AMD Radeon HD 7520G (Trinity) */
|
||||
case 0x10029991: /* AMD Radeon HD 7540D (Trinity) */
|
||||
case 0x10029992: /* AMD Radeon HD 7420G (Trinity) */
|
||||
case 0x10029993: /* AMD Radeon HD 7480D (Trinity) */
|
||||
case 0x10029994: /* AMD Radeon HD 7400G (Trinity) */
|
||||
case 0x10029995: /* AMD Radeon HD 8450G (Richland) */
|
||||
case 0x10029996: /* AMD Radeon HD 8470D (Richland) */
|
||||
case 0x10029997: /* AMD Radeon HD 8350G (Richland) */
|
||||
case 0x10029998: /* AMD Radeon HD 8370D (Richland) */
|
||||
case 0x10029999: /* AMD Radeon HD 8510G (Richland) */
|
||||
case 0x1002999A: /* AMD Radeon HD 8410G (Richland) */
|
||||
case 0x1002999B: /* AMD Radeon HD 8310G (Richland) */
|
||||
case 0x1002999C: /* AMD Radeon HD 8650D (Richland) */
|
||||
case 0x1002999D: /* AMD Radeon HD 8550D (Richland) */
|
||||
case 0x100299A0: /* AMD Radeon HD 7520G (Trinity) */
|
||||
case 0x100299A2: /* AMD Radeon HD 7420G (Trinity) */
|
||||
case 0x100299A4: /* AMD Radeon HD 7400G (Trinity) */
|
||||
new_vendev = 0x10029901;
|
||||
break;
|
||||
}
|
||||
|
||||
return new_vendev;
|
||||
}
|
||||
@@ -1,53 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _AMD_FAM15TN_PCI_DEVS_H_
|
||||
#define _AMD_FAM15TN_PCI_DEVS_H_
|
||||
|
||||
#include <device/pci_def.h>
|
||||
|
||||
#define BUS0 0
|
||||
|
||||
/* GNB Root Complex */
|
||||
#define GNB_DEV 0x0
|
||||
#define GNB_FUNC 0
|
||||
#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC)
|
||||
|
||||
/* IOMMU */
|
||||
#define IOMMU_DEV 0x0
|
||||
#define IOMMU_FUNC 2
|
||||
#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC)
|
||||
|
||||
/* Graphics and Display */
|
||||
#define GFX_DEV 0x1
|
||||
#define GFX_FUNC 0
|
||||
#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC)
|
||||
|
||||
/* Integrated GPU Internal HDMI Audio Controller */
|
||||
#define ACTL_FUNC 1
|
||||
#define ACTL_DEVFN PCI_DEVFN(GFX_DEV, ACTL_FUNC)
|
||||
|
||||
/* PCIe Ports */
|
||||
#define NB_PCIE_PORT1_DEV 0x2
|
||||
#define NB_PCIE_PORT2_DEV 0x3
|
||||
#define NB_PCIE_PORT3_DEV 0x4
|
||||
#define NB_PCIE_PORT4_DEV 0x5
|
||||
#define NB_PCIE_PORT5_DEV 0x6
|
||||
#define NB_PCIE_PORT6_DEV 0x7
|
||||
#define NB_PCIE_PORT7_DEV 0x8
|
||||
#define NB_PCIE_FUNC 0
|
||||
#define NB_PCIE_PORT1_DEVID 0x1412
|
||||
#define NB_PCIE_PORT2_DEVID 0x1413
|
||||
#define NB_PCIE_PORT3_DEVID 0x1414
|
||||
#define NB_PCIE_PORT4_DEVID 0x1415
|
||||
#define NB_PCIE_PORT5_DEVID 0x1416
|
||||
#define NB_PCIE_PORT6_DEVID 0x1417
|
||||
#define NB_PCIE_PORT7_DEVID 0x1418
|
||||
#define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_PCIE_PORT1_DEV, NB_PCIE_FUNC)
|
||||
#define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_PCIE_PORT2_DEV, NB_PCIE_FUNC)
|
||||
#define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_PCIE_PORT3_DEV, NB_PCIE_FUNC)
|
||||
#define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_PCIE_PORT4_DEV, NB_PCIE_FUNC)
|
||||
#define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_PCIE_PORT5_DEV, NB_PCIE_FUNC)
|
||||
#define NB_PCIE_PORT6_DEVFN PCI_DEVFN(NB_PCIE_PORT6_DEV, NB_PCIE_FUNC)
|
||||
#define NB_PCIE_PORT7_DEVFN PCI_DEVFN(NB_PCIE_PORT7_DEV, NB_PCIE_FUNC)
|
||||
|
||||
#endif /* _AMD_FAM15TN_PCI_DEVS_H_ */
|
||||
@@ -1,73 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/biosram.h>
|
||||
|
||||
#include <Porting.h>
|
||||
#include <AGESA.h>
|
||||
#include <northbridge/amd/agesa/state_machine.h>
|
||||
#include <northbridge/amd/agesa/agesa_helper.h>
|
||||
|
||||
void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
|
||||
{
|
||||
}
|
||||
|
||||
void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early)
|
||||
{
|
||||
}
|
||||
|
||||
void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
|
||||
{
|
||||
Post->MemConfig.BottomIo = (UINT16)(MIN(0xE0000000,
|
||||
MAX(0x28000000, CONFIG_BOTTOMIO_POSITION)) >> 24) & 0xF8;
|
||||
}
|
||||
|
||||
void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
|
||||
{
|
||||
backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop);
|
||||
}
|
||||
|
||||
void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume)
|
||||
{
|
||||
OemInitResume(&Resume->S3DataBlock);
|
||||
}
|
||||
|
||||
void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume)
|
||||
{
|
||||
}
|
||||
|
||||
void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
|
||||
{
|
||||
EmptyHeap();
|
||||
}
|
||||
|
||||
void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
|
||||
{
|
||||
}
|
||||
|
||||
void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
|
||||
{
|
||||
OemS3LateRestore(&S3Late->S3DataBlock);
|
||||
}
|
||||
|
||||
void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
|
||||
{
|
||||
amd_initcpuio();
|
||||
}
|
||||
|
||||
void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid)
|
||||
{
|
||||
amd_initcpuio();
|
||||
}
|
||||
|
||||
void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late)
|
||||
{
|
||||
}
|
||||
|
||||
void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late)
|
||||
{
|
||||
}
|
||||
|
||||
void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save)
|
||||
{
|
||||
OemS3Save(&S3Save->S3DataBlock);
|
||||
}
|
||||
Reference in New Issue
Block a user