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Cosmetics, whitespace, coding style, partially ident-aided (trivial).

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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2008-05-14 21:20:55 +00:00
parent 621c09563b
commit 9a6b6b51df
3 changed files with 93 additions and 100 deletions
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35
util/inteltool/inteltool.8
View File

@ -1,4 +1,4 @@
.TH INTELTOOL 8 "May 12, 2008" .TH INTELTOOL 8 "May 14, 2008"
.SH NAME .SH NAME
inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters
.SH SYNOPSIS .SH SYNOPSIS
@ -7,9 +7,9 @@ inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters
.B inteltool .B inteltool
is a handy little tool for dumping the configuration space of Intel(R) is a handy little tool for dumping the configuration space of Intel(R)
CPUs, northbridges and southbridges. CPUs, northbridges and southbridges.
.sp
This tool has been developed for the coreboot project (see This tool has been developed for the coreboot project (see
.B http://www.coreboot.org/ .B http://coreboot.org
for details on coreboot). for details on coreboot).
.SH OPTIONS .SH OPTIONS
.TP .TP
@ -20,31 +20,32 @@ Show a help text and exit.
Show version information and exit. Show version information and exit.
.TP .TP
.B "\-a, \-\-all" .B "\-a, \-\-all"
Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge and Intel(R) Core CPU MSRs. Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge
and Intel(R) Core CPU MSRs.
.TP .TP
.B "\-g, \-\-gpio" .B "\-g, \-\-gpio"
Dump I/O Controller Hub (ICH) southbridge GPIO registers Dump I/O Controller Hub (ICH) southbridge GPIO registers.
.TP .TP
.B "\-r, \-\-rcba" .B "\-r, \-\-rcba"
Dump I/O Controller Hub (ICH) southbridge RCBA registers Dump I/O Controller Hub (ICH) southbridge RCBA registers.
.TP .TP
.B "\-p, \-\-pmbase" .B "\-p, \-\-pmbase"
Dump I/O Controller Hub (ICH) southbridge pmbase registers Dump I/O Controller Hub (ICH) southbridge PMBASE registers.
.TP .TP
.B "\-m, \-\-mchbar" .B "\-m, \-\-mchbar"
Dump Intel(R) northbridge MCHBAR registers Dump Intel(R) northbridge MCHBAR registers.
.TP .TP
.B "\-e, \-\-epbar" .B "\-e, \-\-epbar"
Dump Intel(R) northbridge EPBAR registers Dump Intel(R) northbridge EPBAR registers.
.TP .TP
.B "\-d, \-\-dmibar" .B "\-d, \-\-dmibar"
Dump Intel(R) northbridge DMIBAR registers Dump Intel(R) northbridge DMIBAR registers.
.TP .TP
.B "\-P, \-\-pciexbar" .B "\-P, \-\-pciexbar"
Dump Intel(R) northbridge PCIEXBAR registers Dump Intel(R) northbridge PCIEXBAR registers.
.TP .TP
.B "\-M, \-\-msrs" .B "\-M, \-\-msrs"
Dump Intel(R) CPU MSRs Dump Intel(R) CPU MSRs.
.SH BUGS .SH BUGS
Please report any bugs at Please report any bugs at
.BR http://tracker.coreboot.org/trac/coreboot/newticket "," .BR http://tracker.coreboot.org/trac/coreboot/newticket ","
@ -54,13 +55,13 @@ or on the coreboot mailing list
.B inteltool .B inteltool
is covered by the GNU General Public License (GPL), version 2. is covered by the GNU General Public License (GPL), version 2.
.SH COPYRIGHT .SH COPYRIGHT
(C) 2008 coresystems GmbH Copyright (C) 2008 coresystems GmbH
.SH AUTHORS .SH AUTHORS
Stefan Reinauer <stepan@coresystems.de> Stefan Reinauer <stepan@coresystems.de>
.PP .PP
This manual page was written by Stefan Reinauer <stepan@coresystems.de>. This manual page was written by Stefan Reinauer <stepan@coresystems.de>.
It is licensed under the terms of the GNU GPL (version 2). It is licensed under the terms of the GNU GPL (version 2).
.sp
Intel(R) is a registered trademark of Intel Corporation. Other product and/or company names mentioned herein may be trademarks or registered trademarks of their respective owners. Intel(R) is a registered trademark of Intel Corporation. Other product
and/or company names mentioned herein may be trademarks or registered
trademarks of their respective owners.

48
util/inteltool/inteltool.c
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@ -32,7 +32,7 @@
#define INTELTOOL_VERSION "1.0" #define INTELTOOL_VERSION "1.0"
/* Tested Chipsets: */ /* Tested chipsets: */
#define PCI_VENDOR_ID_INTEL 0x8086 #define PCI_VENDOR_ID_INTEL 0x8086
#define PCI_DEVICE_ID_INTEL_ICH 0x2410 #define PCI_DEVICE_ID_INTEL_ICH 0x2410
#define PCI_DEVICE_ID_INTEL_ICH0 0x2420 #define PCI_DEVICE_ID_INTEL_ICH0 0x2420
@ -59,9 +59,6 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" } { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }
}; };
#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
int fd_mem; int fd_mem;
@ -70,7 +67,6 @@ int fd_msr;
typedef struct { uint32_t hi, lo; } msr_t; typedef struct { uint32_t hi, lo; } msr_t;
typedef struct { uint16_t addr; int size; char *name; } io_register_t; typedef struct { uint16_t addr; int size; char *name; } io_register_t;
static const io_register_t ich0_gpio_registers[] = { static const io_register_t ich0_gpio_registers[] = {
{ 0x00, 4, "GPIO_USE_SEL" }, { 0x00, 4, "GPIO_USE_SEL" },
{ 0x04, 4, "GP_IO_SEL" }, { 0x04, 4, "GP_IO_SEL" },
@ -272,7 +268,6 @@ int print_pmbase(struct pci_dev *sb)
/* /*
* (G)MCH MMIO Config Space * (G)MCH MMIO Config Space
*/ */
int print_mchbar(struct pci_dev *nb) int print_mchbar(struct pci_dev *nb)
{ {
int i, size = (16 * 1024); int i, size = (16 * 1024);
@ -317,7 +312,7 @@ int print_mchbar(struct pci_dev *nb)
*/ */
int print_epbar(struct pci_dev *nb) int print_epbar(struct pci_dev *nb)
{ {
int i, size=4096; int i, size = (4 * 1024);
volatile uint8_t *epbar; volatile uint8_t *epbar;
uint32_t epbar_phys; uint32_t epbar_phys;
@ -353,13 +348,12 @@ int print_epbar(struct pci_dev *nb)
return 0; return 0;
} }
/* /*
* MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
*/ */
int print_dmibar(struct pci_dev *nb) int print_dmibar(struct pci_dev *nb)
{ {
int i, size=4096; int i, size = (4 * 1024);
volatile uint8_t *dmibar; volatile uint8_t *dmibar;
uint32_t dmibar_phys; uint32_t dmibar_phys;
@ -439,14 +433,14 @@ int print_pciexbar(struct pci_dev *nb)
max_busses = 64; max_busses = 64;
break; break;
default: // RSVD default: // RSVD
printf("Undefined Address base. Bailing out\n"); printf("Undefined address base. Bailing out.\n");
return 1; return 1;
} }
printf("PCIEXBAR: 0x%08x\n", pciexbar_phys); printf("PCIEXBAR: 0x%08x\n", pciexbar_phys);
pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ, MAP_SHARED, pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ,
fd_mem, (off_t) pciexbar_phys ); MAP_SHARED, fd_mem, (off_t) pciexbar_phys);
if (pciexbar == MAP_FAILED) { if (pciexbar == MAP_FAILED) {
perror("Error mapping PCIEXBAR"); perror("Error mapping PCIEXBAR");
@ -490,7 +484,7 @@ int msr_readerror = 0;
msr_t rdmsr(int addr) msr_t rdmsr(int addr)
{ {
unsigned char buf[8]; uint8_t buf[8];
msr_t msr = { 0xffffffff, 0xffffffff }; msr_t msr = { 0xffffffff, 0xffffffff };
if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) {
@ -524,7 +518,6 @@ int print_intel_core_msrs(void)
unsigned int i, core; unsigned int i, core;
msr_t msr; msr_t msr;
#define IA32_PLATFORM_ID 0x0017 #define IA32_PLATFORM_ID 0x0017
#define EBL_CR_POWERON 0x002a #define EBL_CR_POWERON 0x002a
#define FSB_CLK_STS 0x00cd #define FSB_CLK_STS 0x00cd
@ -622,10 +615,10 @@ int print_intel_core_msrs(void)
for (i = 0; i < ARRAY_SIZE(global_msrs); i++) { for (i = 0; i < ARRAY_SIZE(global_msrs); i++) {
msr = rdmsr(global_msrs[i].number); msr = rdmsr(global_msrs[i].number);
printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
global_msrs[i].number, msr.hi, msr.lo, global_msrs[i].name); global_msrs[i].number, msr.hi, msr.lo,
global_msrs[i].name);
} }
close(fd_msr); close(fd_msr);
for (core = 0; core < 8; core++) { for (core = 0; core < 8; core++) {
@ -634,19 +627,20 @@ int print_intel_core_msrs(void)
sprintf(msrfilename, "/dev/cpu/%d/msr", core); sprintf(msrfilename, "/dev/cpu/%d/msr", core);
fd_msr = open(msrfilename, O_RDWR); fd_msr = open(msrfilename, O_RDWR);
if (fd_msr<0) {
/* If the file is not there, we're probably through. /* If the file is not there, we're probably through. No error,
* No error, since we successfully opened /dev/cpu/0/msr before * since we successfully opened /dev/cpu/0/msr before.
*/ */
if (fd_msr < 0)
break; break;
}
printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core); printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core);
for (i = 0; i < ARRAY_SIZE(per_core_msrs); i++) { for (i = 0; i < ARRAY_SIZE(per_core_msrs); i++) {
msr = rdmsr(per_core_msrs[i].number); msr = rdmsr(per_core_msrs[i].number);
printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
per_core_msrs[i].number, msr.hi, msr.lo, per_core_msrs[i].name); per_core_msrs[i].number, msr.hi, msr.lo,
per_core_msrs[i].name);
} }
close(fd_msr); close(fd_msr);
@ -697,9 +691,7 @@ int main(int argc, char *argv[])
{ {
struct pci_access *pacc; struct pci_access *pacc;
struct pci_dev *sb, *nb; struct pci_dev *sb, *nb;
int opt; int i, opt, option_index = 0;
int option_index = 0;
int i;
char *sbname = "unknown", *nbname = "unknown"; char *sbname = "unknown", *nbname = "unknown";
@ -772,7 +764,10 @@ int main(int argc, char *argv[])
} }
} }
if (iopl(3)) { printf("You need to be root.\n"); exit(1); } if (iopl(3)) {
printf("You need to be root.\n");
exit(1);
}
if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) {
perror("Can not open /dev/mem"); perror("Can not open /dev/mem");
@ -783,7 +778,6 @@ int main(int argc, char *argv[])
pci_init(pacc); pci_init(pacc);
pci_scan_bus(pacc); pci_scan_bus(pacc);
/* Find the required devices */ /* Find the required devices */
sb = pci_get_dev(pacc, 0, 0, 0x1f, 0); sb = pci_get_dev(pacc, 0, 0, 0x1f, 0);
@ -870,9 +864,7 @@ int main(int argc, char *argv[])
printf("\n\n"); printf("\n\n");
} }
/* Clean up */ /* Clean up */
pci_free_dev(nb); pci_free_dev(nb);
pci_free_dev(sb); pci_free_dev(sb);
pci_cleanup(pacc); pci_cleanup(pacc);