device & commonlib: Update pci_scan_bus postcodes

The function pci_scan_bus had 3 post codes in it:
0x24 - beginning
0x25 - middle
0x55 - end

I got rid of the middle postcode and used 0x25 for the code signifying
the end of the function.  I don't think all three are needed.

0x24 & 0x25 postcodes are currently also used in intel cache-as-ram
code.  Those postcodes should be adjusted to avoid conflicting.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I19c9d5e256505b64234919a99f73a71efbbfdae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/commonlib/include/commonlib/console/post_codes.h

@@ -65,6 +65,20 @@
  */
 #define POST_ENTRY_C_START			0x13
 
+/**
+ * \brief Entry into pci_scan_bus
+ *
+ * Entered pci_scan_bus()
+ */
+#define POST_ENTER_PCI_SCAN_BUS			0x24
+
+/**
+ * \brief Entry into pci_scan_bus
+ *
+ * Entered pci_scan_bus()
+ */
+#define POST_EXIT_PCI_SCAN_BUS			0x25
+
 /**
  * \brief Pre-memory init preparation start
  *