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soc/intel/common/block: Move gspi common functions into block/gspi

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This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/gspi.

BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.

Change-Id: I877c7c48af928ca1e0399ec794d9400bc52edfcb
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik
2018-05-08 20:08:49 +05:30
parent c4986eb7f4
commit 9ab6d92e96
9 changed files with 86 additions and 194 deletions
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51
src/soc/intel/apollolake/gspi.c
View File

@@ -14,51 +14,18 @@
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <intelblocks/gspi.h>
#include <intelblocks/spi.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include "chip.h"
const struct gspi_cfg *gspi_get_soc_cfg(void)
{
const struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
return &common_config->gspi[0];
}
uintptr_t gspi_get_soc_early_base(void)
{
return EARLY_GSPI_BASE_ADDRESS;
}
/*
* SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust
* the bus # accordingly when referring to SPI / GSPI bus numbers.
*/
#define GSPI_TO_SPI_BUS(x) (x)
#define SPI_TO_GSPI_BUS(x) ((x) - 1)
int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)
{
if (spi_bus == 0)
return -1;
if (SPI_TO_GSPI_BUS(spi_bus) >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
return -1;
*gspi_bus = SPI_TO_GSPI_BUS(spi_bus);
return 0;
}
int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
{
if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
return -1;
return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));
switch (gspi_bus) {
case 0:
return PCH_DEVFN_SPI0;
case 1:
return PCH_DEVFN_SPI1;
case 2:
return PCH_DEVFN_SPI2;
}
return -1;
}

15
src/soc/intel/apollolake/spi.c
View File

@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright 2016 Google Inc.
* Copyright 2017 Intel Corporation
* Copyright 2018 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -30,16 +30,3 @@ int spi_soc_devfn_to_bus(unsigned int devfn)
}
return -1;
}
int spi_soc_bus_to_devfn(unsigned int bus)
{
switch (bus) {
case 0:
return PCH_DEVFN_SPI0;
case 1:
return PCH_DEVFN_SPI1;
case 2:
return PCH_DEVFN_SPI2;
}
return -1;
}