soc/amd/cezanne/chip: use common data fabric domain resource code

Use the new common AMD code that gets the usable non-fixed MMIO windows
from the data fabric MMIO decode registers and generate the PCI0 _CRS
ACPI code based on those regions. For a more detailed description see
the corresponding patch that changes the Picasso code to use this new
code. In contrast to the Picasso code, this change will drop the
unneeded _STA method inside the PCI0 scope which wasn't present in
Picasso's ACPI code before it got replaced by the SSDT that gets
generated by amd_pci_domain_fill_ssdt.

TEST=None

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b14ee0682ae1f2212ab43977c076687706434ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75557
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/soc/amd/cezanne/chip.c

@@ -26,10 +26,11 @@ static const char *soc_acpi_name(const struct device *dev)
 };
 
 struct device_operations cezanne_pci_domain_ops = {
-	.read_resources	= pci_domain_read_resources,
+	.read_resources	= amd_pci_domain_read_resources,
 	.set_resources	= pci_domain_set_resources,
-	.scan_bus	= pci_domain_scan_bus,
+	.scan_bus	= amd_pci_domain_scan_bus,
 	.acpi_name	= soc_acpi_name,
+	.acpi_fill_ssdt	= amd_pci_domain_fill_ssdt,
 };
 
 static void soc_init(void *chip_info)