nb/intel/ironlake: Add Generic Non-Core register definitions

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I4d878b5dbb5a5617143240b8f5bc5b6f5a754511
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/ironlake/ironlake.h

@@ -52,6 +52,10 @@
  */
 #define QPI_NON_CORE		PCI_DEV(QUICKPATH_BUS, 0, 0)
 
+#define MAX_RTIDS		0x60
+#define DESIRED_CORES		0x80
+#define MIRROR_PORT_CTL		0xd0
+
 /*
  * SAD - System Address Decoder
  */