From 9ae1bd8cda640cd86af3a29085e622d0d5939e7f Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Thu, 1 Sep 2022 15:51:15 -0600 Subject: [PATCH] mb/system76/tgl-u: Let FSP configure TBT LSX0 Signed-off-by: Tim Crawford Change-Id: I5e34f7de199ab7b1b326baf40604fe2388775567 --- src/mainboard/system76/tgl-u/variants/darp7/gpio.c | 4 ++-- src/mainboard/system76/tgl-u/variants/galp5/gpio.c | 4 ++-- src/mainboard/system76/tgl-u/variants/lemp10/gpio.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/system76/tgl-u/variants/darp7/gpio.c b/src/mainboard/system76/tgl-u/variants/darp7/gpio.c index ad18ca6483..f43db04ab4 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/gpio.c +++ b/src/mainboard/system76/tgl-u/variants/darp7/gpio.c @@ -137,8 +137,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E15, NONE), // ALERT# PAD_CFG_GPI(GPP_E16, DN_20K, DEEP), // SB_KBCRST# PAD_NC(GPP_E17, NONE), - PAD_NC(GPP_E18, NATIVE), // TBT_LSX0_TXD - programmed by FSP, see Intel document 617016 - PAD_NC(GPP_E19, NATIVE), // TBT_LSX0_RXD - programmed by FSP, see Intel document 617016 + //PAD_NC(GPP_E18, NATIVE), // TBT_LSX0_TXD - programmed by FSP, see Intel document 617016 + //PAD_NC(GPP_E19, NATIVE), // TBT_LSX0_RXD - programmed by FSP, see Intel document 617016 PAD_NC(GPP_E20, NONE), // SWI# PAD_NC(GPP_E21, NONE), // DDP2 I2C / TBT_LSX1 strap PAD_NC(GPP_E22, NONE), diff --git a/src/mainboard/system76/tgl-u/variants/galp5/gpio.c b/src/mainboard/system76/tgl-u/variants/galp5/gpio.c index 17119b3e75..c3aee3b4ab 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/gpio.c +++ b/src/mainboard/system76/tgl-u/variants/galp5/gpio.c @@ -131,8 +131,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E15, NONE), // ALERT#_R PAD_CFG_GPI(GPP_E16, DN_20K, DEEP), // SB_KBCRST# PAD_NC(GPP_E17, NONE), - PAD_NC(GPP_E18, NONE), // TBT_LSX0_TXD - programmed by FSP, see Intel document 617016 - PAD_NC(GPP_E19, NONE), // TBT_LSX0_RXD - programmed by FSP, see Intel document 617016 + //PAD_NC(GPP_E18, NONE), // TBT_LSX0_TXD - programmed by FSP, see Intel document 617016 + //PAD_NC(GPP_E19, NONE), // TBT_LSX0_RXD - programmed by FSP, see Intel document 617016 PAD_NC(GPP_E20, NONE), PAD_NC(GPP_E21, NONE), PAD_NC(GPP_E22, NONE), diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/gpio.c b/src/mainboard/system76/tgl-u/variants/lemp10/gpio.c index cca2056450..bef9b409a7 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/gpio.c +++ b/src/mainboard/system76/tgl-u/variants/lemp10/gpio.c @@ -131,8 +131,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_E15, DN_20K, DEEP), // SCI# _PAD_CFG_STRUCT(GPP_E16, 0x82840100, 0x0000), // SMI# PAD_NC(GPP_E17, NONE), - PAD_NC(GPP_E18, NONE), // TBT_LSX0_TXD - programmed by FSP, see Intel document 617016 - PAD_NC(GPP_E19, NONE), // TBT_LSX0_RXD - programmed by FSP, see Intel document 617016 + //PAD_NC(GPP_E18, NONE), // TBT_LSX0_TXD - programmed by FSP, see Intel document 617016 + //PAD_NC(GPP_E19, NONE), // TBT_LSX0_RXD - programmed by FSP, see Intel document 617016 _PAD_CFG_STRUCT(GPP_E20, 0x40880100, 0x0000), // SWI# PAD_NC(GPP_E21, NONE), // GPP_E21 - DDP2 I2C / TBT_LSX1 pin voltage (L=1.8V, H=3.3V) PAD_NC(GPP_E22, NONE),