- Major cleanup of the bootpath
- Changes to allow more code to be compiled both ways - Working SMP support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
@@ -1,76 +1,142 @@
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#ifndef _ASM_IO_H
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#define _ASM_IO_H
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#include <stdint.h>
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/*
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* This file contains the definitions for the x86 IO instructions
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* inb/inw/inl/outb/outw/outl and the "string versions" of the same
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* (insb/insw/insl/outsb/outsw/outsl).
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*
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* This file is not meant to be obfuscating: it's just complicated
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* to (a) handle it all in a way that makes gcc able to optimize it
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* as well as possible and (b) trying to avoid writing the same thing
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* over and over again with slight variations and possibly making a
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* mistake somewhere.
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* (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
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* versions of the single-IO instructions (inb_p/inw_p/..).
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*/
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/*
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* Bit simplified and optimized by Jan Hubicka
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* Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
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*/
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#ifdef __ROMCC__
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static void outb(unsigned char value, unsigned short port)
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{
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__builtin_outb(value, port);
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}
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/*
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* Talk about misusing macros..
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*/
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#define __OUT1(s,x) \
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extern inline void out##s(unsigned x value, unsigned short port) {
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static void outw(unsigned short value, unsigned short port)
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{
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__builtin_outw(value, port);
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}
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#define __OUT2(s,s1,s2) \
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__asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1"
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static void outl(unsigned int value, unsigned short port)
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{
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__builtin_outl(value, port);
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}
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#define __OUT(s,s1,x) \
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__OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "Nd" (port)); }
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#define __IN1(s) \
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extern inline RETURN_TYPE in##s(unsigned short port) { RETURN_TYPE _v;
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static unsigned char inb(unsigned short port)
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{
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return __builtin_inb(port);
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}
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#define __IN2(s,s1,s2) \
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__asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0"
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#define __IN(s,s1,i...) \
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__IN1(s) __IN2(s,s1,"w") : "=a" (_v) : "Nd" (port) ,##i ); return _v; }
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static unsigned char inw(unsigned short port)
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{
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return __builtin_inw(port);
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}
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#define __INS(s) \
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extern inline void ins##s(unsigned short port, void * addr, unsigned long count) \
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{ __asm__ __volatile__ ("cld ; rep ; ins" #s \
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: "=D" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
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static unsigned char inl(unsigned short port)
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{
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return __builtin_inl(port);
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}
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#define __OUTS(s) \
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extern inline void outs##s(unsigned short port, const void * addr, unsigned long count) \
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{ __asm__ __volatile__ ("cld ; rep ; outs" #s \
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: "=S" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
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#else
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#define RETURN_TYPE unsigned char
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__IN(b,"")
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#undef RETURN_TYPE
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#define RETURN_TYPE unsigned short
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__IN(w,"")
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#undef RETURN_TYPE
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#define RETURN_TYPE unsigned int
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__IN(l,"")
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#undef RETURN_TYPE
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static inline void outb(uint8_t value, uint16_t port)
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{
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__asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port));
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}
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__OUT(b,"b",char)
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__OUT(w,"w",short)
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__OUT(l,,int)
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static inline void outw(uint16_t value, uint16_t port)
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{
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__asm__ __volatile__ ("outw %w0, %w1" : : "a" (value), "Nd" (port));
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}
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__INS(b)
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__INS(w)
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__INS(l)
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static inline void outl(uint32_t value, uint16_t port)
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{
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__asm__ __volatile__ ("outl %0, %w1" : : "a" (value), "Nd" (port));
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}
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__OUTS(b)
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__OUTS(w)
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__OUTS(l)
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static inline uint8_t inb(uint16_t port)
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{
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uint8_t value;
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__asm__ __volatile__ ("inb %w1, %b0" : "=a"(value) : "Nd" (port));
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return value;
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}
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static inline uint16_t inw(uint16_t port)
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{
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uint16_t value;
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__asm__ __volatile__ ("inw %w1, %w0" : "=a"(value) : "Nd" (port));
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return value;
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}
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static inline uint32_t inl(uint16_t port)
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{
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uint32_t value;
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__asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port));
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return value;
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}
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#endif /* __ROMCC__ */
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static inline void outsb(uint16_t port, const void *addr, unsigned long count)
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{
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__asm__ __volatile__ (
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"cld ; rep ; outsb "
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: "=S" (addr), "=c" (count)
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: "d"(port), "0"(addr), "1" (count)
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);
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}
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static inline void outsw(uint16_t port, const void *addr, unsigned long count)
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{
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__asm__ __volatile__ (
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"cld ; rep ; outsw "
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: "=S" (addr), "=c" (count)
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: "d"(port), "0"(addr), "1" (count)
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);
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}
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static inline void outsl(uint16_t port, const void *addr, unsigned long count)
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{
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__asm__ __volatile__ (
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"cld ; rep ; outsl "
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: "=S" (addr), "=c" (count)
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: "d"(port), "0"(addr), "1" (count)
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);
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}
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static inline void insb(uint16_t port, void *addr, unsigned long count)
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{
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__asm__ __volatile__ (
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"cld ; rep ; insb "
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: "=D" (addr), "=c" (count)
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: "d"(port), "0"(addr), "1" (count)
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);
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}
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static inline void insw(uint16_t port, void *addr, unsigned long count)
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{
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__asm__ __volatile__ (
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"cld ; rep ; insw "
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: "=D" (addr), "=c" (count)
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: "d"(port), "0"(addr), "1" (count)
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);
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}
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static inline void insl(uint16_t port, void *addr, unsigned long count)
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{
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__asm__ __volatile__ (
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"cld ; rep ; insl "
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: "=D" (addr), "=c" (count)
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: "d"(port), "0"(addr), "1" (count)
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);
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}
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#endif
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@@ -1,37 +1,6 @@
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#ifndef ARCH_ROMCC_IO_H
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#define ARCH_ROMCC_IO_H 1
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static void outb(unsigned char value, unsigned short port)
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{
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__builtin_outb(value, port);
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}
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static void outw(unsigned short value, unsigned short port)
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{
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__builtin_outw(value, port);
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}
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static void outl(unsigned int value, unsigned short port)
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{
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__builtin_outl(value, port);
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}
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static unsigned char inb(unsigned short port)
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{
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return __builtin_inb(port);
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}
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static unsigned char inw(unsigned short port)
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{
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return __builtin_inw(port);
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}
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static unsigned char inl(unsigned short port)
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{
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return __builtin_inl(port);
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}
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static void hlt(void)
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{
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@@ -76,38 +45,6 @@ int log2(int value)
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return __builtin_bsr(value);
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}
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typedef __builtin_msr_t msr_t;
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static msr_t rdmsr(unsigned long index)
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{
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return __builtin_rdmsr(index);
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}
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static void wrmsr(unsigned long index, msr_t msr)
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{
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__builtin_wrmsr(index, msr.lo, msr.hi);
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}
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struct tsc_struct {
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unsigned lo;
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unsigned hi;
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};
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typedef struct tsc_struct tsc_t;
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static tsc_t rdtsc(void)
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{
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tsc_t res;
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asm ("rdtsc"
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: "=a" (res.lo), "=d"(res.hi) /* outputs */
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: /* inputs */
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: /* Clobbers */
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);
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return res;
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}
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#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
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(((BUS) & 0xFF) << 16) | \
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(((DEV) & 0x1f) << 11) | \
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@@ -57,16 +57,16 @@ static void interrupts_on()
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#if defined(APIC)
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/* Only Pentium Pro and later have those MSR stuff */
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unsigned long low, high;
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msr_t msr;
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printk_info("Setting up local apic...");
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/* Enable the local apic */
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rdmsr(APIC_BASE_MSR, low, high);
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low |= APIC_BASE_MSR_ENABLE;
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low &= ~APIC_BASE_MSR_ADDR_MASK;
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low |= APIC_DEFAULT_BASE;
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wrmsr(APIC_BASE_MSR, low, high);
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msr = rdmsr(APIC_BASE_MSR);
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msr.lo |= APIC_BASE_MSR_ENABLE;
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msr.lo &= ~APIC_BASE_MSR_ADDR_MASK;
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msr.lo |= APIC_DEFAULT_BASE;
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wrmsr(APIC_BASE_MSR, msr);
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/*
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* Set Task Priority to 'accept all'.
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@@ -103,13 +103,13 @@ static void interrupts_on()
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#else /* APIC */
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#ifdef i686
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/* Only Pentium Pro and later have those MSR stuff */
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unsigned long low, high;
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msr_t msr;
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printk_info("Disabling local apic...");
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rdmsr(APIC_BASE_MSR, low, high);
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low &= ~APIC_BASE_MSR_ENABLE;
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wrmsr(APIC_BASE_MSR, low, high);
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msr = rdmsr(APIC_BASE_MSR);
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msr.lo &= ~APIC_BASE_MSR_ENABLE;
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wrmsr(APIC_BASE_MSR, msr);
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#endif /* i686 */
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#endif /* APIC */
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printk_info("done.\n");
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@@ -143,6 +143,7 @@ unsigned long cpu_initialize(struct mem_range *mem)
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configure_l2_cache();
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#endif
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interrupts_on();
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processor_id = this_processors_id();
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printk_info("CPU #%d Initialized\n", processor_id);
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return processor_id;
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}
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76
src/arch/i386/smp/secondary.S
Normal file
76
src/arch/i386/smp/secondary.S
Normal file
@@ -0,0 +1,76 @@
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#include <arch/asm.h>
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#include <arch/intel.h>
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#include <cpu/p6/mtrr.h>
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#include <cpu/p6/apic.h>
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.text
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.globl _secondary_start
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.balign 4096
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_secondary_start:
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.code16
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cli
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xorl %eax, %eax
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movl %eax, %cr3 /* Invalidate TLB*/
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/* On hyper threaded cpus invalidating the cache here is
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* very very bad. Don't.
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*/
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/* setup the data segment */
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movw %cs, %ax
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movw %ax, %ds
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data32 lgdt gdtaddr - _secondary_start
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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movl %eax, %cr0
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ljmpl $0x10, $1f
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1:
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.code32
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movw $0x18, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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/* Enable the local apic, and map it where we expext it */
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movl $APIC_BASE_MSR, %ecx
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rdmsr
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orl $APIC_BASE_MSR_ENABLE, %eax
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andl $(~APIC_BASE_MSR_ADDR_MASK), %eax
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orl $APIC_DEFAULT_BASE, %eax
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wrmsr
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/* Get the apic_id */
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movl (APIC_ID + APIC_DEFAULT_BASE), %edi
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shrl $24, %edi
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/* Get the cpu index (MAX_CPUS on error) */
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movl $-4, %ebx
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1: addl $4, %ebx
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cmpl $(MAX_CPUS << 2), %ebx
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je 2
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cmpl %edi, initial_apicid(%ebx)
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jne 1b
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2: shrl $2, %ebx
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/* set the stack pointer */
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movl $_estack, %esp
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movl %ebx, %eax
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movl $STACK_SIZE, %ebx
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mull %ebx
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subl %eax, %esp
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call secondary_cpu_init
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1: hlt
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jmp 1b
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gdtaddr:
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.word gdt_limit /* the table limit */
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.long gdt /* we know the offset */
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.code32
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@@ -3,6 +3,7 @@
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#include <cpu/p6/apic.h>
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#include <delay.h>
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#include <string.h>
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#include <console/console.h>
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#ifndef START_CPU_SEG
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#define START_CPU_SEG 0x90000
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Reference in New Issue
Block a user