- Major cleanup of the bootpath
- Changes to allow more code to be compiled both ways - Working SMP support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
26
src/cpu/k8/apic_timer.c
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26
src/cpu/k8/apic_timer.c
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@ -0,0 +1,26 @@
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#include <stdint.h>
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#include <delay.h>
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#include <cpu/p6/msr.h>
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#include <cpu/p6/apic.h>
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void init_timer(void)
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{
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/* Set the apic timer to no interrupts and periodic mode */
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apic_write(APIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
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/* Set the divider to 1, no divider */
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apic_write(APIC_TDCR, APIC_TDR_DIV_1);
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/* Set the initial counter to 0xffffffff */
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apic_write(APIC_TMICT, 0xffffffff);
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}
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void udelay(unsigned usecs)
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{
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uint32_t start, value, ticks;
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/* Calculate the number of ticks to run, our FSB runs a 200Mhz */
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ticks = usecs * 200;
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start = apic_read(APIC_TMCCT);
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do {
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value = apic_read(APIC_TMCCT);
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} while((start - value) < ticks);
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}
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@ -13,7 +13,8 @@
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void k8_cpufixup(struct mem_range *mem)
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{
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unsigned long lo = 0, hi = 0, i;
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msr_t msr;
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unsigned long i;
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unsigned long ram_megabytes;
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/* For now no Athlon board has significant holes in it's
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@ -27,33 +28,34 @@ void k8_cpufixup(struct mem_range *mem)
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ram_megabytes = (mem[i-1].basek + mem[i-1].sizek) *1024;
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#warning "FIXME handle > 4GB of ram"
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// 8 MB alignment please
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ram_megabytes += 0x7fffff;
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ram_megabytes &= (~0x7fffff);
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// set top_mem registers to ram size
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printk_spew("Setting top_mem to 0x%x\n", ram_megabytes);
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rdmsr(TOP_MEM, lo, hi);
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printk_spew("TOPMEM was 0x%02x:0x%02x\n", hi, lo);
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hi = 0;
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lo = ram_megabytes;
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wrmsr(TOP_MEM, lo, hi);
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msr = rdmsr(TOP_MEM);
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printk_spew("TOPMEM was 0x%02x:0x%02x\n", msr.hi, msr.lo);
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msr.hi = 0;
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msr.lo = ram_megabytes;
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wrmsr(TOP_MEM, msr);
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// I am setting this even though I won't enable it
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wrmsr(TOP_MEM2, lo, hi);
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wrmsr(TOP_MEM2, msr);
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/* zero the IORR's before we enable to prevent
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* undefined side effects
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*/
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lo = hi = 0;
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msr.lo = msr.hi = 0;
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for (i = IORR_FIRST; i <= IORR_LAST; i++)
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wrmsr(i, lo, hi);
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wrmsr(i, msr);
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rdmsr(SYSCFG, lo, hi);
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printk_spew("SYSCFG was 0x%x:0x%x\n", hi, lo);
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lo |= MTRRVARDRAMEN;
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wrmsr(SYSCFG, lo, hi);
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rdmsr(SYSCFG, lo, hi);
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printk_spew("SYSCFG IS NOW 0x%x:0x%x\n", hi, lo);
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msr = rdmsr(SYSCFG);
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printk_spew("SYSCFG was 0x%x:0x%x\n", msr.hi, msr.lo);
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msr.lo |= MTRRVARDRAMEN;
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wrmsr(SYSCFG, msr);
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msr = rdmsr(SYSCFG);
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printk_spew("SYSCFG IS NOW 0x%x:0x%x\n", msr.hi, msr.lo);
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}
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87
src/cpu/k8/earlymtrr.c
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87
src/cpu/k8/earlymtrr.c
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@ -0,0 +1,87 @@
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#include <cpu/k8/mtrr.h>
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/* the fixed and variable MTTRs are power-up with random values,
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* clear them to MTRR_TYPE_UNCACHEABLE for safty.
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*/
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static void early_mtrr_init(void)
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{
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static unsigned long mtrr_msrs[] = {
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/* fixed mtrr */
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0x250, 0x258, 0x259,
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0x268, 0x269, 0x26A
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0x26B, 0x26C, 0x26D
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0x26E, 0x26F,
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/* var mtrr */
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0x200, 0x201, 0x202, 0x203,
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0x204, 0x205, 0x206, 0x207,
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0x208, 0x209, 0x20A, 0x20B,
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0x20C, 0x20D, 0x20E, 0x20F,
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/* var iorr msr */
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0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019,
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/* mem top */
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0xC001001A, 0xC001001D,
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/* NULL end of table */
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0
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};
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msr_t msr;
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unsigned long *msr_addr;
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/* Inialize all of the relevant msrs to 0 */
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msr.lo = 0;
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msr.hi = 0;
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for(msr_addr = &mtrr_msrs; *msr_addr; msr_addr++) {
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wrmsr(*msr_addr, msr);
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}
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/* Enable memory access for 0 - 8MB using top_mem */
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msr.hi = 0;
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msr.lo = 0x08000000;
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wrmsr(TOP_MEM, msr);
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/* Enable caching for 0 - 128MB using variable mtrr */
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msr = rdmsr(0x200);
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msr.hi &= 0xfffffff0;
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msr.hi |= 0x00000000;
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msr.lo &= 0x00000f00;
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msr.lo |= 0x00000006;
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wrmsr(0x200, msr);
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msr = rdmsr(0x201);
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msr.hi &= 0xfffffff0;
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msr.hi |= 0x0000000f;
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msr.lo &= 0x000007ff;
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msr.lo |= 0xf0000800;
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wrmsr(0x201, msr);
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#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
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/* enable write back caching so we can do execute in place
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* on the flash rom.
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*/
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msr.hi = 0x00000000;
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msr.lo = XIP_ROM_BASE | 0x005;
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wrmsr(0x202);
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#error "FIXME verify the type of MTRR I have setup"
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msr.hi = 0x0000000f;
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msr.lo = ~(XIP_ROM_SIZE - 1) | 0x800;
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wrmsr(0x203);
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#endif
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/* Set the default memory type and enable fixed and variable MTRRs
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*/
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/* Enable Variable MTRRs */
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msr.hi = 0x00000000;
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msr.lo = 0x00000800;
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wrmsr(0x2ff, msr);
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/* Enale the MTRRs in SYSCFG */
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msr = rdmsr(SYSCFG_MSR);
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msr.lo |= SYSCFG_MSR_MtrrrVarDramEn;
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wrmsr(SYSCFG_MSR, msr);
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/* Enable the cache */
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unsigned long cr0;
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cr0 = read_cr0();
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cr0 &= 0x9fffffff;
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write_cr0(cr0);
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}
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@ -9,21 +9,20 @@ int mtrr_check(void)
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{
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#ifdef i686
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/* Only Pentium Pro and later have MTRR */
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unsigned long low, high;
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msr_t msr;
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printk_debug("\nMTRR check\n");
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rdmsr(0x2ff, low, high);
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low = low >> 10;
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msr = rdmsr(0x2ff);
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msr.lo >>= 10;
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printk_debug("Fixed MTRRs : ");
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if (low & 0x01)
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if (msr.lo & 0x01)
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printk_debug("Enabled\n");
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else
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printk_debug("Disabled\n");
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printk_debug("Variable MTRRs: ");
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if (low & 0x02)
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if (msr.lo & 0x02)
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printk_debug("Enabled\n");
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else
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printk_debug("Disabled\n");
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@ -31,7 +30,7 @@ int mtrr_check(void)
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printk_debug("\n");
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post_code(0x93);
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return ((int) low);
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return ((int) msr.lo);
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#else /* !i686 */
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return 0;
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#endif /* i686 */
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12
src/cpu/p6/boot_cpu.c
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12
src/cpu/p6/boot_cpu.c
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@ -0,0 +1,12 @@
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#include <cpu/p6/msr.h>
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int boot_cpu(void)
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{
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volatile unsigned long *local_apic;
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unsigned long apic_id;
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int bsp;
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msr_t msr;
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msr = rdmsr(0x1b);
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bsp = !!(msr.lo & (1 << 8));
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return bsp;
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}
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@ -40,20 +40,20 @@ static unsigned int mtrr_msr[] = {
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static void intel_enable_fixed_mtrr(void)
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{
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unsigned long low, high;
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msr_t msr;
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rdmsr(MTRRdefType_MSR, low, high);
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low |= 0xc00;
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wrmsr(MTRRdefType_MSR, low, high);
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msr = rdmsr(MTRRdefType_MSR);
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msr.lo |= 0xc00;
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wrmsr(MTRRdefType_MSR, msr);
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}
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static void intel_enable_var_mtrr(void)
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{
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unsigned long low, high;
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msr_t msr;
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rdmsr(MTRRdefType_MSR, low, high);
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low |= 0x800;
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wrmsr(MTRRdefType_MSR, low, high);
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msr = rdmsr(MTRRdefType_MSR);
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msr.lo |= 0x800;
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wrmsr(MTRRdefType_MSR, msr);
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}
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static inline void disable_cache(void)
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@ -86,19 +86,18 @@ static inline void enable_cache(void)
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/* setting variable mtrr, comes from linux kernel source */
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static void intel_set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type)
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{
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unsigned long base_high, base_low;
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unsigned long mask_high, mask_low;
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msr_t base, mask;
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base_high = basek >> 22;
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base_low = basek << 10;
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base.hi = basek >> 22;
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base.lo = basek << 10;
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if (sizek < 4*1024*1024) {
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mask_high = 0x0F;
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mask_low = ~((sizek << 10) -1);
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mask.hi = 0x0F;
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mask.lo = ~((sizek << 10) -1);
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}
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else {
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mask_high = 0x0F & (~((sizek >> 22) -1));
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mask_low = 0;
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mask.hi = 0x0F & (~((sizek >> 22) -1));
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mask.lo = 0;
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}
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if (reg >= 8)
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@ -108,13 +107,17 @@ static void intel_set_var_mtrr(unsigned int reg, unsigned long basek, unsigned l
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// do this.
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disable_cache();
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if (sizek == 0) {
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msr_t zero;
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zero.lo = zero.hi = 0;
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/* The invalid bit is kept in the mask, so we simply clear the
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relevant mask register to disable a range. */
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wrmsr (MTRRphysMask_MSR (reg), 0, 0);
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wrmsr (MTRRphysMask_MSR(reg), zero);
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} else {
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/* Bit 32-35 of MTRRphysMask should be set to 1 */
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wrmsr (MTRRphysBase_MSR(reg), base_low | type, base_high);
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wrmsr (MTRRphysMask_MSR(reg), mask_low | 0x800, mask_high);
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base.lo |= type;
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mask.lo |= 0x800;
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wrmsr (MTRRphysBase_MSR(reg), base);
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wrmsr (MTRRphysMask_MSR(reg), mask);
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}
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enable_cache();
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}
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@ -131,11 +134,18 @@ void set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsi
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if (size == 0) {
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/* The invalid bit is kept in the mask, so we simply clear the
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relevant mask register to disable a range. */
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wrmsr (MTRRphysMask_MSR (reg), 0, 0);
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msr_t zero;
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zero.lo = zero.hi = 0;
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wrmsr (MTRRphysMask_MSR(reg), zero);
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} else {
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/* Bit 32-35 of MTRRphysMask should be set to 1 */
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wrmsr (MTRRphysBase_MSR (reg), base | type, 0);
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wrmsr (MTRRphysMask_MSR (reg), ~(size - 1) | 0x800, 0x0F);
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msr_t basem, maskm;
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basem.lo = base | type;
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basem.hi = 0;
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maskm.lo = ~(size - 1) | 0x800;
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maskm.hi = 0x0F;
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wrmsr (MTRRphysBase_MSR(reg), basem);
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wrmsr (MTRRphysMask_MSR(reg), maskm);
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}
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// turn cache back on.
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@ -197,32 +207,32 @@ static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char
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{
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unsigned int i;
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unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
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unsigned long low, high;
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low = high = 0; /* Shut up gcc */
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msr_t msr;
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msr.lo = msr.hi = 0; /* Shut up gcc */
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for(i = first; i < last; i++) {
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/* When I switch to a new msr read it in */
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if (fixed_msr != i >> 3) {
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/* But first write out the old msr */
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if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
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disable_cache();
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wrmsr(mtrr_msr[fixed_msr], low, high);
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wrmsr(mtrr_msr[fixed_msr], msr);
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enable_cache();
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}
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fixed_msr = i>>3;
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rdmsr(mtrr_msr[fixed_msr], low, high);
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msr = rdmsr(mtrr_msr[fixed_msr]);
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}
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if ((i & 7) < 4) {
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low &= ~(0xff << ((i&3)*8));
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low |= type << ((i&3)*8);
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msr.lo &= ~(0xff << ((i&3)*8));
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msr.lo |= type << ((i&3)*8);
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} else {
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high &= ~(0xff << ((i&3)*8));
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high |= type << ((i&3)*8);
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msr.hi &= ~(0xff << ((i&3)*8));
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msr.hi |= type << ((i&3)*8);
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}
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}
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/* Write out the final msr */
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if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
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disable_cache();
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wrmsr(mtrr_msr[fixed_msr], low, high);
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wrmsr(mtrr_msr[fixed_msr], msr);
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enable_cache();
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}
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}
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Reference in New Issue
Block a user