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- Major cleanup of the bootpath

Browse Source 
- Changes to allow more code to be compiled both ways
- Working SMP support


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
2003-07-19 04:28:22 +00:00
parent fe4414587a
commit 9b4336cf41
27 changed files with 804 additions and 604 deletions
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32
src/cpu/k8/cpufixup.c
View File

@@ -13,7 +13,8 @@
void k8_cpufixup(struct mem_range *mem)
{
unsigned long lo = 0, hi = 0, i;
msr_t msr;
unsigned long i;
unsigned long ram_megabytes;
/* For now no Athlon board has significant holes in it's
@@ -27,33 +28,34 @@ void k8_cpufixup(struct mem_range *mem)
ram_megabytes = (mem[i-1].basek + mem[i-1].sizek) *1024;
#warning "FIXME handle > 4GB of ram"
// 8 MB alignment please
ram_megabytes += 0x7fffff;
ram_megabytes &= (~0x7fffff);
// set top_mem registers to ram size
printk_spew("Setting top_mem to 0x%x\n", ram_megabytes);
rdmsr(TOP_MEM, lo, hi);
printk_spew("TOPMEM was 0x%02x:0x%02x\n", hi, lo);
hi = 0;
lo = ram_megabytes;
wrmsr(TOP_MEM, lo, hi);
msr = rdmsr(TOP_MEM);
printk_spew("TOPMEM was 0x%02x:0x%02x\n", msr.hi, msr.lo);
msr.hi = 0;
msr.lo = ram_megabytes;
wrmsr(TOP_MEM, msr);
// I am setting this even though I won't enable it
wrmsr(TOP_MEM2, lo, hi);
wrmsr(TOP_MEM2, msr);
/* zero the IORR's before we enable to prevent
* undefined side effects
*/
lo = hi = 0;
msr.lo = msr.hi = 0;
for (i = IORR_FIRST; i <= IORR_LAST; i++)
wrmsr(i, lo, hi);
wrmsr(i, msr);
rdmsr(SYSCFG, lo, hi);
printk_spew("SYSCFG was 0x%x:0x%x\n", hi, lo);
lo |= MTRRVARDRAMEN;
wrmsr(SYSCFG, lo, hi);
rdmsr(SYSCFG, lo, hi);
printk_spew("SYSCFG IS NOW 0x%x:0x%x\n", hi, lo);
msr = rdmsr(SYSCFG);
printk_spew("SYSCFG was 0x%x:0x%x\n", msr.hi, msr.lo);
msr.lo |= MTRRVARDRAMEN;
wrmsr(SYSCFG, msr);
msr = rdmsr(SYSCFG);
printk_spew("SYSCFG IS NOW 0x%x:0x%x\n", msr.hi, msr.lo);
}