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Clean up fidvid files using indent.

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Remove some special print statements.

In general, make them easier to compare.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2010-04-08 15:09:53 +00:00
parent 4839e2c495
commit 9b43afde39
33 changed files with 347 additions and 356 deletions
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57
src/cpu/amd/model_10xxx/fidvid.c
View File

@ -17,41 +17,39 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#if FAM10_SET_FIDVID == 1 #if SET_FIDVID == 1
#include "../../../northbridge/amd/amdht/AsPsDefs.h" #include "../../../northbridge/amd/amdht/AsPsDefs.h"
#define FAM10_SET_FIDVID_DEBUG 1 #define SET_FIDVID_DEBUG 1
// if we are tight of CAR stack, disable it // if we are tight of CAR stack, disable it
#define FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1 #define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
static inline void print_debug_fv(const char *str, u32 val) static inline void print_debug_fv(const char *str, u32 val)
{ {
#if FAM10_SET_FIDVID_DEBUG == 1 #if SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%x\n", str, val); printk(BIOS_DEBUG, "%s%x\n", str, val);
#endif #endif
} }
static inline void print_debug_fv_8(const char *str, u8 val) static inline void print_debug_fv_8(const char *str, u8 val)
{ {
#if FAM10_SET_FIDVID_DEBUG == 1 #if SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%02x\n", str, val); printk(BIOS_DEBUG, "%s%02x\n", str, val);
#endif #endif
} }
static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
{ {
#if FAM10_SET_FIDVID_DEBUG == 1 #if SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
#endif #endif
} }
struct fidvid_st { struct fidvid_st {
u32 common_fid; u32 common_fid;
}; };
static void enable_fid_change(u8 fid) static void enable_fid_change(u8 fid)
{ {
u32 dword; u32 dword;
@ -68,11 +66,11 @@ static void enable_fid_change(u8 fid)
dword |= (u32) fid & 0x1F; dword |= (u32) fid & 0x1F;
dword |= 1 << 5; // enable dword |= 1 << 5; // enable
pci_write_config32(dev, 0xd4, dword); pci_write_config32(dev, 0xd4, dword);
printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i, dword); printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i,
dword);
} }
} }
static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
{ {
u8 pviModeFlag; u8 pviModeFlag;
@ -94,8 +92,6 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
* decimals. * decimals.
*/ */
/* Determine if this is a PVI or SVI system */ /* Determine if this is a PVI or SVI system */
dtemp = pci_read_config32(dev, 0xA0); dtemp = pci_read_config32(dev, 0xA0);
@ -173,7 +169,6 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
pci_write_config32(dev, 0xd8, dtemp); pci_write_config32(dev, 0xd8, dtemp);
} }
static void prep_fid_change(void) static void prep_fid_change(void)
{ {
u32 dword, dtemp; u32 dword, dtemp;
@ -214,8 +209,7 @@ static void prep_fid_change(void)
*/ */
dword = pci_read_config32(dev, 0xd4); dword = pci_read_config32(dev, 0xd4);
dword &= CPTC0_MASK; dword &= CPTC0_MASK;
dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 | dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 | LNK_PLL_LOCK; /* per BKDG */
LNK_PLL_LOCK; /* per BKDG */
pci_write_config32(dev, 0xd4, dword); pci_write_config32(dev, 0xd4, dword);
} else { } else {
dword = pci_read_config32(dev, 0xd4); dword = pci_read_config32(dev, 0xd4);
@ -226,8 +220,7 @@ static void prep_fid_change(void)
3 cores - 133nS -> 100nS - 0011b 3 cores - 133nS -> 100nS - 0011b
4 cores - 100nS - 0011b 4 cores - 100nS - 0011b
*/ */
switch(get_core_num_in_bsp(i)) switch (get_core_num_in_bsp(i)) {
{
case 0: case 0:
dword |= PW_STP_UP400 | PW_STP_DN400; dword |= PW_STP_UP400 | PW_STP_DN400;
break; break;
@ -325,8 +318,6 @@ static void UpdateSinglePlaneNbVid(void)
} }
} }
static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid) static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid)
{ {
msr_t msr; msr_t msr;
@ -379,7 +370,6 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid)
} }
} }
static void coreDelay(void) static void coreDelay(void)
{ {
u32 saved; u32 saved;
@ -400,7 +390,6 @@ static void coreDelay (void)
} while (lo - saved < cycles); } while (lo - saved < cycles);
} }
static void transitionVid(u32 targetVid, u8 dev, u8 isNb) static void transitionVid(u32 targetVid, u8 dev, u8 isNb)
{ {
u32 currentVid, dtemp; u32 currentVid, dtemp;
@ -564,7 +553,6 @@ static u32 calc_common_fid(u32 fid_packed, u32 fid_packed_new)
return fid_packed; return fid_packed;
} }
static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp) static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp)
{ {
u32 readback = 0; u32 readback = 0;
@ -577,15 +565,17 @@ static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp )
loop = 100000; loop = 100000;
while (--loop > 0) { while (--loop > 0) {
if(lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0) continue; if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0)
continue;
if ((readback & 0x3f) == 1) { if ((readback & 0x3f) == 1) {
timeout = 0; timeout = 0;
break; //target ap is in stage 1 break; /* target ap is in stage 1 */
} }
} }
if (timeout) { if (timeout) {
print_initcpu8("fidvid_bsp_stage1: time out while reading from ap ", ap_apicid); printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n",
__func__, ap_apicid);
return; return;
} }
@ -597,7 +587,6 @@ static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp )
} }
static void updateSviPsNbVidAfterWR(u32 newNbVid) static void updateSviPsNbVidAfterWR(u32 newNbVid)
{ {
msr_t msr; msr_t msr;
@ -657,7 +646,6 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll)
} while (msr.lo != StartupPstate); } while (msr.lo != StartupPstate);
} }
static void set_p0(void) static void set_p0(void)
{ {
msr_t msr; msr_t msr;
@ -673,8 +661,8 @@ static void set_p0(void)
} while (msr.lo != 0); } while (msr.lo != 0);
} }
static void finalPstateChange(void)
static void finalPstateChange (void) { {
/* Enble P0 on all cores for best performance. /* Enble P0 on all cores for best performance.
* Linux can slow them down later if need be. * Linux can slow them down later if need be.
* It is safe since they will be in C1 halt * It is safe since they will be in C1 halt
@ -683,7 +671,6 @@ static void finalPstateChange (void) {
set_p0(); set_p0();
} }
static void init_fidvid_stage2(u32 apicid, u32 nodeid) static void init_fidvid_stage2(u32 apicid, u32 nodeid)
{ {
msr_t msr; msr_t msr;
@ -742,7 +729,7 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid)
} }
#if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 #if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
struct ap_apicid_st { struct ap_apicid_st {
u32 num; u32 num;
// it could use 256 bytes for 64 node quad core system // it could use 256 bytes for 64 node quad core system
@ -761,7 +748,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp)
static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
{ {
#if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 #if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
struct ap_apicid_st ap_apicidx; struct ap_apicid_st ap_apicidx;
u32 i; u32 i;
#endif #endif
@ -819,20 +806,20 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8); fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8);
print_debug_fv("BSP fid = ", fv.common_fid); print_debug_fv("BSP fid = ", fv.common_fid);
#if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && FAM10_SET_FIDVID_CORE0_ONLY == 0 #if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && SET_FIDVID_CORE0_ONLY == 0
/* For all APs (We know the APIC ID of all APs even when the APIC ID /* For all APs (We know the APIC ID of all APs even when the APIC ID
is lifted) remote read from AP LAPIC_MSG_REG about max fid. is lifted) remote read from AP LAPIC_MSG_REG about max fid.
Then calculate the common max fid that can be used for all Then calculate the common max fid that can be used for all
APs and BSP */ APs and BSP */
ap_apicidx.num = 0; ap_apicidx.num = 0;
for_each_ap(bsp_apicid, FAM10_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx); for_each_ap(bsp_apicid, SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
for (i = 0; i < ap_apicidx.num; i++) { for (i = 0; i < ap_apicidx.num; i++) {
init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
} }
#else #else
for_each_ap(bsp_apicid, FAM10_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
#endif #endif
print_debug_fv("common_fid = ", fv.common_fid); print_debug_fv("common_fid = ", fv.common_fid);

16
src/cpu/amd/model_10xxx/init_cpus.c
View File

@ -20,14 +20,14 @@
#include "defaults.h" #include "defaults.h"
//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
#ifndef FAM10_SET_FIDVID #ifndef SET_FIDVID
#define FAM10_SET_FIDVID 1 #define SET_FIDVID 1
#endif #endif
#ifndef FAM10_SET_FIDVID_CORE0_ONLY #ifndef SET_FIDVID_CORE0_ONLY
/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores,
Need to do every AP to set common FID/VID*/ Need to do every AP to set common FID/VID*/
#define FAM10_SET_FIDVID_CORE0_ONLY 0 #define SET_FIDVID_CORE0_ONLY 0
#endif #endif
static void print_initcpu8 (const char *strval, u8 val) static void print_initcpu8 (const char *strval, u8 val)
@ -217,7 +217,7 @@ static int lapic_remote_read(int apicid, int reg, u32 *pvalue)
#define LAPIC_MSG_REG 0x380 #define LAPIC_MSG_REG 0x380
#if FAM10_SET_FIDVID == 1 #if SET_FIDVID == 1
static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid); static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid);
#endif #endif
@ -398,8 +398,8 @@ static u32 init_cpus(u32 cpu_init_detectedx)
cpuSetAMDMSR(); cpuSetAMDMSR();
#if FAM10_SET_FIDVID == 1 #if SET_FIDVID == 1
#if (CONFIG_LOGICAL_CPUS == 1) && (FAM10_SET_FIDVID_CORE0_ONLY == 1) #if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1)
// Run on all AP for proper FID/VID setup. // Run on all AP for proper FID/VID setup.
if(id.coreid == 0 ) // only need set fid for core0 if(id.coreid == 0 ) // only need set fid for core0
#endif #endif
@ -994,7 +994,7 @@ void finalize_node_setup(struct sys_info *sysinfo)
cpuSetAMDPCI(i); cpuSetAMDPCI(i);
} }
#if FAM10_SET_FIDVID == 1 #if SET_FIDVID == 1
// Prep each node for FID/VID setup. // Prep each node for FID/VID setup.
prep_fid_change(); prep_fid_change();
#endif #endif

142
src/cpu/amd/model_fxx/fidvid.c
View File

@ -1,10 +1,10 @@
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
#define K8_SET_FIDVID_DEBUG 0 #define SET_FIDVID_DEBUG 0
#define K8_SET_FIDVID_ONE_BY_ONE 1 #define SET_FIDVID_ONE_BY_ONE 1
#define K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1 #define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
#ifndef SB_VFSMAF #ifndef SB_VFSMAF
#define SB_VFSMAF 1 #define SB_VFSMAF 1
@ -12,32 +12,31 @@
#define FX_SUPPORT 1 #define FX_SUPPORT 1
static inline void print_debug_fv(const char *str, unsigned val) static inline void print_debug_fv(const char *str, u32 val)
{ {
#if K8_SET_FIDVID_DEBUG == 1 #if SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%x\n", str, val); printk(BIOS_DEBUG, "%s%x\n", str, val);
#endif #endif
} }
static inline void print_debug_fv_8(const char *str, unsigned val) static inline void print_debug_fv_8(const char *str, u8 val)
{ {
#if K8_SET_FIDVID_DEBUG == 1 #if SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%02x\n", str, val); printk(BIOS_DEBUG, "%s%02x\n", str, val);
#endif #endif
} }
static inline void print_debug_fv_64(const char *str, unsigned val, unsigned val2) static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
{ {
#if K8_SET_FIDVID_DEBUG == 1 #if SET_FIDVID_DEBUG == 1
printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
#endif #endif
} }
static void enable_fid_change(void) static void enable_fid_change(void)
{ {
uint32_t dword; u32 dword;
unsigned nodes; u32 nodes;
int i; int i;
nodes = ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60) >> 4) & 7) + 1; nodes = ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60) >> 4) & 7) + 1;
@ -71,12 +70,12 @@ static void enable_fid_change(void)
} }
} }
#if K8_SET_FIDVID_ONE_BY_ONE == 0 #if SET_FIDVID_ONE_BY_ONE == 0
static unsigned set_fidvid_without_init(unsigned fidvid) static unsigned set_fidvid_without_init(unsigned fidvid)
{ {
msr_t msr; msr_t msr;
uint32_t vid; u32 vid;
uint32_t fid; u32 fid;
fid = (fidvid >> 8) & 0x3f; fid = (fidvid >> 8) & 0x3f;
vid = (fidvid >> 16) & 0x3f; vid = (fidvid >> 16) & 0x3f;
@ -117,12 +116,12 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
}; };
msr_t msr; msr_t msr;
uint32_t vid_new; u32 vid_new;
uint32_t fid_new; u32 fid_new;
uint32_t vid_max; u32 vid_max;
uint32_t fid_max; u32 fid_max;
uint32_t vid_cur; u32 vid_cur;
uint32_t fid_cur; u32 fid_cur;
unsigned apicidx; unsigned apicidx;
int step_limit; int step_limit;
@ -131,7 +130,9 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
apicidx = lapicid(); apicidx = lapicid();
if (apicid != apicidx) { if (apicid != apicidx) {
printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\n", apicid, apicidx); printk(BIOS_ERR,
"wrong apicid, we want change %x, but it is %x\n",
apicid, apicidx);
return fidvid; return fidvid;
} }
@ -179,7 +180,6 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
ldtstop_sb(); ldtstop_sb();
#endif #endif
for (loop = 0; loop < 100000; loop++) { for (loop = 0; loop < 100000; loop++) {
msr = rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
if (!(msr.lo & (1 << 31))) if (!(msr.lo & (1 << 31)))
@ -201,7 +201,8 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
* transition to target fid * transition to target fid
*/ */
printk(BIOS_DEBUG, "Current fid_cur: 0x%x, fid_max: 0x%x\n", fid_cur, fid_max); printk(BIOS_DEBUG, "Current fid_cur: 0x%x, fid_max: 0x%x\n", fid_cur,
fid_max);
printk(BIOS_DEBUG, "Requested fid_new: 0x%x\n", fid_new); printk(BIOS_DEBUG, "Requested fid_new: 0x%x\n", fid_new);
step_limit = 8; /* max 8 steps just in case... */ step_limit = 8; /* max 8 steps just in case... */
@ -226,14 +227,14 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
else else
fid_temp = fid_cur - 2; fid_temp = fid_cur - 2;
} else if (step > 2) { /* If more than a 200Mhz step */ } else if (step > 2) { /* If more than a 200Mhz step */
int temp; int temp;
/* look it up in the table */ /* look it up in the table */
printk(BIOS_DEBUG, "FidVid table step "); printk(BIOS_DEBUG, "FidVid table step ");
temp = next_fid_200[((fid_new/2) * 13) + (fid_cur/2)]; temp =
next_fid_200[((fid_new / 2) * 13) + (fid_cur / 2)];
if (temp > 0) if (temp > 0)
fid_temp = (temp - 4) * 2; /* Table 108 */ fid_temp = (temp - 4) * 2; /* Table 108 */
@ -257,7 +258,8 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
} }
if (fid_temp > fid_max) { if (fid_temp > fid_max) {
printk(BIOS_DEBUG, "fid_temp 0x%x > fid_max 0x%x\n", fid_temp, fid_max); printk(BIOS_DEBUG, "fid_temp 0x%x > fid_max 0x%x\n",
fid_temp, fid_max);
break; break;
} }
@ -274,8 +276,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
ldtstop_sb(); ldtstop_sb();
#endif #endif
#if SET_FIDVID_DEBUG == 1
#if K8_SET_FIDVID_DEBUG == 1
if (showmessage) { if (showmessage) {
print_debug_fv_8("set_fidvid APICID = ", apicid); print_debug_fv_8("set_fidvid APICID = ", apicid);
print_debug_fv_64("fidvid ctrl msr ", msr.hi, msr.lo); print_debug_fv_64("fidvid ctrl msr ", msr.hi, msr.lo);
@ -289,7 +290,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
} }
fid_cur = msr.lo & 0x3f; fid_cur = msr.lo & 0x3f;
#if K8_SET_FIDVID_DEBUG == 1 #if SET_FIDVID_DEBUG == 1
if (showmessage) { if (showmessage) {
print_debug_fv_64("fidvid status msr ", msr.hi, msr.lo); print_debug_fv_64("fidvid status msr ", msr.hi, msr.lo);
} }
@ -328,10 +329,12 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
if (showmessage) { if (showmessage) {
if (vid_new != vid_cur) { if (vid_new != vid_cur) {
print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\n"); printk(BIOS_ERR, "set vid failed for apicid =%02x\n",
apicidx);
} }
if (fid_new != fid_cur) { if (fid_new != fid_cur) {
print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\n"); printk(BIOS_ERR, "set fid failed for apicid =%02x\n",
apicidx);
} }
} }
@ -341,13 +344,13 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
{ {
uint32_t send; u32 send;
uint32_t readback = 0; u32 readback = 0;
unsigned timeout = 1; unsigned timeout = 1;
msr_t msr; msr_t msr;
uint32_t vid_cur; u32 vid_cur;
uint32_t fid_cur; u32 fid_cur;
uint32_t fid_max; u32 fid_max;
int loop; int loop;
msr = rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
@ -365,7 +368,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
send |= ((msr.hi >> (48 - 32)) & 0x3f) << 16; /* max vid */ send |= ((msr.hi >> (48 - 32)) & 0x3f) << 16; /* max vid */
send |= (apicid << 24); /* ap apicid */ send |= (apicid << 24); /* ap apicid */
#if K8_SET_FIDVID_ONE_BY_ONE == 1 #if SET_FIDVID_ONE_BY_ONE == 1
vid_cur = msr.hi & 0x3f; vid_cur = msr.hi & 0x3f;
fid_cur = msr.lo & 0x3f; fid_cur = msr.lo & 0x3f;
@ -377,7 +380,8 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
timeout = wait_cpu_state(bsp_apicid, 1); timeout = wait_cpu_state(bsp_apicid, 1);
if (timeout) { if (timeout) {
print_initcpu8("fidvid_ap_stage1: time out while reading from BSP on ", apicid); printk(BIOS_DEBUG, "fidvid_ap_stage1: time out while reading"
" from BSP on %02x\n", apicid);
} }
/* send signal to BSP about this AP max fid and vid */ /* send signal to BSP about this AP max fid and vid */
/* AP at state 1 that sent our fid and vid */ /* AP at state 1 that sent our fid and vid */
@ -387,14 +391,15 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
loop = 1000000; loop = 1000000;
while (--loop > 0) { while (--loop > 0) {
/* remote read BSP signal that include vid/fid that need to set */ /* remote read BSP signal that include vid/fid that need to set */
if (lapic_remote_read(bsp_apicid, LAPIC_MSG_REG, &readback)!=0) if (lapic_remote_read(bsp_apicid, LAPIC_MSG_REG, &readback) !=
0)
continue; continue;
if (((readback >> 24) & 0xff) == apicid) if (((readback >> 24) & 0xff) == apicid)
break; /* it is this cpu turn */ break; /* it is this cpu turn */
} }
if (loop > 0) { if (loop > 0) {
#if K8_SET_FIDVID_ONE_BY_ONE == 1 #if SET_FIDVID_ONE_BY_ONE == 1
readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP
#else #else
readback = set_fidvid_without_init(readback & 0xffff00); // this AP readback = set_fidvid_without_init(readback & 0xffff00); // this AP
@ -404,25 +409,26 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
/* AP at state that We set the requested fid/vid */ /* AP at state that We set the requested fid/vid */
send = (apicid << 24) | (readback & 0x00ffff00); send = (apicid << 24) | (readback & 0x00ffff00);
} else { } else {
print_initcpu8("fidvid_ap_stage2: time out while reading from BSP on ", apicid); printk(BIOS_DEBUG, "%s: time out while reading from BSP on %02x",
__func__, apicid);
} }
lapic_write(LAPIC_MSG_REG, send | 2); lapic_write(LAPIC_MSG_REG, send | 2);
timeout = wait_cpu_state(bsp_apicid, 3); timeout = wait_cpu_state(bsp_apicid, 3);
if (timeout) { if (timeout) {
print_initcpu8("fidvid_ap_stage3: time out while reading from BSP on ", apicid); printk(BIOS_DEBUG, "%s: time out while reading from BSP on %02x",
__func__, apicid);
} }
} }
static unsigned calc_common_fidvid(unsigned fidvid, unsigned fidvidx) static u32 calc_common_fidvid(unsigned fidvid, unsigned fidvidx)
{ {
/* FIXME: need to check the change path to verify if it is reachable /* FIXME: need to check the change path to verify if it is reachable
* when common fid is small than 1.6G */ * when common fid is small than 1.6G */
if ((fidvid & 0xff00) <= (fidvidx & 0xff00)) { if ((fidvid & 0xff00) <= (fidvidx & 0xff00)) {
return fidvid; return fidvid;
} } else {
else {
return fidvidx; return fidvidx;
} }
} }
@ -431,10 +437,10 @@ struct fidvid_st {
unsigned common_fidvid; unsigned common_fidvid;
}; };
static void init_fidvid_bsp_stage1(unsigned ap_apicid, void *gp ) static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp)
{ {
unsigned readback = 0; u32 readback = 0;
unsigned timeout = 1; u32 timeout = 1;
struct fidvid_st *fvp = gp; struct fidvid_st *fvp = gp;
int loop; int loop;
@ -450,8 +456,10 @@ static void init_fidvid_bsp_stage1(unsigned ap_apicid, void *gp )
break; /* target ap is in stage 1 */ break; /* target ap is in stage 1 */
} }
} }
if (timeout) { if (timeout) {
print_initcpu8("fidvid_bsp_stage1: time out while reading from ap ", ap_apicid); printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n",
__func__, ap_apicid);
return; return;
} }
@ -486,18 +494,18 @@ static void init_fidvid_bsp_stage2(unsigned ap_apicid, void *gp)
} }
if (timeout) { if (timeout) {
print_initcpu8("fidvid_bsp_stage2: time out while reading from ap ", ap_apicid); printk(BIOS_DEBUG, "%s: time out while reading from ap %02x",
__func__, ap_apicid);
return; return;
} }
print_debug_fv("\treadback=", readback); print_debug_fv("\treadback=", readback);
} }
#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 #if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
struct ap_apicid_st { struct ap_apicid_st {
unsigned num; u32 num;
unsigned apicid[16]; /* 8 way dual core need 16 */ unsigned apicid[16]; /* 8 way dual core need 16 */
/* FIXME: 32 node quad core, may need 128 */
}; };
static void store_ap_apicid(unsigned ap_apicid, void *gp) static void store_ap_apicid(unsigned ap_apicid, void *gp)
@ -511,12 +519,12 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp)
static void init_fidvid_bsp(unsigned bsp_apicid) static void init_fidvid_bsp(unsigned bsp_apicid)
{ {
uint32_t vid_max; u32 vid_max;
uint32_t fid_max; u32 fid_max;
struct fidvid_st fv; struct fidvid_st fv;
#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 #if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
struct ap_apicid_st ap_apicidx; struct ap_apicid_st ap_apicidx;
unsigned i; unsigned i;
#endif #endif
@ -535,7 +543,6 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
vid_max = ((msr.hi >> (48 - 32)) & 0x3f); //max vid vid_max = ((msr.hi >> (48 - 32)) & 0x3f); //max vid
fv.common_fidvid = (fid_max << 8) | (vid_max << 16); fv.common_fidvid = (fid_max << 8) | (vid_max << 16);
/* for all APs (We know the APIC ID of all APs even the APIC ID is lifted) /* for all APs (We know the APIC ID of all APs even the APIC ID is lifted)
* remote read from AP about max fid/vid */ * remote read from AP about max fid/vid */
@ -544,19 +551,18 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
/* calculate the common max fid/vid that could be used for /* calculate the common max fid/vid that could be used for
* all APs and BSP */ * all APs and BSP */
#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 #if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
ap_apicidx.num = 0; ap_apicidx.num = 0;
for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx); for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx);
for (i = 0; i < ap_apicidx.num; i++) { for (i = 0; i < ap_apicidx.num; i++) {
init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
} }
#else #else
for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
#endif #endif
#if 0 #if 0
unsigned fid, vid; unsigned fid, vid;
/* Can we use max only? So we can only set fid in one around, /* Can we use max only? So we can only set fid in one around,
@ -581,7 +587,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
#endif #endif
#if K8_SET_FIDVID_ONE_BY_ONE == 1 #if SET_FIDVID_ONE_BY_ONE == 1
/* set BSP fid and vid */ /* set BSP fid and vid */
print_debug_fv("bsp apicid=", bsp_apicid); print_debug_fv("bsp apicid=", bsp_apicid);
fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);
@ -595,15 +601,15 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
fv.common_fidvid &= 0xffff00; fv.common_fidvid &= 0xffff00;
/* set state 2 allow is in init_fidvid_bsp_stage2 */ /* set state 2 allow is in init_fidvid_bsp_stage2 */
#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 #if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
for (i = 0; i < ap_apicidx.num; i++) { for (i = 0; i < ap_apicidx.num; i++) {
init_fidvid_bsp_stage2(ap_apicidx.apicid[i], &fv); init_fidvid_bsp_stage2(ap_apicidx.apicid[i], &fv);
} }
#else #else
for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv); for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv);
#endif #endif
#if K8_SET_FIDVID_ONE_BY_ONE == 0 #if SET_FIDVID_ONE_BY_ONE == 0
/* set BSP fid and vid */ /* set BSP fid and vid */
print_debug_fv("bsp apicid=", bsp_apicid); print_debug_fv("bsp apicid=", bsp_apicid);
fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);
@ -616,7 +622,5 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
/* here wait a while, so last ap could read pack, and stop it, don't /* here wait a while, so last ap could read pack, and stop it, don't
* call init_timer too early or just don't use init_timer */ * call init_timer too early or just don't use init_timer */
} }
#endif #endif

16
src/cpu/amd/model_fxx/init_cpus.c
View File

@ -1,17 +1,17 @@
//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
#ifndef K8_SET_FIDVID #ifndef SET_FIDVID
#if CONFIG_K8_REV_F_SUPPORT == 0 #if CONFIG_K8_REV_F_SUPPORT == 0
#define K8_SET_FIDVID 0 #define SET_FIDVID 0
#else #else
// for rev F, need to set FID to max // for rev F, need to set FID to max
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
#endif #endif
#endif #endif
#ifndef K8_SET_FIDVID_CORE0_ONLY #ifndef SET_FIDVID_CORE0_ONLY
/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, so may don't need to do twice*/ /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, so may don't need to do twice*/
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#endif #endif
static inline void print_initcpu8 (const char *strval, unsigned val) static inline void print_initcpu8 (const char *strval, unsigned val)
@ -149,7 +149,7 @@ static inline int lapic_remote_read(int apicid, int reg, unsigned *pvalue)
#define LAPIC_MSG_REG 0x380 #define LAPIC_MSG_REG 0x380
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid); static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid);
#endif #endif
@ -302,8 +302,8 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
if(apicid != bsp_apicid) { if(apicid != bsp_apicid) {
unsigned timeout=1; unsigned timeout=1;
unsigned loop = 100; unsigned loop = 100;
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
#if (CONFIG_LOGICAL_CPUS == 1) && (K8_SET_FIDVID_CORE0_ONLY == 1) #if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1)
if(id.coreid == 0 ) // only need set fid for core0 if(id.coreid == 0 ) // only need set fid for core0
#endif #endif
init_fidvid_ap(bsp_apicid, apicid); init_fidvid_ap(bsp_apicid, apicid);

2
src/mainboard/amd/dbm690t/romstage.c
View File

@ -18,7 +18,7 @@
*/ */
#define RAMINIT_SYSINFO 1 #define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1

2
src/mainboard/amd/mahogany/romstage.c
View File

@ -18,7 +18,7 @@
*/ */
#define RAMINIT_SYSINFO 1 #define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1

6
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -34,8 +34,8 @@
#define FAM10_ALLOCATE_IO_RANGE 0 #define FAM10_ALLOCATE_IO_RANGE 0
//used by init_cpus and fidvid //used by init_cpus and fidvid
#define FAM10_SET_FIDVID 1 #define SET_FIDVID 1
#define FAM10_SET_FIDVID_CORE_RANGE 0 #define SET_FIDVID_CORE_RANGE 0
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
@ -208,7 +208,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup(); rs780_early_setup();
sb700_early_setup(); sb700_early_setup();
#if FAM10_SET_FIDVID == 1 #if SET_FIDVID == 1
msr = rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);

2
src/mainboard/amd/pistachio/romstage.c
View File

@ -18,7 +18,7 @@
*/ */
#define RAMINIT_SYSINFO 1 #define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1

8
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -10,9 +10,9 @@
//#define K8_ALLOCATE_IO_RANGE 1 //#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid //used by init_cpus and fidvid
#define K8_SET_FIDVID 0 #define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0 //if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -164,7 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset; int needs_reset;
unsigned bsp_apicid = 0; unsigned bsp_apicid = 0;
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
struct cpuid_result cpuid1; struct cpuid_result cpuid1;
#endif #endif
@ -228,7 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif #endif
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
/* Check to see if processor is capable of changing FIDVID */ /* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007); cpuid1 = cpuid(0x80000007);

6
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -34,8 +34,8 @@
#define FAM10_ALLOCATE_IO_RANGE 0 #define FAM10_ALLOCATE_IO_RANGE 0
//used by init_cpus and fidvid //used by init_cpus and fidvid
#define FAM10_SET_FIDVID 1 #define SET_FIDVID 1
#define FAM10_SET_FIDVID_CORE_RANGE 0 #define SET_FIDVID_CORE_RANGE 0
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
@ -211,7 +211,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38); post_code(0x38);
#if FAM10_SET_FIDVID == 1 #if SET_FIDVID == 1
msr = rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);

2
src/mainboard/asrock/939a785gmh/romstage.c
View File

@ -19,7 +19,7 @@
*/ */
#define RAMINIT_SYSINFO 1 #define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1

4
src/mainboard/asus/a8v-e_se/romstage.c
View File

@ -32,10 +32,10 @@ unsigned int get_sbdn(unsigned bus);
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
/* Used by init_cpus and fidvid */ /* Used by init_cpus and fidvid */
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
/* If we want to wait for core1 done before DQS training, set it to 0. */ /* If we want to wait for core1 done before DQS training, set it to 0. */
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>

4
src/mainboard/asus/m2v-mx_se/romstage.c
View File

@ -32,10 +32,10 @@ unsigned int get_sbdn(unsigned bus);
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
/* Used by init_cpus and fidvid */ /* Used by init_cpus and fidvid */
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
/* If we want to wait for core1 done before DQS training, set it to 0. */ /* If we want to wait for core1 done before DQS training, set it to 0. */
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0

6
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View File

@ -32,9 +32,9 @@
#endif #endif
//used by init_cpus and fidvid //used by init_cpus and fidvid
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0 //if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -235,7 +235,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */ /* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
{ {
msr_t msr; msr_t msr;

6
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -30,9 +30,9 @@
#endif #endif
//used by init_cpus and fidvid //used by init_cpus and fidvid
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0 //if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -249,7 +249,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */ /* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
{ {
msr_t msr; msr_t msr;

6
src/mainboard/hp/dl145_g3/romstage.c
View File

@ -36,9 +36,9 @@
#endif #endif
//used by init_cpus and fidvid //used by init_cpus and fidvid
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0 //if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -252,7 +252,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
bcm5785_early_setup(); bcm5785_early_setup();
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);

6
src/mainboard/iwill/dk8_htx/romstage.c
View File

@ -10,9 +10,9 @@
//#define K8_ALLOCATE_IO_RANGE 1 //#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid //used by init_cpus and fidvid
#define K8_SET_FIDVID 0 #define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0 //if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -188,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */ /* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
{ {
msr_t msr; msr_t msr;

6
src/mainboard/iwill/dk8s2/romstage.c
View File

@ -10,9 +10,9 @@
//#define K8_ALLOCATE_IO_RANGE 1 //#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid //used by init_cpus and fidvid
#define K8_SET_FIDVID 0 #define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0 //if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -188,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */ /* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
{ {
msr_t msr; msr_t msr;

6
src/mainboard/iwill/dk8x/romstage.c
View File

@ -10,9 +10,9 @@
//#define K8_ALLOCATE_IO_RANGE 1 //#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid //used by init_cpus and fidvid
#define K8_SET_FIDVID 0 #define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0 //if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -188,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */ /* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
{ {
msr_t msr; msr_t msr;

2
src/mainboard/kontron/kt690/romstage.c
View File

@ -19,7 +19,7 @@
*/ */
#define RAMINIT_SYSINFO 1 #define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1

6
src/mainboard/msi/ms7260/romstage.c
View File

@ -33,10 +33,10 @@
#endif #endif
/* Used by init_cpus and fidvid. */ /* Used by init_cpus and fidvid. */
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
/* If we want to wait for core1 done before DQS training, set it to 0. */ /* If we want to wait for core1 done before DQS training, set it to 0. */
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -214,7 +214,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Set up chains and store link pair for optimization later. */ /* Set up chains and store link pair for optimization later. */
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
{ {
msr_t msr = rdmsr(0xc0010042); msr_t msr = rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug("begin msr fid, vid ");

6
src/mainboard/msi/ms9185/romstage.c
View File

@ -35,9 +35,9 @@
//#define K8_ALLOCATE_IO_RANGE 1 //#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid //used by init_cpus and fidvid
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0 //if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
@ -221,7 +221,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif #endif
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
{ {
msr_t msr; msr_t msr;

4
src/mainboard/msi/ms9282/romstage.c
View File

@ -31,9 +31,9 @@
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
//used by init_cpus and fidvid //used by init_cpus and fidvid
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0 //if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>

6
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -30,8 +30,8 @@
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1
#endif #endif
#define FAM10_SET_FIDVID 1 #define SET_FIDVID 1
#define FAM10_SET_FIDVID_CORE_RANGE 0 #define SET_FIDVID_CORE_RANGE 0
#define DBGP_DEFAULT 7 #define DBGP_DEFAULT 7
@ -248,7 +248,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38); post_code(0x38);
#if FAM10_SET_FIDVID == 1 #if SET_FIDVID == 1
msr = rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

6
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -30,9 +30,9 @@
#endif #endif
//used by init_cpus and fidvid //used by init_cpus and fidvid
#define K8_SET_FIDVID 0 #define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0 //if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -236,7 +236,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */ /* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
{ {
msr_t msr; msr_t msr;

6
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -27,9 +27,9 @@
#endif #endif
// used by init_cpus and fidvid // used by init_cpus and fidvid
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0 //if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -295,7 +295,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */ /* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
{ {
msr_t msr; msr_t msr;

6
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -30,9 +30,9 @@
#endif #endif
//used by init_cpus and fidvid //used by init_cpus and fidvid
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0 //if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -223,7 +223,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */ /* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
{ {
msr_t msr; msr_t msr;

6
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -30,8 +30,8 @@
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1
#endif #endif
#define FAM10_SET_FIDVID 1 #define SET_FIDVID 1
#define FAM10_SET_FIDVID_CORE_RANGE 0 #define SET_FIDVID_CORE_RANGE 0
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
@ -235,7 +235,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38); post_code(0x38);
#if FAM10_SET_FIDVID == 1 #if SET_FIDVID == 1
msr = rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);

6
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -30,8 +30,8 @@
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1
#endif #endif
#define FAM10_SET_FIDVID 1 #define SET_FIDVID 1
#define FAM10_SET_FIDVID_CORE_RANGE 0 #define SET_FIDVID_CORE_RANGE 0
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
@ -280,7 +280,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38); post_code(0x38);
#if FAM10_SET_FIDVID == 1 #if SET_FIDVID == 1
msr = rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);

2
src/mainboard/technexion/tim5690/romstage.c
View File

@ -18,7 +18,7 @@
*/ */
#define RAMINIT_SYSINFO 1 #define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1

2
src/mainboard/technexion/tim8690/romstage.c
View File

@ -18,7 +18,7 @@
*/ */
#define RAMINIT_SYSINFO 1 #define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1 #define SET_FIDVID 1
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1

6
src/mainboard/tyan/s2912/romstage.c
View File

@ -30,9 +30,9 @@
#endif #endif
//used by init_cpus and fidvid //used by init_cpus and fidvid
#define K8_SET_FIDVID 0 #define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0 //if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1 #define SET_FIDVID_CORE0_ONLY 1
#if CONFIG_K8_REV_F_SUPPORT == 1 #if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
@ -232,7 +232,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */ /* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1 #if SET_FIDVID == 1
{ {
msr_t msr; msr_t msr;

6
src/mainboard/tyan/s2912_fam10/romstage.c
View File

@ -30,8 +30,8 @@
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1
#endif #endif
#define FAM10_SET_FIDVID 1 #define SET_FIDVID 1
#define FAM10_SET_FIDVID_CORE_RANGE 0 #define SET_FIDVID_CORE_RANGE 0
#define DBGP_DEFAULT 7 #define DBGP_DEFAULT 7
@ -243,7 +243,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38); post_code(0x38);
#if FAM10_SET_FIDVID == 1 #if SET_FIDVID == 1
msr = rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);