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Winbond W83627HF: Use existing functions instead of open-coding.

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Use w83627hf_set_clksel_48() where needed instead or open-coding the same
functionality, and also use w83627hf_enable_serial() instead of 
w83627hf_enable_dev() (which does exactly the same, but isn't wrapped in the
enter/exit config mode functions).

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
2010-12-06 18:17:01 +00:00
parent 29cb06abca
commit 9b9791c29d
11 changed files with 34 additions and 47 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/mainboard/msi/ms6178/romstage.c
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@@ -33,18 +33,15 @@
#include <lib.h> #include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
void enable_smbus(void); void enable_smbus(void);
int smbus_read_byte(u8 device, u8 address); int smbus_read_byte(u8 device, u8 address);
void main(unsigned long bist) void main(unsigned long bist)
{ {
/* FIXME */ w83627hf_set_clksel_48(DUMMY_DEV);
outb(0x87, 0x2e);
outb(0x87, 0x2e);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
outb(0x87, 0xaa);
uart_init(); uart_init();
console_init(); console_init();

7
src/mainboard/supermicro/h8dme/romstage.c
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@@ -48,6 +48,7 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
static void memreset(int controllers, const struct mem_controller *ctrl) { } static void memreset(int controllers, const struct mem_controller *ctrl) { }
@@ -193,10 +194,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (bist == 0) if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
pnp_enter_ext_func_mode(SERIAL_DEV); w83627hf_set_clksel_48(DUMMY_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
uart_init(); uart_init();
console_init(); console_init();

7
src/mainboard/supermicro/h8dmr/romstage.c
View File

@@ -51,6 +51,7 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
static void memreset(int controllers, const struct mem_controller *ctrl) { } static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -122,10 +123,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (bist == 0) if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
pnp_enter_ext_func_mode(SERIAL_DEV); w83627hf_set_clksel_48(DUMMY_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
uart_init(); uart_init();
console_init(); console_init();

7
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@@ -50,6 +50,7 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
static void activate_spd_rom(const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -125,10 +126,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x32); post_code(0x32);
pnp_enter_ext_func_mode(SERIAL_DEV); w83627hf_set_clksel_48(DUMMY_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
uart_init(); uart_init();
console_init(); console_init();

7
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@@ -50,6 +50,7 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
static inline void activate_spd_rom(const struct mem_controller *ctrl) static inline void activate_spd_rom(const struct mem_controller *ctrl)
{ {
@@ -176,10 +177,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x32); post_code(0x32);
pnp_enter_ext_func_mode(SERIAL_DEV); w83627hf_set_clksel_48(DUMMY_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
uart_init(); uart_init();
console_init(); console_init();

10
src/mainboard/supermicro/x6dai_g/romstage.c
View File

@@ -16,13 +16,14 @@
#include "debug.c" #include "debug.c"
#include "watchdog.c" #include "watchdog.c"
#include "reset.c" #include "reset.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "northbridge/intel/e7525/memory_initialized.c" #include "northbridge/intel/e7525/memory_initialized.c"
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <spd.h> #include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
#define DEVPRES_CONFIG ( \ #define DEVPRES_CONFIG ( \
DEVPRES_D1F0 | \ DEVPRES_D1F0 | \
@@ -63,11 +64,8 @@ static void main(unsigned long bist)
skip_romstage(); skip_romstage();
} }
/* Setup the console */ w83627hf_set_clksel_48(DUMMY_DEV);
outb(0x87,0x2e); w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
outb(0x87,0x2e);
pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();

10
src/mainboard/supermicro/x6dhe_g/romstage.c
View File

@@ -17,13 +17,14 @@
#include "watchdog.c" #include "watchdog.c"
#include "reset.c" #include "reset.c"
#include "x6dhe_g_fixups.c" #include "x6dhe_g_fixups.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "northbridge/intel/e7520/memory_initialized.c" #include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <spd.h> #include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
#define DEVPRES_CONFIG ( \ #define DEVPRES_CONFIG ( \
DEVPRES_D1F0 | \ DEVPRES_D1F0 | \
@@ -60,11 +61,8 @@ static void main(unsigned long bist)
skip_romstage(); skip_romstage();
} }
/* Setup the console */ w83627hf_set_clksel_48(DUMMY_DEV);
outb(0x87,0x2e); w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
outb(0x87,0x2e);
pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();

10
src/mainboard/supermicro/x6dhr_ig/romstage.c
View File

@@ -15,13 +15,14 @@
#include "watchdog.c" #include "watchdog.c"
#include "reset.c" #include "reset.c"
#include "x6dhr_fixups.c" #include "x6dhr_fixups.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "northbridge/intel/e7520/memory_initialized.c" #include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <spd.h> #include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
#define DEVPRES_CONFIG ( \ #define DEVPRES_CONFIG ( \
DEVPRES_D0F0 | \ DEVPRES_D0F0 | \
@@ -59,11 +60,8 @@ static void main(unsigned long bist)
skip_romstage(); skip_romstage();
} }
/* Setup the console */ w83627hf_set_clksel_48(DUMMY_DEV);
outb(0x87,0x2e); w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
outb(0x87,0x2e);
pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();

10
src/mainboard/supermicro/x6dhr_ig2/romstage.c
View File

@@ -15,13 +15,14 @@
#include "watchdog.c" #include "watchdog.c"
#include "reset.c" #include "reset.c"
#include "x6dhr2_fixups.c" #include "x6dhr2_fixups.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "northbridge/intel/e7520/memory_initialized.c" #include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <spd.h> #include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
#define DEVPRES_CONFIG ( \ #define DEVPRES_CONFIG ( \
DEVPRES_D0F0 | \ DEVPRES_D0F0 | \
@@ -59,11 +60,8 @@ static void main(unsigned long bist)
skip_romstage(); skip_romstage();
} }
/* Setup the console */ w83627hf_set_clksel_48(DUMMY_DEV);
outb(0x87,0x2e); w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
outb(0x87,0x2e);
pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();

3
src/mainboard/via/epia-m700/romstage.c
View File

@@ -46,6 +46,7 @@
#include "superio/winbond/w83697hf/w83697hf_early_serial.c" #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
/* /*
* This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
@@ -384,7 +385,7 @@ void main(unsigned long bist)
*/ */
pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
/* EmbedComInit(); */ /* EmbedComInit(); */
w83697hf_set_clksel_48(SERIAL_DEV); w83697hf_set_clksel_48(DUMMY_DEV);
w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init(); uart_init();
/* enable_vx800_serial(); */ /* enable_vx800_serial(); */

3
src/mainboard/via/epia-n/romstage.c
View File

@@ -38,6 +38,7 @@
#include <spd.h> #include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
static const struct mem_controller ctrl = { static const struct mem_controller ctrl = {
.d0f0 = 0x0000, .d0f0 = 0x0000,
@@ -109,7 +110,7 @@ static void main(unsigned long bist)
/* Enable multifunction for northbridge. */ /* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01); pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
w83697hf_set_clksel_48(SERIAL_DEV); w83697hf_set_clksel_48(DUMMY_DEV);
w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();