intel/sandybridge: Use common ACPI S3 recovery

Fix regression, S3 resume not working on sandy/ivy after commit
   9d6f365 ACPI S3: Remove HIGH_MEMORY_SAVE where possible

There is some 20ms delay with ACPI S3 wakeup time due to MTRR setup
being done after the backup copy. Moving to RELOCATABLE_RAMSTAGE fixes
this delay by removing need of this backup entirely.

Change-Id: Ib72ff914f5dfef8611f5f6cf9687495779013b02
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15248
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/intel/model_206ax/cache_as_ram.inc

@@ -17,8 +17,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
-#include <arch/acpi.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
 
 /* The full cache-as-ram size includes the cache-as-ram portion from coreboot
  * and the space used by the reference code. These 2 values combined should
@@ -284,27 +282,6 @@ before_romstage:
 
 	post_code(0x3c)
 
-#if CONFIG_HAVE_ACPI_RESUME
-	movl	CBMEM_BOOT_MODE, %eax
-	cmpl	$0x2, %eax // Resume?
-	jne	__acpi_resume_backup_done
-
-	/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
-	 * through stage 2. We could keep stuff like stack and heap in high
-	 * tables memory completely, but that's a wonderful clean up task for
-	 * another day.
-	 */
-	cld
-	movl	$CONFIG_RAMBASE, %esi
-	movl	CBMEM_RESUME_BACKUP, %edi
-	movl	$HIGH_MEMORY_SAVE >> 2, %ecx
-	rep	movsl
-
-__acpi_resume_backup_done:
-#endif
-
-	post_code(0x3d)
-
 __main:
 	post_code(POST_PREPARE_RAMSTAGE)
 	cld			/* Clear direction flag. */