- Updates to config.g so that it works more reliably and has initial support
for paths - Renamed some configuration variables SMP -> CONFIG_SMP MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS - Removed some dead configuration variables MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS SMP -> CONFIG_SMP FINAL_MAINBOARD_FIXUP SIO_BASE SIO_SYSTEM_CLK_INPUT NO_KEYBOARD USE_NORMAL_IMAGE SERIAL_CONSOLE USE_ELF_BOOT ENABLE_FIXED_AND_VARIABLE_MTRRS START_CPU_SEG DISABLE_WATCHDOG ENABLE_IOMMU AMD8111_DEV - Removed some assembly files that are no longer needed killed src/southbridge/amd/amd8111/smbus.inc killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc killed src/ram/ramtest.inc - Updates to config.g so that it works more reliably and has initial support for paths - Renamed some configuration variables SMP -> CONFIG_SMP MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS - Removed some dead configuration variables MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS SMP -> CONFIG_SMP FINAL_MAINBOARD_FIXUP SIO_BASE SIO_SYSTEM_CLK_INPUT NO_KEYBOARD USE_NORMAL_IMAGE SERIAL_CONSOLE USE_ELF_BOOT ENABLE_FIXED_AND_VARIABLE_MTRRS START_CPU_SEG DISABLE_WATCHDOG ENABLE_IOMMU AMD8111_DEV - Removed some assembly files that are no longer needed killed src/southbridge/amd/amd8111/smbus.inc killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc killed src/ram/ramtest.inc killed src/sdram/generic_dump_spd.inc killed src/sdram/generic_dump_spd.inc - Updated the arima/hdama to build with the new configuration system - Updated config.g to list all of the variables with make echo git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
@@ -20,7 +20,7 @@ static void remove_logical_cpus(unsigned long *processor_map)
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if (disable_logical_cpus) {
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/* disable logical cpus */
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int cnt;
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for(cnt=MAX_PHYSICAL_CPUS;cnt<MAX_CPUS;cnt++)
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for(cnt=CONFIG_MAX_PHYSICAL_CPUS;cnt<CONFIG_MAX_CPUS;cnt++)
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processor_map[cnt]=0;
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printk_debug("logical cpus disabled\n");
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}
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@@ -268,7 +268,7 @@ void *smp_write_floating_table(unsigned long addr);
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unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map);
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/* A table (per mainboard) listing the initial apicid of each cpu. */
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extern unsigned long initial_apicid[MAX_CPUS];
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extern unsigned long initial_apicid[CONFIG_MAX_CPUS];
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#else /* HAVE_MP_TABLE */
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static inline
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@@ -45,10 +45,10 @@ _start:
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movl APIC_ID(%edi), %eax
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shrl $24, %eax
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/* Get the cpu index (MAX_CPUS on error) */
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/* Get the cpu index (CONFIG_MAX_CPUS on error) */
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movl $-4, %ebx
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1: addl $4, %ebx
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cmpl $(MAX_CPUS << 2), %ebx
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cmpl $(CONFIG_MAX_CPUS << 2), %ebx
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je 2
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cmpl %eax, initial_apicid(%ebx)
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jne 1b
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@@ -108,7 +108,7 @@ void smp_write_processors(struct mp_config_table *mc,
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cpuid(1, &eax, &ebx, &ecx, &edx);
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cpu_features = eax;
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cpu_feature_flags = edx;
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for(i = 0; i < MAX_CPUS; i++) {
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for(i = 0; i < CONFIG_MAX_CPUS; i++) {
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unsigned long cpu_apicid = initial_apicid[i];
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unsigned long cpu_flag;
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if(initial_apicid[i]==-1)
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@@ -48,10 +48,10 @@ _secondary_start:
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movl (APIC_ID + APIC_DEFAULT_BASE), %edi
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shrl $24, %edi
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/* Get the cpu index (MAX_CPUS on error) */
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/* Get the cpu index (CONFIG_MAX_CPUS on error) */
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movl $-4, %ebx
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1: addl $4, %ebx
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cmpl $(MAX_CPUS << 2), %ebx
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cmpl $(CONFIG_MAX_CPUS << 2), %ebx
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je 2
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cmpl %edi, initial_apicid(%ebx)
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jne 1b
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@@ -5,13 +5,6 @@
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#include <string.h>
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#include <console/console.h>
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#ifndef START_CPU_SEG
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#define START_CPU_SEG 0x90000
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#endif
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#if (START_CPU_SEG&0xffff) != 0
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#error START_CPU_SEG must be 64k aligned
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#endif
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static inline void hlt(void)
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{
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asm("hlt");
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@@ -26,7 +19,7 @@ unsigned long this_processors_id(void)
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int processor_index(unsigned long apicid)
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{
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int i;
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for(i = 0; i < MAX_CPUS; i++) {
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for(i = 0; i < CONFIG_MAX_CPUS; i++) {
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if (initial_apicid[i] == apicid) {
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return i;
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}
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@@ -230,7 +223,7 @@ void startup_other_cpus(unsigned long *processor_map)
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int i;
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/* Assume the cpus are densly packed by apicid */
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for(i = 0; i < MAX_CPUS; i++) {
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for(i = 0; i < CONFIG_MAX_CPUS; i++) {
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unsigned long cpu_apicid = initial_apicid[i];
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if (cpu_apicid == -1) {
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printk_err("CPU %d not found\n",i);
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@@ -60,7 +60,7 @@ it with the version available from LANL.
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* info per processor at some point. I hope we don't need
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* anything more complex than an int.
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*/
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static unsigned long processor_map[MAX_CPUS];
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static unsigned long processor_map[CONFIG_MAX_CPUS];
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static struct mem_range *get_ramsize(void)
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{
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@@ -114,7 +114,7 @@ static void wait_for_other_cpus(void)
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}
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active_count = atomic_read(&active_cpus);
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}
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for(i = 0; i < MAX_CPUS; i++) {
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for(i = 0; i < CONFIG_MAX_CPUS; i++) {
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if (!(processor_map[i] & CPU_ENABLED)) {
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printk_err("CPU %d did not initialize!\n", i);
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processor_map[i] = 0;
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@@ -117,7 +117,7 @@ define OBJCOPY
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comment "Objcopy command"
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end
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define LINUXBIOS_VERSION
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default "1.1.0"
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default "1.1.1"
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export always
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comment "LinuxBIOS version"
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end
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@@ -148,7 +148,7 @@ define LINUXBIOS_COMPILE_HOST
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end
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define LINUXBIOS_COMPILE_DOMAIN
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default ""
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default "$(shell dnsdomainname)"
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export always
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comment "Build domain name"
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end
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@@ -183,16 +183,10 @@ define HAVE_FALLBACK_BOOT
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comment "Set if fallback booting required"
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end
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define USE_FALLBACK_IMAGE
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default 0
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default 1
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export used
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comment "Set to build a fallback image"
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end
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define USE_NORMAL_IMAGE
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format "%d"
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default {!USE_FALLBACK_IMAGE}
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export used
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comment "Set to build a normal image"
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end
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define FALLBACK_SIZE
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default 65536
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format "0x%x"
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@@ -277,16 +271,16 @@ define CACHE_RAM_SIZE
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comment "Size of cache when using it for temporary RAM"
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end
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define XIP_ROM_BASE
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default 0xffff8000
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default 0
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format "0x%x"
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export used
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comment "base address of range of ROM that can be cached to speed up linuxBIOS"
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comment "Start address of area to cache during LinuxBIOS execution directly from ROM"
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end
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define XIP_ROM_SIZE
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default 0x8000
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default 0
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format "0x%x"
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export used
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comment "size of range of ROM that can be cached to speed up linuxBIOS"
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comment "Size of area to cache during LinuxBIOS execution directly from ROM"
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end
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define CONFIG_COMPRESS
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default 1
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@@ -348,14 +342,8 @@ end
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define CONFIG_CONSOLE_SERIAL8250
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default 0
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export always
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comment "Log messages to serial 8250 console"
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comment "Log messages to 8250 uart based serial console"
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end
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define SERIAL_CONSOLE
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default none
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export used
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comment "Log messages to serial console"
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end
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define DEFAULT_CONSOLE_LOGLEVEL
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default 7
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export always
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@@ -373,17 +361,25 @@ define NO_POST
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export always
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comment "Disable POST codes"
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end
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define TTYS0_BASE
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default 0x3f8
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export always
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comment "Base address for 8250 uart for the serial console"
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end
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define TTYS0_BAUD
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default 115200
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export always
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comment "Default baud rate for serial console"
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end
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define NO_KEYBOARD
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default none
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export never
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comment "Set if we don't have a keyboard"
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end
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define TTYS0_LCS
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default 0x3
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export always
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comment "Default flow control settings for the 8250 serial console uart"
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end
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###############################################
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# Mainboard options
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###############################################
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@@ -403,11 +399,6 @@ define MAINBOARD_VENDOR
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export always
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comment "Vendor of mainboard"
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end
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define FINAL_MAINBOARD_FIXUP
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default 0
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export used
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comment "Do final mainboard fixups"
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end
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define CONFIG_SYS_CLK_FREQ
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default none
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export used
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@@ -426,23 +417,18 @@ end
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define CONFIG_MAX_CPUS
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default 1
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export always
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comment "Config CPU count for this machine"
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comment "Maximum CPU count for this machine"
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end
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define MAX_CPUS
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default 1
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export always
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comment "CPU count for this machine"
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end
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define CONFIG_LOGICAL_CPUS
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default 1
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export always
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comment "Logical CPU count for this machine"
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end
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define MAX_PHYSICAL_CPUS
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default 1
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define CONFIG_MAX_PHYSICAL_CPUS
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default {CONFIG_MAX_CPUS}
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export always
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comment "Physical CPU count for this machine"
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end
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define CONFIG_LOGICAL_CPUS
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default 0
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export always
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comment "Should multiple cpus per die be enabled?"
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end
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define HAVE_MP_TABLE
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default none
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export always
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@@ -453,11 +439,6 @@ end
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# Boot options
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###############################################
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define USE_ELF_BOOT
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default none
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export always
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comment "Use ELF boot loader"
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end
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define CONFIG_IDE_STREAM
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default 0
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export always
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@@ -540,21 +521,6 @@ define SMBUS_MEM_DEVICE_INC
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comment "Increment value SMBUS"
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end
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###############################################
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# SuperIO options
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###############################################
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define SIO_BASE
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default none
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export used
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comment "Superio base address"
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end
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define SIO_SYSTEM_CLK_INPUT
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default none
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export used
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comment "Superio CLK input default"
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end
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###############################################
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# Misc options
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###############################################
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@@ -569,57 +535,30 @@ define MEMORY_HOLE
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export used
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comment "Set to deal with memory hole"
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end
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define ENABLE_FIXED_AND_VARIABLE_MTRRS
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default none
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export used
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comment "Enable fixed and variable mtrrs"
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end
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define START_CPU_SEG
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default 0xf0000
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format "0x%x"
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export always
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comment "Start CPU segment"
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end
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||||
define MAX_REBOOT_CNT
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default 2
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default 3
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export always
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comment "Set maximum reboots"
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end
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define DISABLE_WATCHDOG
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default {MAXIMUM_CONSOLE_LOGLEVEL >= 8}
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export used
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comment "Disable watchdog if we're doing lots of output"
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end
|
||||
define ENABLE_IOMMU
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default 1
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export used
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comment "Enable IOMMU aperture"
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end
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||||
|
||||
###############################################
|
||||
# Misc device options
|
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###############################################
|
||||
|
||||
define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
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default none
|
||||
default 0
|
||||
export used
|
||||
comment ""
|
||||
comment "Use timer2 to callibrate the x86 time stamp counter"
|
||||
end
|
||||
define INTEL_PPRO_MTRR
|
||||
default none
|
||||
export always
|
||||
comment ""
|
||||
end
|
||||
define AMD8111_DEV
|
||||
default 0x3800
|
||||
format "0x%x"
|
||||
export used
|
||||
comment ""
|
||||
end
|
||||
define CONFIG_UDELAY_TSC
|
||||
default 0
|
||||
export used
|
||||
comment ""
|
||||
comment "Implement udelay with the x86 time stamp counter"
|
||||
end
|
||||
|
||||
###############################################
|
||||
|
@@ -87,7 +87,7 @@ SECTIONS
|
||||
_stack = .;
|
||||
.stack . : {
|
||||
/* Reserve a stack for each possible cpu, +1 extra */
|
||||
. = ((MAX_CPUS * STACK_SIZE) + STACK_SIZE) ;
|
||||
. = ((CONFIG_MAX_CPUS * STACK_SIZE) + STACK_SIZE) ;
|
||||
}
|
||||
_estack = .;
|
||||
_heap = .;
|
||||
|
@@ -1,6 +1,7 @@
|
||||
#ifndef DEVICE_H
|
||||
#define DEVICE_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/resource.h>
|
||||
|
||||
struct device;
|
||||
|
@@ -1,8 +1,6 @@
|
||||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses USE_NORMAL_IMAGE
|
||||
uses ENABLE_IOMMU
|
||||
#
|
||||
#
|
||||
###
|
||||
@@ -34,15 +32,11 @@ ldscript /cpu/i386/entry32.lds
|
||||
### Build our reset vector (This is where linuxBIOS is entered)
|
||||
###
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript /cpu/i386/reset16.lds
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript /cpu/i386/reset16.lds
|
||||
else
|
||||
print "NO FALLBACK USED!"
|
||||
end
|
||||
|
||||
if USE_NORMAL_IMAGE
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript /cpu/i386/reset32.lds
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript /cpu/i386/reset32.lds
|
||||
end
|
||||
#
|
||||
#### Should this be in the northbridge code?
|
||||
@@ -76,15 +70,6 @@ end
|
||||
mainboardinit cpu/k8/earlymtrr.inc
|
||||
#
|
||||
#
|
||||
###
|
||||
### Only the bootstrap cpu makes it here.
|
||||
### Failover if we need to
|
||||
###
|
||||
#
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
|
||||
end
|
||||
#
|
||||
####
|
||||
#### O.k. We aren't just an intermediary anymore!
|
||||
####
|
||||
@@ -94,10 +79,6 @@ end
|
||||
###
|
||||
##option MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
#default MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
|
||||
#if DISABLE_WATCHDOG
|
||||
# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
|
||||
#end
|
||||
#
|
||||
if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
|
||||
#
|
||||
@@ -118,13 +99,6 @@ end
|
||||
mainboardinit ./auto.inc
|
||||
#
|
||||
###
|
||||
### Setup RAM
|
||||
###
|
||||
mainboardinit ram/ramtest.inc
|
||||
mainboardinit southbridge/amd/amd8111/smbus.inc
|
||||
mainboardinit sdram/generic_dump_spd.inc
|
||||
#
|
||||
###
|
||||
### Include the secondary Configuration files
|
||||
###
|
||||
northbridge amd/amdk8
|
||||
@@ -142,4 +116,3 @@ cpu p6 end
|
||||
cpu k7 end
|
||||
cpu k8 end
|
||||
|
||||
option ENABLE_IOMMU=1
|
||||
|
@@ -17,6 +17,8 @@
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "debug.c"
|
||||
|
||||
#define SIO_BASE 0x2e
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
/* Set the memreset low */
|
||||
|
@@ -5,7 +5,7 @@
|
||||
#include <device/pci_ops.h>
|
||||
|
||||
|
||||
unsigned long initial_apicid[MAX_CPUS] =
|
||||
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
|
||||
{
|
||||
0, 1, 2, 3
|
||||
};
|
||||
|
@@ -24,8 +24,6 @@ default CONFIG_UDELAY_TSC=0
|
||||
###
|
||||
### Customize our winbond superio chip for this motherboard
|
||||
###
|
||||
option SIO_BASE=0x2e
|
||||
option SIO_SYSTEM_CLK_INPUT=0
|
||||
option CONFIG_CONSOLE_SERIAL8250=0
|
||||
#
|
||||
###
|
||||
@@ -51,16 +49,11 @@ option IRQ_SLOT_COUNT=7
|
||||
##option HAVE_MP_TABLE=1
|
||||
#
|
||||
###
|
||||
### Do not build special code for the keyboard
|
||||
###
|
||||
default NO_KEYBOARD=1
|
||||
#
|
||||
###
|
||||
### Build code for SMP support
|
||||
### Only worry about 2 micro processors
|
||||
###
|
||||
##option CONFIG_SMP=1
|
||||
option MAX_CPUS=1
|
||||
option CONFIG_MAX_CPUS=1
|
||||
#
|
||||
###
|
||||
### Build code to setup a generic IOAPIC
|
||||
@@ -79,37 +72,17 @@ option CONFIG_IOAPIC=1
|
||||
option MEMORY_HOLE=0
|
||||
#
|
||||
###
|
||||
### Enable both fixed and variable MTRRS
|
||||
### When we setup MTRRs in mtrr.c
|
||||
###
|
||||
### We must setup the fixed mtrrs or we confuse SMP secondary
|
||||
### processor identification
|
||||
###
|
||||
option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
|
||||
#
|
||||
###
|
||||
### Clean up the motherboard id strings
|
||||
###
|
||||
option MAINBOARD_PART_NUMBER="Solo7"
|
||||
option MAINBOARD_VENDOR="AMD"
|
||||
#
|
||||
###
|
||||
### Let Assembly code know where on the pci bus the AMD southbridge is
|
||||
###
|
||||
option AMD8111_DEV=0x3800
|
||||
#
|
||||
###
|
||||
### Call the final_mainboard_fixup function
|
||||
###
|
||||
option FINAL_MAINBOARD_FIXUP=1
|
||||
#
|
||||
###
|
||||
### Figure out which type of linuxBIOS image to build
|
||||
### If we aren't a fallback image we must be a normal image
|
||||
### This is useful for optional includes
|
||||
###
|
||||
default USE_FALLBACK_IMAGE=0
|
||||
option USE_NORMAL_IMAGE=(! USE_FALLBACK_IMAGE)
|
||||
#
|
||||
####
|
||||
#### LinuxBIOS layout values
|
||||
@@ -144,8 +117,7 @@ default FALLBACK_SIZE=65536
|
||||
if USE_FALLBACK_IMAGE
|
||||
option ROM_SECTION_SIZE = FALLBACK_SIZE
|
||||
option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
|
||||
end
|
||||
if USE_NORMAL_IMAGE
|
||||
else
|
||||
option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
|
||||
option ROM_SECTION_OFFSET= 0
|
||||
end
|
||||
@@ -177,13 +149,6 @@ option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
|
||||
##option XIP_ROM_BASE=0xffff8000
|
||||
#
|
||||
###
|
||||
### Compute where the SMP startup code needs to live
|
||||
### FIXME I don't see how to make this work for the normal image....
|
||||
###
|
||||
option START_CPU_SEG=0xf0000
|
||||
#
|
||||
#
|
||||
###
|
||||
### Set all of the defaults for an x86 architecture
|
||||
###
|
||||
#
|
||||
@@ -217,13 +182,11 @@ ldscript /cpu/i386/entry32.lds
|
||||
### Build our reset vector (This is where linuxBIOS is entered)
|
||||
###
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript /cpu/i386/reset16.lds
|
||||
end
|
||||
|
||||
if USE_NORMAL_IMAGE
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript /cpu/i386/reset32.lds
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript /cpu/i386/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript /cpu/i386/reset32.lds
|
||||
end
|
||||
#
|
||||
#### Should this be in the northbridge code?
|
||||
@@ -251,15 +214,6 @@ end
|
||||
mainboardinit cpu/k8/earlymtrr.inc
|
||||
#
|
||||
#
|
||||
###
|
||||
### Only the bootstrap cpu makes it here.
|
||||
### Failover if we need to
|
||||
###
|
||||
#
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
|
||||
end
|
||||
#
|
||||
####
|
||||
#### O.k. We aren't just an intermediary anymore!
|
||||
####
|
||||
@@ -269,10 +223,6 @@ end
|
||||
###
|
||||
##option MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
#default MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
|
||||
#if DISABLE_WATCHDOG
|
||||
# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
|
||||
#end
|
||||
#
|
||||
###
|
||||
### Setup the serial port
|
||||
@@ -293,13 +243,6 @@ makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
|
||||
mainboardinit ./auto.inc
|
||||
#
|
||||
###
|
||||
### Setup RAM
|
||||
###
|
||||
mainboardinit ram/ramtest.inc
|
||||
mainboardinit southbridge/amd/amd8111/smbus.inc
|
||||
mainboardinit sdram/generic_dump_spd.inc
|
||||
#
|
||||
###
|
||||
### Include the secondary Configuration files
|
||||
###
|
||||
northbridge amd/amdk8
|
||||
|
@@ -5,7 +5,7 @@
|
||||
#include <device/pci_ops.h>
|
||||
|
||||
|
||||
unsigned long initial_apicid[MAX_CPUS] =
|
||||
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
|
||||
{
|
||||
0
|
||||
};
|
||||
|
@@ -1,168 +1,286 @@
|
||||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses USE_NORMAL_IMAGE
|
||||
uses AMD8111_DEV
|
||||
uses MAINBOARD
|
||||
uses ARCH
|
||||
uses ENABLE_IOMMU
|
||||
#
|
||||
#
|
||||
uses FALLBACK_SIZE
|
||||
uses ROM_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_IMAGE_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_STREAM_START
|
||||
uses PAYLOAD_SIZE
|
||||
uses _ROMBASE
|
||||
uses XIP_ROM_SIZE
|
||||
uses XIP_ROM_BASE
|
||||
|
||||
###
|
||||
### Set all of the defaults for an x86 architecture
|
||||
### Build options
|
||||
###
|
||||
#
|
||||
#
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
option HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from linuxBIOS
|
||||
##
|
||||
option HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
option HAVE_PIRQ_TABLE=1
|
||||
option IRQ_SLOT_COUNT=7
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
option HAVE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
option HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
option CONFIG_SMP=1
|
||||
option CONFIG_MAX_CPUS=2
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
option CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
option MAINBOARD_PART_NUMBER="HDAMA"
|
||||
option MAINBOARD_VENDOR="ARIMA"
|
||||
|
||||
###
|
||||
### Build the objects we have code for in this directory.
|
||||
### LinuxBIOS layout values
|
||||
###
|
||||
##object mainboard.o
|
||||
driver mainboard.o
|
||||
object static_devices.o
|
||||
if HAVE_MP_TABLE object mptable.o end
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
#
|
||||
|
||||
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||
option ROM_SIZE = 524288
|
||||
|
||||
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||
option ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
option STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
option HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
option USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||
|
||||
##
|
||||
## Compute the location and size of where this firmware image
|
||||
## (linuxBIOS plus bootloader) will live in the boot rom chip.
|
||||
##
|
||||
if USE_FALLBACK_IMAGE
|
||||
option ROM_SECTION_SIZE = FALLBACK_SIZE
|
||||
option ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
|
||||
else
|
||||
option ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
|
||||
option ROM_SECTION_OFFSET = 0
|
||||
end
|
||||
|
||||
##
|
||||
## Compute the start location and size size of
|
||||
## The linuxBIOS bootloader.
|
||||
##
|
||||
option PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
|
||||
option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
|
||||
option CONFIG_ROM_STREAM = 1
|
||||
|
||||
##
|
||||
## Compute where this copy of linuxBIOS will start in the boot rom
|
||||
##
|
||||
option _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
|
||||
|
||||
##
|
||||
## Compute a range of ROM that can cached to speed up linuxBIOS,
|
||||
## execution speed.
|
||||
##
|
||||
## XIP_ROM_SIZE must be a power of 2.
|
||||
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
|
||||
##
|
||||
option XIP_ROM_SIZE=65536
|
||||
option XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
#cpu k8 end
|
||||
#
|
||||
###
|
||||
### Build our 16 bit and 32 bit linuxBIOS entry code
|
||||
###
|
||||
mainboardinit cpu/i386/entry16.inc
|
||||
mainboardinit cpu/i386/entry32.inc
|
||||
ldscript /cpu/i386/entry16.lds
|
||||
ldscript /cpu/i386/entry32.lds
|
||||
#
|
||||
###
|
||||
### Build our reset vector (This is where linuxBIOS is entered)
|
||||
###
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript /cpu/i386/reset16.lds
|
||||
else
|
||||
print "NO FALLBACK USED!"
|
||||
end
|
||||
|
||||
if USE_NORMAL_IMAGE
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript /cpu/i386/reset32.lds
|
||||
end
|
||||
#
|
||||
#### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
#
|
||||
###
|
||||
### Include an id string (For safe flashing)
|
||||
###
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
#
|
||||
####
|
||||
#### This is the early phase of linuxBIOS startup
|
||||
#### Things are delicate and we test to see if we should
|
||||
#### failover to another image.
|
||||
####
|
||||
#option MAX_REBOOT_CNT=2
|
||||
if USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
#
|
||||
###
|
||||
### Setup our mtrrs
|
||||
###
|
||||
mainboardinit cpu/k8/earlymtrr.inc
|
||||
###
|
||||
### Only the bootstrap cpu makes it here.
|
||||
### Failover if we need to
|
||||
###
|
||||
#
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit ./failover.inc
|
||||
# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
|
||||
end
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
#
|
||||
#
|
||||
###
|
||||
### Setup the serial port
|
||||
###
|
||||
#mainboardinit superiowinbond/w83627hf/setup_serial.inc
|
||||
mainboardinit pc80/serial.inc
|
||||
mainboardinit arch/i386/lib/console.inc
|
||||
#
|
||||
####
|
||||
#### O.k. We aren't just an intermediary anymore!
|
||||
####
|
||||
#
|
||||
###
|
||||
### When debugging disable the watchdog timer
|
||||
###
|
||||
##option MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
#default MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
|
||||
#if DISABLE_WATCHDOG
|
||||
# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
|
||||
#end
|
||||
#
|
||||
#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
|
||||
#
|
||||
###
|
||||
### Romcc output
|
||||
###
|
||||
#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
|
||||
#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
|
||||
#mainboardinit .failover.inc
|
||||
#object mainboard.o
|
||||
driver mainboard.o
|
||||
#object static_devices.o
|
||||
if HAVE_MP_TABLE object mptable.o end
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
object reset.o
|
||||
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(MAINBOARD)/failover.c"
|
||||
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "./romcc ./failover.E"
|
||||
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
|
||||
depends "./failover.E ./romcc"
|
||||
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(MAINBOARD)/auto.c"
|
||||
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "./romcc ./auto.E"
|
||||
depends "./auto.E ./romcc"
|
||||
action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit linuxBIOS entry code
|
||||
##
|
||||
mainboardinit cpu/i386/entry16.inc
|
||||
mainboardinit cpu/i386/entry32.inc
|
||||
ldscript /cpu/i386/entry16.lds
|
||||
ldscript /cpu/i386/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where linuxBIOS is entered)
|
||||
##
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript /cpu/i386/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript /cpu/i386/reset32.lds
|
||||
end
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## Setup our mtrrs
|
||||
##
|
||||
mainboardinit cpu/k8/earlymtrr.inc
|
||||
|
||||
###
|
||||
### This is the early phase of linuxBIOS startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/k8/enable_mmx_sse.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/k8/disable_mmx_sse.inc
|
||||
#
|
||||
###
|
||||
### Setup RAM
|
||||
###
|
||||
#mainboardinit ram/ramtest.inc
|
||||
#mainboardinit southbridge/amd/amd8111/smbus.inc
|
||||
#mainboardinit sdram/generic_dump_spd.inc
|
||||
#
|
||||
###
|
||||
### Include the secondary Configuration files
|
||||
###
|
||||
northbridge amd/amdk8
|
||||
end
|
||||
southbridge amd/amd8111 "amd8111"
|
||||
end
|
||||
southbridge amd/amd8131 "amd8131"
|
||||
end
|
||||
#mainboardinit archi386/smp/secondary.inc
|
||||
superio NSC/pc87360
|
||||
register "com1" = "{1}"
|
||||
register "lpt" = "{1}"
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
##dir /src/superio/winbond/w83627hf
|
||||
#dir /cpu/k8
|
||||
cpu k8 "cpu0"
|
||||
register "up" = "{.chip = &amd8111, .ht_width=8, .ht_speed=200}"
|
||||
|
||||
northbridge amd/amdk8 "mc0"
|
||||
#pci 0:18.0
|
||||
#pci 0:18.0
|
||||
#pci 0:18.0
|
||||
#pci 0:18.1
|
||||
#pci 0:18.2
|
||||
#pci 0:18.3
|
||||
southbridge amd/amd8131 "amd8131"
|
||||
#pci 0:0.0
|
||||
#pci 0:0.1
|
||||
#pci 0:1.0
|
||||
#pci 0:1.1
|
||||
end
|
||||
southbridge amd/amd8111 "amd8111"
|
||||
#pci 0:0.0
|
||||
#pci 0:1.0
|
||||
#pci 0:1.1
|
||||
#pci 0:1.2
|
||||
#pci 0:1.3
|
||||
#pci 0:1.5 off
|
||||
#pci 0:1.6 off
|
||||
superio NSC/pc87360
|
||||
#pnp 1:2e.0
|
||||
#pnp 1:2e.1
|
||||
#pnp 1:2e.2
|
||||
#pnp 1:2e.3
|
||||
#pnp 1:2e.4
|
||||
#pnp 1:2e.5
|
||||
#pnp 1:2e.6
|
||||
#pnp 1:2e.7
|
||||
#pnp 1:2e.8
|
||||
#pnp 1:2e.9
|
||||
#pnp 1:2e.a
|
||||
register "com1" = "{1, 0, 0x3f8, 4}"
|
||||
register "lpt" = "{1}"
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
northbridge amd/amdk8 "mc1"
|
||||
#pci 0:19.0
|
||||
#pci 0:19.0
|
||||
#pci 0:19.0
|
||||
#pci 0:19.1
|
||||
#pci 0:19.2
|
||||
#pci 0:19.3
|
||||
end
|
||||
|
||||
cpu k8 "cpu0"
|
||||
register "up" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
|
||||
end
|
||||
|
||||
cpu k8 "cpu1"
|
||||
end
|
||||
|
||||
option ENABLE_IOMMU=1
|
||||
##
|
||||
## Include the old serial code for those few places that still need it.
|
||||
##
|
||||
mainboardinit pc80/serial.inc
|
||||
mainboardinit arch/i386/lib/console.inc
|
||||
|
||||
|
@@ -1,6 +1,4 @@
|
||||
#define ASSEMBLY 1
|
||||
#define MAXIMUM_CONSOLE_LOGLEVEL 9
|
||||
#define DEFAULT_CONSOLE_LOGLEVEL 9
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
@@ -20,6 +18,8 @@
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "debug.c"
|
||||
|
||||
#define SIO_BASE 0x2e
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
/* Set the memreset low */
|
||||
@@ -151,7 +151,7 @@ static void pc87360_enable_serial(void)
|
||||
}
|
||||
|
||||
#define FIRST_CPU 1
|
||||
#define SECOND_CPU 0
|
||||
#define SECOND_CPU 1
|
||||
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
|
||||
static void main(void)
|
||||
{
|
||||
@@ -209,7 +209,7 @@ static void main(void)
|
||||
memreset_setup();
|
||||
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||
|
||||
#if 1
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
#endif
|
||||
#if 0
|
||||
@@ -227,13 +227,21 @@ static void main(void)
|
||||
#endif
|
||||
#if 0
|
||||
ram_check(0x00000000, msr.lo);
|
||||
#else
|
||||
#if TOTAL_CPUS < 2
|
||||
/* Check 16MB of memory @ 0*/
|
||||
ram_check(0x00000000, 0x01000);
|
||||
#else
|
||||
/* Check 16MB of memory @ 2GB */
|
||||
ram_check(0x80000000, 0x81000000);
|
||||
#endif
|
||||
#if 0
|
||||
static const struct {
|
||||
unsigned long lo, hi;
|
||||
} check_addrs[] = {
|
||||
/* Check 16MB of memory @ 0*/
|
||||
{ 0x00000000, 0x01000000 },
|
||||
#if TOTAL_CPUS > 1
|
||||
/* Check 16MB of memory @ 2GB */
|
||||
{ 0x80000000, 0x81000000 },
|
||||
#endif
|
||||
};
|
||||
int i;
|
||||
for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
|
||||
ram_check(check_addrs[i].lo, check_addrs[i].hi);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
@@ -9,7 +9,7 @@
|
||||
#include "chip.h"
|
||||
|
||||
|
||||
unsigned long initial_apicid[MAX_CPUS] =
|
||||
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
|
||||
{
|
||||
0, 1,
|
||||
};
|
||||
|
@@ -1,11 +1,8 @@
|
||||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses USE_NORMAL_IMAGE
|
||||
uses AMD8111_DEV
|
||||
uses MAINBOARD
|
||||
uses ARCH
|
||||
uses ENABLE_IOMMU
|
||||
#
|
||||
#
|
||||
###
|
||||
@@ -37,15 +34,11 @@ ldscript /cpu/i386/entry32.lds
|
||||
### Build our reset vector (This is where linuxBIOS is entered)
|
||||
###
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript /cpu/i386/reset16.lds
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript /cpu/i386/reset16.lds
|
||||
else
|
||||
print "NO FALLBACK USED!"
|
||||
end
|
||||
|
||||
if USE_NORMAL_IMAGE
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript /cpu/i386/reset32.lds
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript /cpu/i386/reset32.lds
|
||||
end
|
||||
#
|
||||
#### Should this be in the northbridge code?
|
||||
@@ -78,7 +71,6 @@ mainboardinit cpu/k8/earlymtrr.inc
|
||||
#
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit ./failover.inc
|
||||
# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
|
||||
end
|
||||
|
||||
#
|
||||
@@ -99,10 +91,6 @@ mainboardinit arch/i386/lib/console.inc
|
||||
###
|
||||
##option MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
#default MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
|
||||
#if DISABLE_WATCHDOG
|
||||
# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
|
||||
#end
|
||||
#
|
||||
#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
|
||||
#
|
||||
@@ -135,13 +123,6 @@ mainboardinit ./auto.inc
|
||||
mainboardinit cpu/k8/disable_mmx_sse.inc
|
||||
#
|
||||
###
|
||||
### Setup RAM
|
||||
###
|
||||
#mainboardinit ram/ramtest.inc
|
||||
#mainboardinit southbridge/amd/amd8111/smbus.inc
|
||||
#mainboardinit sdram/generic_dump_spd.inc
|
||||
#
|
||||
###
|
||||
### Include the secondary Configuration files
|
||||
###
|
||||
northbridge amd/amdk8
|
||||
@@ -165,4 +146,3 @@ end
|
||||
cpu k8 "cpu1"
|
||||
end
|
||||
|
||||
option ENABLE_IOMMU=1
|
||||
|
@@ -20,6 +20,8 @@
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "debug.c"
|
||||
|
||||
#define SIO_BASE 0x2e
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
/* Set the memreset low */
|
||||
|
@@ -9,7 +9,7 @@
|
||||
#include "chip.h"
|
||||
|
||||
|
||||
unsigned long initial_apicid[MAX_CPUS] =
|
||||
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
|
||||
{
|
||||
0, 1,
|
||||
};
|
||||
|
@@ -1,11 +1,8 @@
|
||||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses USE_NORMAL_IMAGE
|
||||
uses AMD8111_DEV
|
||||
uses MAINBOARD
|
||||
uses ARCH
|
||||
uses ENABLE_IOMMU
|
||||
#
|
||||
#
|
||||
###
|
||||
@@ -46,15 +43,11 @@ ldscript /cpu/i386/entry32.lds
|
||||
### Build our reset vector (This is where linuxBIOS is entered)
|
||||
###
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript /cpu/i386/reset16.lds
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript /cpu/i386/reset16.lds
|
||||
else
|
||||
# print "NO FALLBACK USED!"
|
||||
end
|
||||
|
||||
if USE_NORMAL_IMAGE
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript /cpu/i386/reset32.lds
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript /cpu/i386/reset32.lds
|
||||
end
|
||||
#
|
||||
#### Should this be in the northbridge code?
|
||||
@@ -87,7 +80,6 @@ mainboardinit cpu/k8/earlymtrr.inc
|
||||
#
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit ./failover.inc
|
||||
# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
|
||||
end
|
||||
|
||||
#
|
||||
@@ -108,10 +100,6 @@ mainboardinit arch/i386/lib/console.inc
|
||||
###
|
||||
##option MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
#default MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
|
||||
#if DISABLE_WATCHDOG
|
||||
# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
|
||||
#end
|
||||
#
|
||||
#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
|
||||
#
|
||||
@@ -145,13 +133,6 @@ mainboardinit ./auto.inc
|
||||
mainboardinit cpu/k8/disable_mmx_sse.inc
|
||||
#
|
||||
###
|
||||
### Setup RAM
|
||||
###
|
||||
#mainboardinit ram/ramtest.inc
|
||||
#mainboardinit southbridge/amd/amd8111/smbus.inc
|
||||
#mainboardinit sdram/generic_dump_spd.inc
|
||||
#
|
||||
###
|
||||
### Include the secondary Configuration files
|
||||
###
|
||||
northbridge amd/amdk8
|
||||
@@ -175,5 +156,3 @@ end
|
||||
|
||||
cpu k8 "cpu1"
|
||||
end
|
||||
|
||||
option ENABLE_IOMMU=1
|
||||
|
@@ -7,7 +7,7 @@
|
||||
#include "chip.h"
|
||||
//#include <part/mainboard.h>
|
||||
//#include "lsi_scsi.c"
|
||||
unsigned long initial_apicid[MAX_CPUS] =
|
||||
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
|
||||
{
|
||||
0,1
|
||||
};
|
||||
|
@@ -1,11 +1,8 @@
|
||||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses USE_NORMAL_IMAGE
|
||||
uses AMD8111_DEV
|
||||
uses MAINBOARD
|
||||
uses ARCH
|
||||
uses ENABLE_IOMMU
|
||||
#
|
||||
#
|
||||
###
|
||||
@@ -45,15 +42,11 @@ ldscript /cpu/i386/entry32.lds
|
||||
### Build our reset vector (This is where linuxBIOS is entered)
|
||||
###
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript /cpu/i386/reset16.lds
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript /cpu/i386/reset16.lds
|
||||
else
|
||||
# print "NO FALLBACK USED!"
|
||||
end
|
||||
|
||||
if USE_NORMAL_IMAGE
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript /cpu/i386/reset32.lds
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript /cpu/i386/reset32.lds
|
||||
end
|
||||
#
|
||||
#### Should this be in the northbridge code?
|
||||
@@ -86,7 +79,6 @@ mainboardinit cpu/k8/earlymtrr.inc
|
||||
#
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit ./failover.inc
|
||||
# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
|
||||
end
|
||||
|
||||
#
|
||||
@@ -107,10 +99,6 @@ mainboardinit arch/i386/lib/console.inc
|
||||
###
|
||||
##option MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
#default MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
|
||||
#if DISABLE_WATCHDOG
|
||||
# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
|
||||
#end
|
||||
#
|
||||
#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
|
||||
#
|
||||
@@ -144,13 +132,6 @@ mainboardinit ./auto.inc
|
||||
mainboardinit cpu/k8/disable_mmx_sse.inc
|
||||
#
|
||||
###
|
||||
### Setup RAM
|
||||
###
|
||||
#mainboardinit ram/ramtest.inc
|
||||
#mainboardinit southbridge/amd/amd8111/smbus.inc
|
||||
#mainboardinit sdram/generic_dump_spd.inc
|
||||
#
|
||||
###
|
||||
### Include the secondary Configuration files
|
||||
###
|
||||
northbridge amd/amdk8
|
||||
@@ -174,5 +155,3 @@ end
|
||||
|
||||
cpu k8 "cpu1"
|
||||
end
|
||||
|
||||
option ENABLE_IOMMU=1
|
||||
|
@@ -7,7 +7,7 @@
|
||||
#include "chip.h"
|
||||
//#include <part/mainboard.h>
|
||||
//#include "lsi_scsi.c"
|
||||
unsigned long initial_apicid[MAX_CPUS] =
|
||||
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
|
||||
{
|
||||
0,1
|
||||
};
|
||||
|
@@ -1,11 +1,8 @@
|
||||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses USE_NORMAL_IMAGE
|
||||
uses AMD8111_DEV
|
||||
uses MAINBOARD
|
||||
uses ARCH
|
||||
uses ENABLE_IOMMU
|
||||
#
|
||||
#
|
||||
###
|
||||
@@ -46,15 +43,11 @@ ldscript /cpu/i386/entry32.lds
|
||||
### Build our reset vector (This is where linuxBIOS is entered)
|
||||
###
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript /cpu/i386/reset16.lds
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript /cpu/i386/reset16.lds
|
||||
else
|
||||
# print "NO FALLBACK USED!"
|
||||
end
|
||||
|
||||
if USE_NORMAL_IMAGE
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript /cpu/i386/reset32.lds
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript /cpu/i386/reset32.lds
|
||||
end
|
||||
#
|
||||
#### Should this be in the northbridge code?
|
||||
@@ -87,7 +80,6 @@ mainboardinit cpu/k8/earlymtrr.inc
|
||||
#
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit ./failover.inc
|
||||
# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
|
||||
end
|
||||
|
||||
#
|
||||
@@ -108,10 +100,6 @@ mainboardinit arch/i386/lib/console.inc
|
||||
###
|
||||
##option MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
#default MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8)
|
||||
#if DISABLE_WATCHDOG
|
||||
# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
|
||||
#end
|
||||
#
|
||||
#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
|
||||
#
|
||||
@@ -145,13 +133,6 @@ mainboardinit ./auto.inc
|
||||
mainboardinit cpu/k8/disable_mmx_sse.inc
|
||||
#
|
||||
###
|
||||
### Setup RAM
|
||||
###
|
||||
#mainboardinit ram/ramtest.inc
|
||||
#mainboardinit southbridge/amd/amd8111/smbus.inc
|
||||
#mainboardinit sdram/generic_dump_spd.inc
|
||||
#
|
||||
###
|
||||
### Include the secondary Configuration files
|
||||
###
|
||||
northbridge amd/amdk8
|
||||
@@ -178,5 +159,3 @@ end
|
||||
cpu k8 "cpu1"
|
||||
end
|
||||
|
||||
option ENABLE_IOMMU=0
|
||||
|
||||
|
@@ -7,7 +7,7 @@
|
||||
#include "chip.h"
|
||||
//#include <part/mainboard.h>
|
||||
//#include "lsi_scsi.c"
|
||||
unsigned long initial_apicid[MAX_CPUS] =
|
||||
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
|
||||
{
|
||||
0,1
|
||||
};
|
||||
|
@@ -157,7 +157,7 @@ static void enable_routing(u8 node)
|
||||
print_debug(" done.\r\n");
|
||||
}
|
||||
|
||||
#if MAX_CPUS > 1
|
||||
#if CONFIG_MAX_CPUS > 1
|
||||
|
||||
static void rename_temp_node(u8 node)
|
||||
{
|
||||
@@ -290,7 +290,7 @@ static void setup_remote_node(u8 node, u8 cpus)
|
||||
|
||||
#endif
|
||||
|
||||
#if MAX_CPUS > 2
|
||||
#if CONFIG_MAX_CPUS > 2
|
||||
static void setup_temp_node(u8 node, u8 cpus)
|
||||
{
|
||||
u8 row;
|
||||
@@ -306,7 +306,7 @@ static u8 setup_uniprocessor(void)
|
||||
return 1;
|
||||
}
|
||||
|
||||
#if MAX_CPUS > 1
|
||||
#if CONFIG_MAX_CPUS > 1
|
||||
static u8 setup_smp(void)
|
||||
{
|
||||
u8 cpus=2;
|
||||
@@ -332,7 +332,7 @@ static u8 setup_smp(void)
|
||||
|
||||
clear_temp_row(0); /* delete temporary connection */
|
||||
|
||||
#if MAX_CPUS > 2
|
||||
#if CONFIG_MAX_CPUS > 2
|
||||
cpus=4;
|
||||
|
||||
/* Setup and check temporary connection from Node 0 to Node 2 */
|
||||
@@ -386,7 +386,7 @@ static u8 setup_smp(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if MAX_CPUS > 1
|
||||
#if CONFIG_MAX_CPUS > 1
|
||||
static unsigned detect_mp_capabilities(unsigned cpus)
|
||||
{
|
||||
unsigned node, row, mask;
|
||||
@@ -479,7 +479,7 @@ static int setup_coherent_ht_domain(void)
|
||||
|
||||
enable_bsp_routing();
|
||||
|
||||
#if MAX_CPUS == 1
|
||||
#if CONFIG_MAX_CPUS == 1
|
||||
cpus=setup_uniprocessor();
|
||||
#else
|
||||
cpus=setup_smp();
|
||||
|
@@ -1,6 +1,8 @@
|
||||
#include <cpu/k8/mtrr.h>
|
||||
#include "raminit.h"
|
||||
|
||||
#define ENABLE_IOMMU 1
|
||||
|
||||
/* Function 2 */
|
||||
#define DRAM_CSBASE 0x40
|
||||
#define DRAM_CSMASK 0x60
|
||||
|
Reference in New Issue
Block a user