sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

device/pci_ops: Define pci_find_capability() just once

Browse Source 
Wrap the simple romstage implementation to be called
from ramstage.

Change-Id: Iadadf3d550416850d6c37233bd4eda025f4d3960
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31755
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-01-23 16:46:35 +02:00
parent dace2498ec
commit 9c0e14e7c4
7 changed files with 94 additions and 133 deletions
Download Patch File Download Diff File Expand all files Collapse all files

48
src/device/pci_early.c
View File

@@ -21,54 +21,6 @@
#include <device/pci_type.h>
#include <delay.h>
unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last)
{
unsigned pos = 0;
u16 status;
unsigned reps = 48;
status = pci_read_config16(dev, PCI_STATUS);
if (!(status & PCI_STATUS_CAP_LIST))
return 0;
u8 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
switch (hdr_type & 0x7f) {
case PCI_HEADER_TYPE_NORMAL:
case PCI_HEADER_TYPE_BRIDGE:
pos = PCI_CAPABILITY_LIST;
break;
case PCI_HEADER_TYPE_CARDBUS:
pos = PCI_CB_CAPABILITY_LIST;
break;
default:
return 0;
}
pos = pci_read_config8(dev, pos);
while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */
int this_cap;
pos &= ~3;
this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
if (this_cap == 0xff)
break;
if (!last && (this_cap == cap))
return pos;
if (last == pos)
last = 0;
pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
}
return 0;
}
unsigned pci_find_capability(pci_devfn_t dev, unsigned cap)
{
return pci_find_next_capability(dev, cap, 0);
}
static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge)
{
u16 reg16;