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soc/intel/skylake: Enable thermal subsystem depending on devicetree

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Currently SA thermal subsystem gets enabled by the option Device4Enable,
but this duplicates the devicetree on/off options. Therefore depend on
the devicetree for enablement of the SA thermal subsystem controller.

All corresponding mainboards were checked if the devicetree
configuration matches the Device4Enable setting, and missing entries
were added.

Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer
2020-07-29 20:48:08 +02:00
committed by Michael Niewöhner
parent c787a246f9
commit 9c1c00968c
23 changed files with 22 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
View File

@@ -28,7 +28,6 @@ chip soc/intel/skylake
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "SaGv" = "SaGv_Enabled"
register "PchHdaVcType" = "Vc1"
@@ -121,6 +120,7 @@ chip soc/intel/skylake
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem

2
src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
View File

@@ -4,7 +4,6 @@ chip soc/intel/skylake
register "DspEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "Device4Enable" = "0"
register "PmTimerDisabled" = "0"
register "serirq_mode" = "SERIRQ_CONTINUOUS"
@@ -117,6 +116,7 @@ chip soc/intel/skylake
}"
device domain 0 on
device pci 04.0 off end # SA thermal subsystem
device pci 17.0 on end # SATA
device pci 19.1 on end # I2C #5
device pci 1e.1 on end # UART #1

2
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@@ -29,7 +29,6 @@ chip soc/intel/skylake
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "SaGv_Enabled"
register "PmTimerDisabled" = "1"
@@ -175,6 +174,7 @@ chip soc/intel/skylake
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem

2
src/mainboard/intel/saddlebrook/devicetree.cb
View File

@@ -23,7 +23,6 @@ chip soc/intel/skylake
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "0"
register "SaGv" = "SaGv_Enabled"
register "PmTimerDisabled" = "0"
@@ -211,6 +210,7 @@ chip soc/intel/skylake
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 off end # SA thermal subsystem
device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem