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soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurable

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SOC_INTEL_CSE_SEND_EOP_EARLY breaks soft ME disable, which works using
a HECI message that needs to be sent before EOP. Make the option
configurable to allow soft ME disable on alderlake.

Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Michał Kopeć
2022-10-29 18:00:18 +02:00
committed by Felix Held
parent 34a7e66faa
commit 9c4ae9131c
2 changed files with 4 additions and 2 deletions
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2
src/soc/intel/common/block/cse/Kconfig
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@@ -46,7 +46,7 @@ config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR
to make `HECI1` device disable using private configuration register (PCR) write.
config SOC_INTEL_CSE_SEND_EOP_EARLY
bool
bool "CSE send EOP early"
depends on SOC_INTEL_COMMON_BLOCK_CSE
help
Use this config to send End Of Post (EOP) earlier through SoC code in order to