Delete mainboard/google/cheza

Work on this mainboard was abandoned and never finished. It's not really
usable in its current state, so let's get rid of it.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Documentation/security/vboot/list_vboot.md

@@ -20,7 +20,6 @@
 - Tricky (Dell Chromebox 3010)
 - Zako (HP Chromebox G1)
 - Butterfly (HP Pavilion Chromebook 14)
-- Cheza
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))

payloads/libpayload/configs/config.cheza

@@ -1,3 +0,0 @@
-CONFIG_LP_CHROMEOS=y
-CONFIG_LP_ARCH_ARM64=y
-CONFIG_LP_TIMER_ARM64_ARCH=y

src/mainboard/google/cheza/Kconfig

@@ -1,46 +0,0 @@
-
-config BOARD_GOOGLE_CHEZA_COMMON  # Umbrella option to be selected by variants
-	def_bool n
-
-if BOARD_GOOGLE_CHEZA_COMMON
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select BOARD_ROMSIZE_KB_16384
-	select COMMON_CBFS_SPI_WRAPPER
-	select EC_GOOGLE_CHROMEEC
-	select EC_GOOGLE_CHROMEEC_RTC
-	select EC_GOOGLE_CHROMEEC_SPI
-	select RTC
-	select SOC_QUALCOMM_SDM845
-	select SPI_FLASH
-	select SPI_FLASH_WINBOND
-	select MAINBOARD_HAS_CHROMEOS
-	select MAINBOARD_HAS_TPM2
-	select MAINBOARD_HAS_SPI_TPM_CR50
-
-config VBOOT
-	select EC_GOOGLE_CHROMEEC_SWITCHES
-	select VBOOT_VBNV_FLASH
-
-config MAINBOARD_DIR
-	string
-	default "google/cheza"
-
-config DRIVER_TPM_SPI_BUS
-	hex
-	default 0x5
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
-	hex
-	default 0xa
-
-##########################################################
-#### Update below when adding a new derivative board. ####
-##########################################################
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Cheza" if BOARD_GOOGLE_CHEZA
-
-endif # BOARD_GOOGLE_CHEZA_COMMON

src/mainboard/google/cheza/Kconfig.name

@@ -1,4 +0,0 @@
-
-config BOARD_GOOGLE_CHEZA
-	bool "Cheza"
-	select BOARD_GOOGLE_CHEZA_COMMON

src/mainboard/google/cheza/Makefile.inc

@@ -1,20 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += bootblock.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c

src/mainboard/google/cheza/board.h

@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H
-#define __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H
-
-#include <gpio.h>
-#include <soc/gpio.h>
-
-#define GPIO_EC_IN_RW	GPIO(11)
-#define GPIO_AP_EC_INT	GPIO(122)
-#define GPIO_AP_SUSPEND	GPIO(126)
-#define GPIO_WP_STATE	GPIO(128)
-#define GPIO_H1_AP_INT	GPIO(129)
-
-void setup_chromeos_gpios(void);
-
-#endif  /* ! __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H */

src/mainboard/google/cheza/board_info.txt

@@ -1,6 +0,0 @@
-Vendor name: Google
-Board name: Cheza Qualcomm SDM845 reference board
-Category: eval
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y

src/mainboard/google/cheza/boardid.c

@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <boardid.h>
-#include <gpio.h>
-
-uint32_t board_id(void)
-{
-	const gpio_t pins[] = {[2] = GPIO(51), [1] = GPIO(62), [0] = GPIO(38)};
-	static uint32_t id = UNDEFINED_STRAPPING_ID;
-
-	if (id == UNDEFINED_STRAPPING_ID)
-		id = gpio_base2_value(pins, ARRAY_SIZE(pins));
-
-	return id;
-}
-
-uint32_t ram_code(void)
-{
-	const gpio_t pins[] = {[1] = GPIO(147), [0] = GPIO(146)};
-	static uint32_t id = UNDEFINED_STRAPPING_ID;
-
-	if (id == UNDEFINED_STRAPPING_ID)
-		id = gpio_base2_value(pins, ARRAY_SIZE(pins));
-
-	return id;
-}
-
-uint32_t sku_id(void)
-{
-	const gpio_t pins[] = {[1] = GPIO(113), [0] = GPIO(79)};
-	static uint32_t id = UNDEFINED_STRAPPING_ID;
-
-	if (id == UNDEFINED_STRAPPING_ID)
-		id = gpio_base2_value(pins, ARRAY_SIZE(pins));
-
-	return id;
-}

src/mainboard/google/cheza/bootblock.c

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include "board.h"
-
-void bootblock_mainboard_init(void)
-{
-	setup_chromeos_gpios();
-}

src/mainboard/google/cheza/chromeos.c

@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <boot/coreboot_tables.h>
-#include <bootmode.h>
-#include "board.h"
-
-int get_write_protect_state(void)
-{
-	return !gpio_get(GPIO_WP_STATE);
-}
-
-void setup_chromeos_gpios(void)
-{
-	gpio_input_pullup(GPIO_EC_IN_RW);
-	gpio_input_pullup(GPIO_AP_EC_INT);
-	gpio_output(GPIO_AP_SUSPEND, 1);
-	gpio_input(GPIO_WP_STATE);
-	gpio_input_pullup(GPIO_H1_AP_INT);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-	struct lb_gpio chromeos_gpios[] = {
-		{GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW),
-			"EC in RW"},
-		{GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT),
-			"EC interrupt"},
-		{GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT),
-			"TPM interrupt"},
-	};
-
-	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}

src/mainboard/google/cheza/chromeos.fmd

@@ -1,42 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-FLASH@0x0 8M {
-	WP_RO 4M {
-		RO_SECTION 0x184000 {
-			BOOTBLOCK 96K
-			COREBOOT(CBFS)
-			#TODO: Move FMAP to 2M or 3M once FSG can be smaller
-			FMAP@0x180000 0x1000
-			GBB 0x2f00
-			RO_FRID 0x100
-		}
-		RO_VPD(PRESERVE) 16K
-		RO_DDR_TRAINING(PRESERVE) 8K
-		RO_LIMITS_CFG(PRESERVE) 4K
-		RO_FSG(PRESERVE)
-	}
-
-	RW_VPD(PRESERVE) 32K
-	RW_NVRAM(PRESERVE) 16K
-	RW_DDR_TRAINING(PRESERVE) 8K
-	RW_LIMITS_CFG(PRESERVE) 4K
-	RW_ELOG(PRESERVE) 4K
-	RW_SHARED 4K {
-		SHARED_DATA
-	}
-
-	RW_SECTION_A 1280K {
-		VBLOCK_A 8K
-		FW_MAIN_A(CBFS)
-		RW_FWID_A 256
-	}
-
-
-	RW_SECTION_B 1280K {
-		VBLOCK_B 8K
-		FW_MAIN_B(CBFS)
-		RW_FWID_B 256
-	}
-
-	RW_LEGACY(CBFS)
-}

src/mainboard/google/cheza/devicetree.cb

@@ -1,5 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-chip soc/qualcomm/sdm845
-	device cpu_cluster 0 on end
-end

src/mainboard/google/cheza/mainboard.c

@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <gpio.h>
-#include <soc/usb.h>
-
-static struct usb_board_data usb1_board_data = {
-	.pll_bias_control_2 = 0x28,
-	.imp_ctrl1 = 0x08,
-	.port_tune1 = 0x20,
-};
-
-static void setup_usb(void)
-{
-	/*
-	 * Primary USB is used only for DP functionality on cheza platform.
-	 * Hence Setting up only Secondary USB DWC3 controller.
-	 */
-	setup_usb_host1(&usb1_board_data);
-
-	gpio_output(GPIO(120), 1);	/* Deassert HUB_RST_L to enable hub. */
-}
-
-static void mainboard_init(struct device *dev)
-{
-	setup_usb();
-}
-
-static void mainboard_enable(struct device *dev)
-{
-	dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
-	.name = CONFIG_MAINBOARD_PART_NUMBER,
-	.enable_dev = mainboard_enable,
-};

src/mainboard/google/cheza/reset.c

@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <ec/google/chromeec/ec.h>
-#include <reset.h>
-
-/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage),
-   but this works well enough for our purposes. */
-void do_board_reset(void)
-{
-	google_chromeec_reboot(0, EC_REBOOT_COLD, 0);
-}

src/mainboard/google/cheza/romstage.c

@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/stages.h>
-#include <soc/usb.h>
-#include <soc/qclib_common.h>
-
-static void prepare_usb(void)
-{
-	/*
-	 * Do DWC3 core and phy reset. Kick these resets
-	 * off early so they get at least 1ms to settle.
-	 */
-	reset_usb1();
-}
-
-void platform_romstage_main(void)
-{
-	prepare_usb();
-
-	/* QCLib: DDR init & train */
-	qclib_load_and_run();
-}