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southbridge/intel: Remove space before/after parenthesis

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Change-Id: Id1bc0c88aeecc3f1d12964346326e5b087a2985e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25880
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS
2018-04-26 22:21:21 +02:00
committed by Patrick Georgi
parent 9ab9db0bc5
commit 9c5d4634dd
12 changed files with 26 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/intel/bd82x6x/lpc.c
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@ -239,7 +239,7 @@ static void pch_power_options(device_t dev)
reg8 &= ~(1 << 7); /* Set NMI. */ reg8 &= ~(1 << 7); /* Set NMI. */
} else { } else {
printk(BIOS_INFO, "NMI sources disabled.\n"); printk(BIOS_INFO, "NMI sources disabled.\n");
reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
} }
outb(reg8, 0x70); outb(reg8, 0x70);

2
src/southbridge/intel/fsp_bd82x6x/lpc.c
View File

@ -249,7 +249,7 @@ static void pch_power_options(device_t dev)
reg8 &= ~(1 << 7); /* Set NMI. */ reg8 &= ~(1 << 7); /* Set NMI. */
} else { } else {
printk(BIOS_INFO, "NMI sources disabled.\n"); printk(BIOS_INFO, "NMI sources disabled.\n");
reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
} }
outb(reg8, 0x70); outb(reg8, 0x70);

2
src/southbridge/intel/fsp_i89xx/lpc.c
View File

@ -249,7 +249,7 @@ static void pch_power_options(device_t dev)
reg8 &= ~(1 << 7); /* Set NMI. */ reg8 &= ~(1 << 7); /* Set NMI. */
} else { } else {
printk(BIOS_INFO, "NMI sources disabled.\n"); printk(BIOS_INFO, "NMI sources disabled.\n");
reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
} }
outb(reg8, 0x70); outb(reg8, 0x70);

2
src/southbridge/intel/fsp_rangeley/lpc.c
View File

@ -270,7 +270,7 @@ static void soc_power_options(device_t dev)
reg8 &= ~(1 << 7); /* Set NMI. */ reg8 &= ~(1 << 7); /* Set NMI. */
} else { } else {
printk(BIOS_INFO, "NMI sources disabled.\n"); printk(BIOS_INFO, "NMI sources disabled.\n");
reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
} }
outb(reg8, 0x70); outb(reg8, 0x70);

14
src/southbridge/intel/i82371eb/acpi/i82371eb.asl
View File

@ -29,11 +29,11 @@
/* 8259-compatible Programmable Interrupt Controller */ /* 8259-compatible Programmable Interrupt Controller */
Device (PIC) Device (PIC)
{ {
Name (_HID, EisaId ("PNP0000") ) Name (_HID, EisaId ("PNP0000"))
Name (_CRS, ResourceTemplate () Name (_CRS, ResourceTemplate ()
{ {
IO (Decode16, 0x0020, 0x0020, 0x01, 0x02, ) IO (Decode16, 0x0020, 0x0020, 0x01, 0x02,)
IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02, ) IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02,)
IRQNoFlags () {2} IRQNoFlags () {2}
}) })
} }
@ -41,10 +41,10 @@
/* PC-class DMA Controller */ /* PC-class DMA Controller */
Device (DMA1) Device (DMA1)
{ {
Name (_HID, EisaId ("PNP0200") ) Name (_HID, EisaId ("PNP0200"))
Name (_CRS, ResourceTemplate () Name (_CRS, ResourceTemplate ()
{ {
DMA (Compatibility, BusMaster, Transfer8, ) {4} DMA (Compatibility, BusMaster, Transfer8,) {4}
IO (Decode16, 0x0000, 0x0000, 0x01, 0x10,) IO (Decode16, 0x0000, 0x0000, 0x01, 0x10,)
IO (Decode16, 0x0080, 0x0080, 0x01, 0x11,) IO (Decode16, 0x0080, 0x0080, 0x01, 0x11,)
IO (Decode16, 0x0094, 0x0094, 0x01, 0x0C,) IO (Decode16, 0x0094, 0x0094, 0x01, 0x0C,)
@ -66,7 +66,7 @@
/* AT Real-Time Clock */ /* AT Real-Time Clock */
Device (RTC) Device (RTC)
{ {
Name (_HID, EisaId ("PNP0B00") ) Name (_HID, EisaId ("PNP0B00"))
Name (_CRS, ResourceTemplate () Name (_CRS, ResourceTemplate ()
{ {
IO (Decode16,0x0070,0x0070,0x01,0x04,) IO (Decode16,0x0070,0x0070,0x01,0x04,)
@ -86,7 +86,7 @@
/* x87-compatible Floating Point Processing Unit */ /* x87-compatible Floating Point Processing Unit */
Device (COPR) Device (COPR)
{ {
Name (_HID, EisaId ("PNP0C04") ) Name (_HID, EisaId ("PNP0C04"))
Name (_CRS, ResourceTemplate () Name (_CRS, ResourceTemplate ()
{ {
IO (Decode16,0x00F0,0x00F0,0x01,0x10,) IO (Decode16,0x00F0,0x00F0,0x01,0x10,)

2
src/southbridge/intel/i82801dx/ac97.c
View File

@ -220,7 +220,7 @@ static void ac97_modem_init(struct device *dev)
mbar = pci_read_config16(dev, MBAR) & 0xfffe; mbar = pci_read_config16(dev, MBAR) & 0xfffe;
reg16 = inw(mmbar + EXT_MODEM_ID1); reg16 = inw(mmbar + EXT_MODEM_ID1);
if ((reg16 & 0xc000) != 0xc000 ) { if ((reg16 & 0xc000) != 0xc000) {
if (reg16 & (1 << 0)) { if (reg16 & (1 << 0)) {
reg32 = inw(mmbar + VENDOR_ID2); reg32 = inw(mmbar + VENDOR_ID2);
reg32 <<= 16; reg32 <<= 16;

2
src/southbridge/intel/i82801dx/lpc.c
View File

@ -155,7 +155,7 @@ static void i82801dx_power_options(device_t dev)
reg8 &= ~(1 << 7); /* Set NMI. */ reg8 &= ~(1 << 7); /* Set NMI. */
} else { } else {
printk(BIOS_INFO, "NMI sources disabled.\n"); printk(BIOS_INFO, "NMI sources disabled.\n");
reg8 |= ( 1 << 7); /* Disable NMI. */ reg8 |= (1 << 7); /* Disable NMI. */
} }
outb(reg8, 0x70); outb(reg8, 0x70);

2
src/southbridge/intel/i82801ix/lpc.c
View File

@ -227,7 +227,7 @@ static void i82801ix_power_options(device_t dev)
reg8 &= ~(1 << 7); /* Set NMI. */ reg8 &= ~(1 << 7); /* Set NMI. */
} else { } else {
printk(BIOS_INFO, "NMI sources disabled.\n"); printk(BIOS_INFO, "NMI sources disabled.\n");
reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
} }
outb(reg8, 0x70); outb(reg8, 0x70);

2
src/southbridge/intel/i82801jx/lpc.c
View File

@ -229,7 +229,7 @@ static void i82801jx_power_options(device_t dev)
reg8 &= ~(1 << 7); /* Set NMI. */ reg8 &= ~(1 << 7); /* Set NMI. */
} else { } else {
printk(BIOS_INFO, "NMI sources disabled.\n"); printk(BIOS_INFO, "NMI sources disabled.\n");
reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
} }
outb(reg8, 0x70); outb(reg8, 0x70);

2
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -231,7 +231,7 @@ static void pch_power_options(device_t dev)
reg8 &= ~(1 << 7); /* Set NMI. */ reg8 &= ~(1 << 7); /* Set NMI. */
} else { } else {
printk(BIOS_INFO, "NMI sources disabled.\n"); printk(BIOS_INFO, "NMI sources disabled.\n");
reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
} }
outb(reg8, 0x70); outb(reg8, 0x70);

18
src/southbridge/intel/lynxpoint/acpi/serialio.asl
View File

@ -131,7 +131,7 @@ Device (SDMA)
Name (RBUF, ResourceTemplate () Name (RBUF, ResourceTemplate ()
{ {
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7}
}) })
Method (_CRS, 0, NotSerialized) Method (_CRS, 0, NotSerialized)
@ -172,7 +172,7 @@ Device (I2C0)
Name (RBUF, ResourceTemplate () Name (RBUF, ResourceTemplate ()
{ {
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7}
}) })
// DMA channels are only used if Serial IO DMA controller is enabled // DMA channels are only used if Serial IO DMA controller is enabled
@ -254,7 +254,7 @@ Device (I2C1)
Name (RBUF, ResourceTemplate () Name (RBUF, ResourceTemplate ()
{ {
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7}
}) })
// DMA channels are only used if Serial IO DMA controller is enabled // DMA channels are only used if Serial IO DMA controller is enabled
@ -333,7 +333,7 @@ Device (SPI0)
Name (RBUF, ResourceTemplate () Name (RBUF, ResourceTemplate ()
{ {
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7}
}) })
Method (_CRS, 0, NotSerialized) Method (_CRS, 0, NotSerialized)
@ -371,7 +371,7 @@ Device (SPI1)
Name (RBUF, ResourceTemplate () Name (RBUF, ResourceTemplate ()
{ {
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7}
}) })
// DMA channels are only used if Serial IO DMA controller is enabled // DMA channels are only used if Serial IO DMA controller is enabled
@ -422,7 +422,7 @@ Device (UAR0)
Name (RBUF, ResourceTemplate () Name (RBUF, ResourceTemplate ()
{ {
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13} Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {13}
}) })
// DMA channels are only used if Serial IO DMA controller is enabled // DMA channels are only used if Serial IO DMA controller is enabled
@ -473,7 +473,7 @@ Device (UAR1)
Name (RBUF, ResourceTemplate () Name (RBUF, ResourceTemplate ()
{ {
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13} Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {13}
}) })
Method (_CRS, 0, NotSerialized) Method (_CRS, 0, NotSerialized)
@ -511,7 +511,7 @@ Device (SDIO)
Name (RBUF, ResourceTemplate () Name (RBUF, ResourceTemplate ()
{ {
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {5} Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {5}
}) })
Method (_CRS, 0, NotSerialized) Method (_CRS, 0, NotSerialized)
@ -560,7 +560,7 @@ Device (GPIO)
, // ResourceSource , // ResourceSource
BAR0) BAR0)
Interrupt (ResourceConsumer, Interrupt (ResourceConsumer,
Level, ActiveHigh, Shared, , , ) {14} Level, ActiveHigh, Shared, , ,) {14}
}) })
Method (_CRS, 0, NotSerialized) Method (_CRS, 0, NotSerialized)

2
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -247,7 +247,7 @@ static void pch_power_options(device_t dev)
reg8 &= ~(1 << 7); /* Set NMI. */ reg8 &= ~(1 << 7); /* Set NMI. */
} else { } else {
printk(BIOS_INFO, "NMI sources disabled.\n"); printk(BIOS_INFO, "NMI sources disabled.\n");
reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
} }
outb(reg8, 0x70); outb(reg8, 0x70);