sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel: clean up dmi driver code

Browse Source 
1. Remove dmi.h as it's migrated as gpmr.header
2. Remove unused gpmr definitions
3. For old platforms, define DMI defintions in c code
   for less code changes.

TEST=Build
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ib340ff1ab7fd88b1e7b3860ffec055a75e562de7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Wonkyu Kim
2022-04-07 10:31:25 -07:00
committed by Felix Held
parent 211be9c031
commit 9cb5dcb40c
11 changed files with 4 additions and 65 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/ocp/deltalake/bootblock.c
View File

@@ -13,6 +13,8 @@
#include <cpxsp_dl_gpio.h>
#define ASPEED_SIO_PORT 0x2E
#define PCR_DMI_LPCIOD 0x2770
#define PCR_DMI_LPCIOE 0x2774
static void enable_espi_lpc_io_windows(void)
{

6
src/soc/intel/alderlake/bootblock/pch.c
View File

@@ -9,7 +9,6 @@
#include <device/mmio.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <intelblocks/dmi.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/gspi.h>
#include <intelblocks/lpc_lib.h>
@@ -39,11 +38,6 @@
#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_DMI_ACPIBA 0x27B4
#define PCR_DMI_ACPIBDID 0x27B8
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
static void soc_config_pwrmbase(void)
{
/*

6
src/soc/intel/cannonlake/bootblock/pch.c
View File

@@ -4,7 +4,6 @@
#include <device/mmio.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <intelblocks/dmi.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
@@ -34,11 +33,6 @@
#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_DMI_ACPIBA 0x27B4
#define PCR_DMI_ACPIBDID 0x27B8
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
static uint32_t get_pmc_reg_base(void)
{
if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))

20
src/soc/intel/common/block/include/intelblocks/dmi.h
View File

@@ -1,20 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SOC_INTEL_COMMON_BLOCK_DMI_H
#define SOC_INTEL_COMMON_BLOCK_DMI_H
#include <types.h>
#define PCR_DMI_DMICTL 0x2234
#define PCR_DMI_DMICTL_SRLOCK (1 << 31)
#define PCR_DMI_GCS 0x274C
#define PCR_DMI_GCS_BILD (1 << 0)
/*
* Takes base, size and destination ID and configures the GPMR
* for accessing the region.
*/
enum cb_err dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id);
#endif /* SOC_INTEL_COMMON_BLOCK_DMI_H */

7
src/soc/intel/common/block/include/intelblocks/lpc_lib.h
View File

@@ -25,13 +25,6 @@
#define LPC_IOE_COMA_EN (1 << 0)
#define LPC_NUM_GENERIC_IO_RANGES 4
#define PCR_DMI_LPCLGIR1 0x2730
#define PCR_DMI_LPCGMR 0x2740
#define PCR_DMI_LPCIOD 0x2770
#define PCR_DMI_LPCIOE 0x2774
/* LPC PCR configuration */
#define PCR_LPC_PRC 0x341c
#define PCR_LPC_CCE_EN 0xf

6
src/soc/intel/elkhartlake/bootblock/pch.c
View File

@@ -5,7 +5,6 @@
#include <device/device.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <intelblocks/dmi.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/gspi.h>
#include <intelblocks/lpc_lib.h>
@@ -32,11 +31,6 @@
#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_DMI_ACPIBA 0x27B4
#define PCR_DMI_ACPIBDID 0x27B8
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
static void soc_config_pwrmbase(void)
{
/*

6
src/soc/intel/icelake/bootblock/pch.c
View File

@@ -3,7 +3,6 @@
#include <device/mmio.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <intelblocks/dmi.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/gspi.h>
#include <intelblocks/lpc_lib.h>
@@ -28,11 +27,6 @@
#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_DMI_ACPIBA 0x27B4
#define PCR_DMI_ACPIBDID 0x27B8
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
static void soc_config_pwrmbase(void)
{
/*

6
src/soc/intel/jasperlake/bootblock/pch.c
View File

@@ -5,7 +5,6 @@
#include <device/mmio.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <intelblocks/dmi.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/gspi.h>
#include <intelblocks/lpc_lib.h>
@@ -32,11 +31,6 @@
#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_DMI_ACPIBA 0x27B4
#define PCR_DMI_ACPIBDID 0x27B8
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
static void soc_config_pwrmbase(void)
{
/*

1
src/soc/intel/skylake/bootblock/pch.c
View File

@@ -2,7 +2,6 @@
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <intelblocks/dmi.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/gspi.h>
#include <intelblocks/itss.h>

6
src/soc/intel/tigerlake/bootblock/pch.c
View File

@@ -11,7 +11,6 @@
#include <device/device.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <intelblocks/dmi.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/gspi.h>
#include <intelblocks/lpc_lib.h>
@@ -42,11 +41,6 @@
#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_DMI_ACPIBA 0x27B4
#define PCR_DMI_ACPIBDID 0x27B8
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
static void soc_config_pwrmbase(void)
{
/*

3
src/soc/intel/xeon_sp/pch.c
View File

@@ -3,7 +3,6 @@
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#include <intelblocks/dmi.h>
#include <intelblocks/pcr.h>
#include <intelblocks/rtc.h>
#include <intelblocks/p2sb.h>
@@ -14,6 +13,8 @@
#define PCR_DMI_ACPIBA 0x27B4
#define PCR_DMI_ACPIBDID 0x27B8
#define PCR_DMI_DMICTL 0x2234
#define PCR_DMI_DMICTL_SRLOCK (1 << 31)
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0