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Include IPQ8064 SBLs code in the coreboot bootblock

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We want the coreboot build produce an image which can be run on the
target, even if the remaining parts of the bootprom (recovery path,
read-write stages, gbb, etc.) are not available yet.

This is achieved by including the Qualcomm SBLs blob in the bootblock.

CQ-DEPEND=CL:193518
BRANCH=None
BUG=chrome-os-partner:27784
TEST=manual

  . run the following commands inside chroot to confirm expected image
    layout (no actual code is executed on the target yet):

   $ emerge-storm coreboot
   $ \od -Ax -t x1 -v   /build/storm/firmware/coreboot.rom  2>/dev/null  | head -1
   000000 d1 dc 4b 84 34 10 d7 73 15 00 00 00 ff ff ff ff
   $ \od -Ax -t x1 -v   /build/storm/firmware/coreboot.rom  | grep 220000
   220000 05 00 00 00 03 00 00 00 00 00 00 00 00 00 01 2a

Original-Change-Id: I10e8b81c7bd90e4550a027573ad3a26c38c3808a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/193540
(cherry picked from commit 64e193974ee448f78e0a5775a440094901590afb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Idbdbeb9d229eff94a7a94af5dc4844a295458200
Reviewed-on: http://review.coreboot.org/7262
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Vadim Bendebury
2014-04-07 18:59:53 -07:00
committed by Marc Jones
parent bf04edaba7
commit 9cb70ae31f
3 changed files with 23 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/storm/Kconfig
View File

@@ -22,7 +22,7 @@ if BOARD_GOOGLE_STORM
config BOARD_SPECIFIC_OPTIONS # dummy config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y def_bool y
select SOC_QC_IPQ806X select SOC_QC_IPQ806X
select BOARD_ROMSIZE_KB_1024 select BOARD_ROMSIZE_KB_4096
config MAINBOARD_DIR config MAINBOARD_DIR
string string

8
src/soc/qualcomm/ipq806x/Kconfig
View File

@@ -13,11 +13,11 @@ config BOOTBLOCK_ROM_OFFSET
config CBFS_HEADER_ROM_OFFSET config CBFS_HEADER_ROM_OFFSET
hex "offset of master CBFS header in ROM" hex "offset of master CBFS header in ROM"
default 0x18000 default 0x221000
config CBFS_ROM_OFFSET config CBFS_ROM_OFFSET
hex "offset of CBFS data in ROM" hex "offset of CBFS data in ROM"
default 0x18080 default 0x221080
config MBN_ENCAPSULATION config MBN_ENCAPSULATION
depends on USE_BLOBS depends on USE_BLOBS
@@ -34,7 +34,7 @@ config SBL_BLOB
vendor. vendor.
config BOOTBLOCK_BASE config BOOTBLOCK_BASE
hex "64K bytes left for TZBSP" hex "256K bytes left for TZBSP"
default 0x2a010000 default 0x2a040000
endif endif

23
src/soc/qualcomm/ipq806x/Makefile.inc
View File

@@ -7,12 +7,25 @@ romstage-y += timer.c
ramstage-y += cbfs.c ramstage-y += cbfs.c
ramstage-y += timer.c ramstage-y += timer.c
ifeq ($(CONFIG_MBN_ENCAPSULATION),y) ifeq ($(CONFIG_USE_BLOBS),y)
$(objcbfs)/%.bin: $(objcbfs)/%.elf # Generate the actual coreboot bootblock code
$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
@printf " OBJCOPY $(subst $(obj)/,,$(@))\n" @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
$(OBJCOPY_bootblock) -O binary $< $@.prembn $(OBJCOPY_bootblock) -O binary $< $@.tmp
@printf " ADD MBN $(subst $(obj)/,,$(@))\n"
./util/ipqheader/ipqheader.py $(CONFIG_BOOTBLOCK_BASE) $@.prembn $@.tmp
@mv $@.tmp $@ @mv $@.tmp $@
# Add MBN header to allow SBL3 to start coreboot bootblock
$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw
@printf " ADD MBN $(subst $(obj)/,,$(@))\n"
./util/ipqheader/ipqheader.py $(CONFIG_BOOTBLOCK_BASE) $< $@.tmp
@mv $@.tmp $@
# Create a complete bootblock which will start up the system
$(objcbfs)/bootblock.bin: ./$(call strip_quotes,$(CONFIG_SBL_BLOB)) \
$(objcbfs)/bootblock.mbn
@printf " CAT $(subst $(obj)/,,$(@))\n"
@cat $^ > $@.tmp
@mv $@.tmp $@
endif endif