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soc/intel/common/pch: Add pch lockdown code

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pch lockdown functionality can be used by supported PCH.
Right now pch lockdown functionality is applied for SPT
(Skylake SOC) and CNP(Cannon Lake SOC) PCH.

BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL and CNL platform.

Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik
2018-05-28 16:12:03 +05:30
committed by Martin Roth
parent 6994bfefb5
commit 9cd99a1524
9 changed files with 195 additions and 146 deletions
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9
src/soc/intel/skylake/chip_fsp20.c
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@ -30,6 +30,7 @@
#include <fsp/api.h>
#include <fsp/util.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <romstage_handoff.h>
#include <soc/acpi.h>
#include <soc/intel/common/vbt.h>
@ -211,14 +212,6 @@ static void soc_enable(struct device *dev)
dev->ops = &cpu_bus_ops;
}
static int get_lockdown_config(void)
{
const struct soc_intel_common_config *soc_config;
soc_config = chip_get_common_soc_structure();
return soc_config->chipset_lockdown;
}
struct chip_operations soc_intel_skylake_ops = {
CHIP_NAME("Intel 6th Gen")
.enable_dev = &soc_enable,