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google/kahlee: Fix GPIO ASL

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Use a single define and set the CROS GPIO ASL device to match the
Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN
field in the GPIO ASL. This addresses the TEST indicated below.

BUG=b:65597554
BRANCH=none
TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030.

Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marc Jones
2017-09-20 17:09:19 -06:00
committed by Aaron Durbin
parent 469c01ebd2
commit 9cffe25ce0
3 changed files with 14 additions and 9 deletions
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6
src/mainboard/google/kahlee/chromeos.c
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@@ -21,7 +21,7 @@
#include <gpio.h>
/* SPI Write protect */
#define CROS_WP_GPIO GPIO_122
#define CROS_WP_GPIO GPIO_142
void fill_lb_gpios(struct lb_gpios *gpios)
{
@@ -40,8 +40,8 @@ int get_write_protect_state(void)
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(CROS_WP_GPIO, GPIO_DEVICE_NAME),
};
void mainboard_chromeos_acpi_generate(void)