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Fixes from AMD. Tested to build on rumba and olpc, and builds.

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Tested to booting linux on olpc, and boots. 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
2006-06-20 03:53:54 +00:00
parent 1f96360315
commit 9d0b30dd2b
2 changed files with 83 additions and 98 deletions
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179
src/cpu/amd/model_gx2/cpubug.c
View File

@@ -90,7 +90,7 @@ pcideadlock(void)
* Exit: * Exit:
* Modified: * Modified:
* *
/****************************************************************************/ ****************************************************************************/
void bug784(void) void bug784(void)
{ {
@@ -150,117 +150,102 @@ void eng1398(void)
wrmsr(MC_GLD_MSR_PM, msr); wrmsr(MC_GLD_MSR_PM, msr);
} }
/***************************************************************************
*
* CPUbugIAENG2900
*
* Clear Quest IAENG00002900, VSS 118.150
*
* BTB issue causes blue screen in windows, but the fix is required
* for all operating systems.
*
* Entry:
* Exit:
* Modified:
*
**************************************************************************/
void void
eng2900(void){ eng2900(void)
printk_err(" NOT DOING eng2900: only shown to be a windows problem\n"); {
#if 0 msr_t msr;
;************************************************************************** printk_debug("CPU_BUG:%s\n", __FUNCTION__);
;* /* Clear bit 43, disables the sysenter/sysexit in CPUID3 */
;* CPUbugIAENG2900 msr = rdmsr(0x3003);
;* msr.hi &= 0xFFFFF7FF;
;* Clear Quest IAENG00002900, VSS 118.150 wrmsr(0x3003, msr);
;*
;* BTB issue causes blue screen in windows.
;*
;* Entry:
;* Exit:
;* Modified:
;*
;**************************************************************************
CPUbugIAENG2900 PROC NEAR PUBLIC
pushad
; Clear bit 43, disables the sysenter/sysexit in CPUID3 /* change this value to zero if you need to disable this BTB SWAPSiF. */
mov ecx, 3003h if (1) {
RDMSR
and edx, 0FFFFF7FFh
WRMSR
mov cx, TOKEN_BTB_2900_SWAPSIF_ENABLE /* Disable enable_actions in DIAGCTL while setting up GLCP */
NOSTACK bx, GetNVRAMValueBX msr.hi = 0;
cmp ax, TVALUE_ENABLE msr.lo = 0;
jne bug2900exit wrmsr(MSR_GLCP + 0x005f, msr);
/* Changing DBGCLKCTL register to GeodeLink */
msr.hi = 0;
msr.lo = 0;
wrmsr(MSR_GLCP + 0x0016, msr);
;Disable enable_actions in DIAGCTL while setting up GLCP msr.hi = 0;
mov ecx, MSR_GLCP + 005fh msr.lo = 2;
xor edx, edx wrmsr(MSR_GLCP + 0x0016, msr);
xor eax, eax
WRMSR
;Changing DBGCLKCTL register to GeodeLink /* The code below sets up the CPU to stall for 4 GeodeLink
mov ecx, MSR_GLCP + 0016h * clocks when CPU is snooped. Because setting XSTATE to 0
xor edx, edx * overrides any other XSTATE action, the code will always
xor eax, eax * stall for 4 GeodeLink clocks after a snoop request goes
WRMSR * away even if it occured a clock or two later than a
* different snoop; the stall signal will never 'glitch high'
* for only one or two CPU clocks with this code.
*/
mov ecx, MSR_GLCP + 0016h /* Send mb0 port 3 requests to upper GeodeLink diag bits
xor edx, edx [63:32] */
mov eax, 02h msr.hi = 0;
WRMSR msr.lo = 0x80338041;
wrmsr(MSR_GLIU0 + 0x2005, msr);
;The code below sets up the RedCloud to stall for 4 GeodeLink clocks when CPU is snooped. /* set5m watches request ready from mb0 to CPU (snoop) */
;Because setting XSTATE to 0 overrides any other XSTATE action, the code will always msr.hi = 0x5ad68000;
;stall for 4 GeodeLink clocks after a snoop request goes away even if it occured a clock or two msr.lo = 0;
;later than a different snoop; the stall signal will never 'glitch high' for wrmsr(MSR_GLCP + 0x0045, msr);
;only one or two CPU clocks with this code.
;Send mb0 port 3 requests to upper GeodeLink diag bits [63:32] /* SET4M will be high when state is idle (XSTATE=11) */
mov ecx, MSR_GLIU0 + 2005h msr.hi = 0;
xor edx, edx msr.lo = 0x0140;
mov eax, 80338041h wrmsr(MSR_GLCP + 0x0044, msr);
WRMSR
;set5m watches request ready from mb0 to CPU (snoop) /* SET5n to watch for processor stalled state */
mov ecx, MSR_GLCP + 0045h msr.hi = 0x2000;
mov edx, 5ad68000h msr.lo = 0;
xor eax, eax wrmsr(MSR_GLCP + 0x004D, msr);
WRMSR
;SET4M will be high when state is idle (XSTATE=11) /* Writing action number 13: XSTATE=0 to occur when CPU is
mov ecx, MSR_GLCP + 0044h snooped unless we're stalled */
xor edx, edx msr.hi = 0;
mov eax, 0140h msr.lo = 0x00400000;
WRMSR wrmsr(MSR_GLCP + 0x0075, msr);
;SET5n to watch for processor stalled state /* Writing action number 11: inc XSTATE every GeodeLink clock
mov ecx, MSR_GLCP + 004Dh unless we're idle */
mov edx, 2000h msr.hi = 0;
xor eax, eax msr.lo = 0x30000;
WRMSR wrmsr(MSR_GLCP + 0x0073, msr);
;Writing action number 13: XSTATE=0 to occur when CPU is snooped unless we're stalled /* Writing action number 5: STALL_CPU_PIPE when exitting idle
mov ecx, MSR_GLCP + 0075h state or not in idle state */
xor edx, edx msr.hi = 0;
mov eax, 00400000h msr.lo = 0x00430000;
WRMSR wrmsr(MSR_GLCP + 0x006D, msr);
;Writing action number 11: inc XSTATE every GeodeLink clock unless we're idle /* Writing DIAGCTL Register to enable the stall action and to
mov ecx, MSR_GLCP + 0073h let set5m watch the upper GeodeLink diag bits. */
xor edx, edx msr.hi = 0;
mov eax, 30000h msr.lo = 0x80004000;
WRMSR wrmsr(MSR_GLCP + 0x005f, msr);
}
;Writing action number 5: STALL_CPU_PIPE when exitting idle state or not in idle state
mov ecx, MSR_GLCP + 006Dh
xor edx, edx
mov eax, 00430000h
WRMSR
;Writing DIAGCTL Register to enable the stall action and to let set5m watch the upper GeodeLink diag bits.
mov ecx, MSR_GLCP + 005fh
xor edx, edx
mov eax, 80004000h
WRMSR
bug2900exit:
popad
ret
CPUbugIAENG2900 ENDP
#endif
} }
void bug118253(void) void bug118253(void)

2
src/northbridge/amd/gx2/northbridgeinit.c
View File

@@ -95,7 +95,7 @@ struct msrinit GeodeLinkPriorityTable [] = {
{DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority.*/ {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority.*/
{VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority.*/ {VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority.*/
{GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority.*/ {GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority.*/
{GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0017}}, /* GLPCI Priority + PID*/ {GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0027}}, /* GLPCI Priority + PID*/
{GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID*/ {GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID*/
{VIP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* VIP PID*/ {VIP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* VIP PID*/
{AES_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0013}}, /* AES PID*/ {AES_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0013}}, /* AES PID*/